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REJ09B0180-0151
16/32
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Hardware Manual
RENESAS MCU M16C FAMILY / M32C/80 SERIES
All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).
Rev.1.51 Revision Date:Jul 31, 2008
www.renesas.com
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different part numbers, implement a system-evaluation test for each of the products.
How to Use This Manual
1. Purpose and Target Readers
This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual. The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral functions, and electrical characteristics; and usage notes. Particular attention should be paid to the precautionary notes when using the manual. These notes occur within the body of the text, at the end of each section, and in the Usage Notes section.
The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer to the text of the manual for details. The following documents apply to the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). Make sure to refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the Renesas Technology Web site. Description Document Title Document No. REJ03B0127Hardware overview and electrical characteristics M32C/87 Group 0151 (M32C/87, M32C/87A, M32C/87B) Datasheet This hardware M32C/87 Group Hardware manual Hardware specifications (pin assignments, manual (M32C/87, memory maps, peripheral function M32C/87A, specifications, electrical characteristics, timing M32C/87B) charts) and operation description Note: Refer to the application notes for details on Hardware Manual using peripheral functions. Software manual Description of CPU instruction set M32C/80 Series REJ09B0319Software Manual 0100 Available from Renesas Application note Information on using peripheral functions and Technology Web site. application examples Sample programs Information on writing programs in assembly language and C Renesas Product specifications, updates on documents, technical update etc. Document Type Datasheet
2.
Notation of Numbers and Symbols
The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word "register," "bit," or "pin" to distinguish the three categories. Examples the PM03 bit in the PM0 register P3_5 pin, VCC pin Notation of Numbers The indication "b" is appended to numeric values given in binary format. However, nothing is appended to the values of single bits. The indication "h" is appended to numeric values given in hexadecimal format. Nothing is appended to numeric values given in decimal format. Examples Binary: 11b Hexadecimal: EFA0h Decimal: 1234
(2)
3.
Register Notation
The symbols and terms used in register diagrams are described below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
*1
Symbol XXX Address XXX After Reset 00h
0
Bit Symbol
XXX0 XXX1
Bit Name
XXX bits
b1 b0
Function
1 0: XXX 0 1: XXX 1 0: Do not set to this value 1 1: XXX
RW RW RW
*2
(b2)
Unimplemented. Write 0. Read as undefined value. Reserved bit Set to 0 Function varies depending on each operation mode RW
*3 *4
(b3)
XXX4
XXX bits
RW
XXX5
WO
XXX6 XXX7 XXX bit 0: XXX 1: XXX
RW
RO
*1 Blank: Set to 0 or 1 according to the application. 0: Set to 0. 1: Set to 1. X: Unimplemented. *2 RW: Read and write. RO: Read only. WO: Write only. -: Unimplemented. *3 * Reserved bit Reserved bit. Set to specified value. *4 * Unimplemented Nothing is implemented to the bit. As the bit may be used for future functions, if necessary, set to 0. * Do not set to a value Operation is not guaranteed when a value is set. * Function varies according to the operating mode. The function of the bit varies with the peripheral function mode. Refer to the register diagram for information on the individual modes.
4.
List of Abbreviations and Acronyms
Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Full Form Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access Direct Memory Access Controller Global System for Mobile Communications High Impedance Inter Equipment bus Input/Output Infrared Data Association Least Significant Bit Most Significant Bit Non-Connection Phase Locked Loop Pulse Width Modulation Special Function Registers Subscriber Identity Module Universal Asynchronous Receiver/Transmitter Voltage Controlled Oscillator
All trademarks and registered trademarks are the property of their respective owners. IEBus is a registered trademark of NEC Electronics Corporation.
Table of Contents
Special Function Register (SFR) Page Reference ............................................................................... B - 1 1. Overview ......................................................................................................................................... 1 1.1 1.1.1 1.1.2 1.2 1.3 1.4 1.5 2. Features ..................................................................................................................................................... 1 Applications .......................................................................................................................................... 1 Specifications ........................................................................................................................................ 2 Product List .......................................................................................................................................... 6 Block Diagram .......................................................................................................................................... 8 Pin Assignments ........................................................................................................................................ 9 Pin Functions ........................................................................................................................................... 19
Central Processing Unit (CPU) ..................................................................................................... 23 2.1 General Registers .................................................................................................................................... 2.1.1 Data Registers (R0, R1, R2, and R3) .................................................................................................. 2.1.2 Address Registers (A0 and A1) .......................................................................................................... 2.1.3 Static Base Register (SB) ................................................................................................................... 2.1.4 Frame Base Register (FB) .................................................................................................................. 2.1.5 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)............................................................... 2.1.6 Interrupt Table Register (INTB) ......................................................................................................... 2.1.7 Program Counter (PC) ........................................................................................................................ 2.1.8 Flag Register (FLG) ............................................................................................................................ 2.2 High-Speed Interrupt Registers ............................................................................................................... 2.3 DMAC-Associated Registers .................................................................................................................. 24 24 24 24 24 24 24 24 24 25 25
3. 4. 5.
Memory ......................................................................................................................................... 26 Special Function Registers (SFRs) ............................................................................................... 27 Reset ............................................................................................................................................. 47 5.1 5.1.1 5.1.2 5.2 5.3 5.4 5.5 Hardware Reset 1 .................................................................................................................................... Reset at a Stable Supply Voltage ........................................................................................................ Power-on Reset ................................................................................................................................... Hardware Reset 2 (Vdet3 detection function) ......................................................................................... Software Reset ........................................................................................................................................ Watchdog Timer Reset ............................................................................................................................ Internal Registers .................................................................................................................................... 47 47 47 49 49 49 50
6.
Power Supply Voltage Detection Function .................................................................................... 51 6.1 Vdet3 Detection Function ....................................................................................................................... 6.2 Vdet4 Detection Function ....................................................................................................................... 6.2.1 Usage Notes on Vdet4 Detection Interrupt ......................................................................................... 6.3 Cold Start/Warm Start Determination Function ..................................................................................... 55 56 58 58
7. 7.1 7.2 8. 8.1
Processor Mode ............................................................................................................................ 59 Processor Mode ....................................................................................................................................... 59 Setting of Processor Mode ...................................................................................................................... 59 Bus ................................................................................................................................................ 63 Bus Settings ............................................................................................................................................. 63 A-1
8.1.1 Selecting External Address Bus ......................................................................................................... 8.1.2 Selecting External Data Bus ............................................................................................................... 8.1.3 Selecting Separate Bus/Multiplexed Bus ........................................................................................... 8.2 Bus Control ............................................................................................................................................. 8.2.1 Address Bus and Data Bus ................................................................................................................. 8.2.2 Chip-Select Output ............................................................................................................................. 8.2.3 Read/Write Output Signals ................................................................................................................. 8.2.4 Bus Timing ......................................................................................................................................... 8.2.5 ALE Output ........................................................................................................................................ 8.2.6 RDY Input .......................................................................................................................................... 8.2.7 HOLD Input ........................................................................................................................................ 8.2.8 External Bus States when Accessing Internal Space .......................................................................... 8.2.9 BCLK Output ..................................................................................................................................... 9.
64 64 64 66 66 66 68 69 77 77 78 79 79
Clock Generation Circuits ............................................................................................................. 80 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.4 9.5 9.5.1 9.5.2 9.5.3 9.6 Types of the Clock Generation Circuit ................................................................................................... 80 Main Clock ......................................................................................................................................... 89 Sub Clock ........................................................................................................................................... 90 On-Chip Oscillator Clock ................................................................................................................... 91 PLL Clock ........................................................................................................................................... 93 CPU Clock and BCLK ............................................................................................................................ 94 Peripheral Function Clock ....................................................................................................................... 94 f1, f8, f32, and f2n .............................................................................................................................. 94 fAD ..................................................................................................................................................... 94 fC32 .................................................................................................................................................... 94 fCAN .................................................................................................................................................. 94 Clock Output Function ............................................................................................................................ 95 Power Consumption Control .................................................................................................................. 96 CPU operating mode .......................................................................................................................... 96 Wait Mode .......................................................................................................................................... 98 Stop Mode ......................................................................................................................................... 101 System Clock Protect Function ............................................................................................................. 104
10. 11.
Protection .................................................................................................................................... 105 Interrupts ..................................................................................................................................... 106 Types of Interrupts ................................................................................................................................ Software Interrupts ................................................................................................................................ Undefined Instruction Interrupt ........................................................................................................ Overflow Interrupt ............................................................................................................................ BRK Interrupt ................................................................................................................................... BRK2 Interrupt ................................................................................................................................. INT Instruction Interrupt .................................................................................................................. Hardware Interrupts .............................................................................................................................. Special Interrupts .............................................................................................................................. DMACII End-of-Transfer Complete Interrupt ................................................................................. Peripheral Function Interrupt ............................................................................................................ High-Speed Interrupt ............................................................................................................................. Interrupts and Interrupt Vectors ............................................................................................................ Fixed Vector Table ........................................................................................................................... A-2 106 107 107 107 107 107 107 108 108 108 108 109 110 110
11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.3 11.3.1 11.3.2 11.3.3 11.4 11.5 11.5.1
11.5.2 11.6 11.6.1 11.6.2 11.6.3 11.6.4 11.6.5 11.6.6 11.6.7 11.6.8 11.6.9 11.7 11.8 11.9 11.10 11.11
Relocatable Vector Table ................................................................................................................. 110 Interrupt Request Acknowledgement .................................................................................................... 113 I Flag and IPL ................................................................................................................................... 113 Interrupt Control Registers and RLVL Register ............................................................................... 113 Interrupt Sequence ............................................................................................................................ 117 Interrupt Response Time .................................................................................................................. 118 IPL Change when Interrupt Request is Acknowledged .................................................................... 119 Saving a Register .............................................................................................................................. 119 Returning from Interrupt Routine ..................................................................................................... 120 Interrupt Priority ............................................................................................................................... 120 Interrupt Priority Level Decision Circuit .......................................................................................... 120 INT Interrupt ......................................................................................................................................... 122 NMI Interrupt ........................................................................................................................................ 126 Key Input Interrupt ................................................................................................................................ 126 Address Match Interrupt ....................................................................................................................... 127 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/Receive Interrupts, and INT6 to INT8 Interrupts .................................................................................................................. 128 11.11.1 IIOiIE Register ................................................................................................................................. 131 11.11.2 IIOiIR Register ................................................................................................................................. 131 11.11.3 IIOiIC (CANjIC) Register ................................................................................................................ 131 Watchdog Timer .......................................................................................................................... 134 DMAC ......................................................................................................................................... 138
12. 13.
13.1 Transfer Cycles ..................................................................................................................................... 148 13.1.1 Effect of Source and Destination Addresses .................................................................................... 148 13.1.2 Effect of the DS Register .................................................................................................................. 148 13.1.3 Effect of Software Wait State ........................................................................................................... 148 13.1.4 Effect of the RDY Signal .................................................................................................................. 148 13.2 DMA Transfer Time ............................................................................................................................. 149 13.3 Channel Priority and DMA Transfer Timing ........................................................................................ 149 14. DMACII ....................................................................................................................................... 151 DMACII Settings .................................................................................................................................. RLVL Register ................................................................................................................................. DMACII Index ................................................................................................................................. Interrupt Control Register for the Peripheral Function .................................................................... Relocatable Vector Table for the Peripheral Function ..................................................................... IRLT Bit in the IIOiIE Register (i = 0 to 11) .................................................................................... DMACII Performance ........................................................................................................................... Transfer Data ......................................................................................................................................... Memory-to-memory Transfer ........................................................................................................... Immediate Data Transfer .................................................................................................................. Calculation Transfer ......................................................................................................................... Transfer Modes ..................................................................................................................................... Single Transfer ................................................................................................................................. Burst Transfer ................................................................................................................................... Multiple Transfer .............................................................................................................................. Chain Transfer ....................................................................................................................................... End-of-Transfer Interrupt ...................................................................................................................... A-3 151 151 153 155 155 155 155 155 155 156 156 156 156 156 156 157 157
14.1 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.2 14.3 14.3.1 14.3.2 14.3.3 14.4 14.4.1 14.4.2 14.4.3 14.5 14.6
14.7 15.
Execution Time ..................................................................................................................................... 158 Timers ......................................................................................................................................... 159 161 173 174 179 181 184 191 192 193
15.1 Timer A ................................................................................................................................................. 15.1.1 Timer Mode ...................................................................................................................................... 15.1.2 Event Counter Mode ......................................................................................................................... 15.1.3 One-Shot Timer Mode ...................................................................................................................... 15.1.4 Pulse Width Modulation Mode ......................................................................................................... 15.2 Timer B ................................................................................................................................................. 15.2.1 Timer Mode ...................................................................................................................................... 15.2.2 Event Counter Mode ......................................................................................................................... 15.2.3 Pulse Period Measurement Mode, Pulse Width Measurement Mode .............................................. 16.
Three-Phase Motor Control Timer Function ............................................................................... 196 207 211 213 213 213 213
16.1 Triangular Wave Modulation Mode ...................................................................................................... 16.2 Sawtooth Wave Modulation Mode ....................................................................................................... 16.3 Short Circuit Prevention Features ......................................................................................................... 16.3.1 Prevention Against Upper/Lower Arm Short Circuit by Program Errors ........................................ 16.3.2 Arm Short Circuit Prevention Using Dead Time Timer ................................................................... 16.3.3 Forced-Cutoff Function by the NMI Input ....................................................................................... 17.
Serial Interfaces .......................................................................................................................... 214 215 225 234 242 254 259 263 269 272 278 286
17.1 UART0 to UART4 ................................................................................................................................ 17.1.1 Clock Synchronous Mode ................................................................................................................ 17.1.2 Clock Asynchronous (UART) Mode ................................................................................................ 17.1.3 Special Mode 1 (I2C Mode) ............................................................................................................. 17.1.4 Special Mode 2 ................................................................................................................................. 17.1.5 Special Mode 3 (GCI Mode) ............................................................................................................ 17.1.6 Special Mode 4 (SIM Mode) ............................................................................................................ 17.1.7 Special Mode 5 (IrDA mode) * * * UART0 ...................................................................................... 17.2 UART5 and UART6 ............................................................................................................................. 17.2.1 Clock Synchronous Mode ................................................................................................................ 17.2.2 Clock Asynchronous (UART) Mode ................................................................................................ 18.
A/D Converter ............................................................................................................................. 293 300 301 302 303 304 305 307 308 309 309 309 309 309 309
18.1 Mode Descriptions ................................................................................................................................ 18.1.1 One-Shot Mode ................................................................................................................................. 18.1.2 Repeat Mode ..................................................................................................................................... 18.1.3 Single Sweep Mode .......................................................................................................................... 18.1.4 Repeat Sweep Mode 0 ...................................................................................................................... 18.1.5 Repeat Sweep Mode 1 ...................................................................................................................... 18.1.6 Multi-Port Single Sweep Mode ........................................................................................................ 18.1.7 Multi-Port Repeat Sweep Mode 0 .................................................................................................... 18.2 Functions ............................................................................................................................................... 18.2.1 Resolution ......................................................................................................................................... 18.2.2 Sample and Hold .............................................................................................................................. 18.2.3 Trigger Select Function .................................................................................................................... 18.2.4 DMAC Operating Mode ................................................................................................................... 18.2.5 Extended Analog Input Pins ............................................................................................................. A-4
18.2.6 External Operating Amplifier (Op-Amp) Connection Mode ........................................................... 18.2.7 Power Consumption Reduce Function ............................................................................................. 18.3 Read from the AD0i Register (i = 0 to 7) .............................................................................................. 18.4 Output Impedance of Sensor Equivalent Circuit under A/D Conversion ............................................. 19. 20. 21. 22.
310 310 311 311
D/A Converter ............................................................................................................................. 313 CRC Calculation ......................................................................................................................... 316 X/Y Conversion ........................................................................................................................... 318 Intelligent I/O ............................................................................................................................... 321 Base Timer ............................................................................................................................................ Time Measurement Function (Input Capture) ....................................................................................... Prescaler Function ............................................................................................................................ Gate Function ................................................................................................................................... Waveform Generation Function (Output Compare) ............................................................................. Single-Phase Waveform Output Mode (Group 1 and Group 2) ....................................................... Phase-Delayed Waveform Output Mode (Group 1 and Group 2) .................................................... Set/Reset (SR) Waveform Output Mode (Group 1 and Group 2) .................................................... Bit Modulation PWM Output Mode (Group 2) ................................................................................ Real-Time Port Output Mode (Group 2) .......................................................................................... Parallel Real-Time Port Output Mode (Group 2) ............................................................................. GiPOj Register Value Reload Timing Select Function (i = 1, 2; j = 0 to 7) .................................... Group 0 and Group 1 Communication Function ................................................................................... Clock Synchronous Mode (Groups 0 and 1) .................................................................................... Clock Asynchronous (UART) Mode (Group 1) ............................................................................... HDLC Data Processing Mode (Group 0 and Group 1) .................................................................... Group 2 Communication Function ........................................................................................................ Variable Data Length Clock Synchronous Mode (Group 2) ............................................................ 336 342 346 348 350 354 356 358 360 362 364 367 368 379 385 389 392 398
22.1 22.2 22.2.1 22.2.2 22.3 22.3.1 22.3.2 22.3.3 22.3.4 22.3.5 22.3.6 22.3.7 22.4 22.4.1 22.4.2 22.4.3 22.5 22.5.1 23.
CAN Module ................................................................................................................................ 401 405 405 408 409 410 413 414 416 417 418 418 419 421 422 423 424 426 428
23.1 CAN-Associated Registers .................................................................................................................... 23.1.1 CANi Control Register 0 (CiCTLR0 Register) (i = 0, 1) ................................................................. 23.1.2 CANi Control Register 1 (CiCTLR1 Register) (i = 0, 1) ................................................................. 23.1.3 CANi Sleep Control Register (CiSLPR Register) (i = 0, 1) ............................................................. 23.1.4 CANi Status Register (CiSTR Register) (i = 0, 1) ........................................................................... 23.1.5 CANi Extended ID Register (CiIDR Register) (i = 0, 1) ................................................................. 23.1.6 CANi Configuration Register (CiCONR Register) (i = 0, 1) ........................................................... 23.1.7 CANi Baud Rate Prescaler (CiBRP Register) (i = 0, 1) ................................................................... 23.1.8 CANi Time Stamp Register (CiTSR Register) (i = 0, 1) .................................................................. 23.1.9 CANi Transmit Error Count Register (CiTEC Register) (i = 0, 1) .................................................. 23.1.10 CANi Receive Error Count Register (CiREC Register) (i = 0, 1) .................................................... 23.1.11 CANi Slot Interrupt Status Register (CiSISTR Register) (i = 0, 1) ................................................. 23.1.12 CANi Slot Interrupt Mask Register (CiSIMKR Register) (i = 0, 1) ................................................. 23.1.13 CANi Error Interrupt Mask Register (CiEIMKR Register) (i = 0, 1) .............................................. 23.1.14 CANi Error Interrupt Status Register (CiEISTR Register) (i = 0, 1) ............................................... 23.1.15 CANi Error Source Register (CiEFR Register) (i = 0, 1) ................................................................. 23.1.16 CANi Mode Register (CiMDR Register) (i = 0, 1) .......................................................................... 23.1.17 CANi Single-Shot Control Register (CiSSCTLR Register) (i = 0, 1) .............................................. A-5
23.1.18 CANi Single-Shot Status Register (CiSSSTR Register) (i = 0, 1) ................................................... 23.1.19 CANi Global Mask Register, CANi Local Mask Register A, and CANi Local Mask Register B (CiGMRk, CiLMARk, and CiLMBRk Registers) (i = 0,1, k = 0 to 4) ............................................ 23.1.20 CANi Message Slot j Control Register (CiMCTLj Register) (i = 0, 1, j = 0 to 15) ......................... 23.1.21 CANi Slot Buffer Select Register (CiSBS Register) (i = 0, 1) ......................................................... 23.1.22 CANi Message Slot Buffer j (i = 0, 1; j = 0, 1) ................................................................................ 23.1.23 CANi Acceptance Filter Support Register (CiAFS Register) (i = 0, 1) ........................................... 23.2 CAN Clock and CPU Clock .................................................................................................................. 23.2.1 CAN Clock ....................................................................................................................................... 23.2.2 CPU Clock ........................................................................................................................................ 23.3 Setting and Timing in CAN-Associated Registers ................................................................................ 23.3.1 CAN Module Initialize Timing ........................................................................................................ 23.3.2 CAN Transmit Timing ...................................................................................................................... 23.3.3 CAN Receive Timing ....................................................................................................................... 23.3.4 CAN Bus Error Timing .................................................................................................................... 23.4 CAN Interrupts ...................................................................................................................................... 23.4.1 CAN1 Wake-Up Interrupt ................................................................................................................ 23.4.2 CANij Interrupt ................................................................................................................................. 24. 25.
430 432 438 442 443 447 448 448 448 449 449 450 451 452 453 454 454
Real-Time Port (RTP) ................................................................................................................. 458 Programmable I/O Ports ............................................................................................................. 461 Port Pi Direction Register (PDi Register, i = 0 to 15) ........................................................................... Port Pi Register (Pi Register, i = 0 to 15) .............................................................................................. Function Select Register A (PSj Register, j = 0 to 9) ............................................................................ Function Select Register B (PSLk Register, k = 0 to 3, 5 to 7, 9) ........................................................ Function Select Register C (PSC, PSC2, PSC3, and PSC6 Registers) ................................................. Function Select Register D (PSD1 and PSD2 Registers) ...................................................................... Function Select Register E (PSE1 and PSE2 Registers) ....................................................................... Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers) ................................................................. Port Control Register (PCR Register) ................................................................................................... Input Function Select Register (IPS, IPSA, and IPSB Registers) ......................................................... Analog Input and Other Peripheral Function Input ............................................................................... 461 461 461 461 461 462 462 462 462 462 462
25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.10 25.11 26.
Flash Memory ............................................................................................................................. 493 Memory Map ......................................................................................................................................... Boot Mode ........................................................................................................................................ Functions to Prevent Access to Flash Memory ..................................................................................... ROM Code Protect Function ............................................................................................................ ID Code Check Function .................................................................................................................. CPU Rewrite Mode ............................................................................................................................... Flash Memory Control Register (FMR0 and FMR1 Registers) ....................................................... Software Commands ......................................................................................................................... Data Protect Function ....................................................................................................................... Status Register (SRD Register) ........................................................................................................ Full Status Check .............................................................................................................................. Standard Serial I/O Mode ...................................................................................................................... Pin Handling in Standard Serial I/O Mode ....................................................................................... Parallel I/O Mode .................................................................................................................................. Boot ROM Area ................................................................................................................................ A-6 494 495 495 495 495 497 498 504 509 509 510 512 517 518 518
26.1 26.1.1 26.2 26.2.1 26.2.2 26.3 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.4 26.4.1 26.5 26.5.1
27. 28.
Electrical Characteristics ............................................................................................................. 519 Usage Notes ............................................................................................................................... 556 556 556 557 557 558 558 558 559 560 560 561 561 561 561 561 564 565 565 565 565 567 567 567 568 569 569 569 571 572 573 573 573 573 573 574 576 576 577 578 579 579 579 579 579 579 579 579
28.1 Power Supply ........................................................................................................................................ 28.1.1 Power-on ........................................................................................................................................... 28.1.2 Power Supply Ripple ........................................................................................................................ 28.1.3 Noise ................................................................................................................................................. 28.2 Special Function Registers (SFRs) ........................................................................................................ 28.2.1 100 Pin-Package ............................................................................................................................... 28.2.2 Register Settings ............................................................................................................................... 28.3 Processor Mode ..................................................................................................................................... 28.4 Bus ......................................................................................................................................................... 28.4.1 HOLD Input ...................................................................................................................................... 28.5 Clock Generation Circuits ..................................................................................................................... 28.5.1 Main Clock ....................................................................................................................................... 28.5.2 Sub Clock ......................................................................................................................................... 28.5.3 Clock Dividing Ratio ........................................................................................................................ 28.5.4 Power Consumption Control ............................................................................................................ 28.6 Protection .............................................................................................................................................. 28.7 Interrupts ............................................................................................................................................... 28.7.1 ISP Setting ........................................................................................................................................ 28.7.2 NMI Interrupt ................................................................................................................................... 28.7.3 INT Interrupt ..................................................................................................................................... 28.7.4 Changing Interrupt Control Register ................................................................................................ 28.7.5 Changing IIOiIR Register (i = 0 to 11) ............................................................................................. 28.7.6 Changing RLVL Register ................................................................................................................. 28.8 DMAC ................................................................................................................................................... 28.9 Timers ................................................................................................................................................... 28.9.1 Timer A, Timer B ............................................................................................................................. 28.9.2 Timer A ............................................................................................................................................. 28.9.3 Timer B ............................................................................................................................................. 28.10 Three-Phase Motor Control Timer Function ......................................................................................... 28.11 Serial Interfaces ..................................................................................................................................... 28.11.1 Changing UiBRG Register (i = 0 to 6) ............................................................................................. 28.11.2 Clock Synchronous Mode ................................................................................................................ 28.11.3 UART Mode ..................................................................................................................................... 28.11.4 Special Mode 1 (I2C Mode) .............................................................................................................. 28.12 A/D Converter ....................................................................................................................................... 28.13 Intelligent I/O ........................................................................................................................................ 28.13.1 Register Setting ................................................................................................................................. 28.14 CAN ...................................................................................................................................................... 28.15 Programmable I/O Ports ........................................................................................................................ 28.16 Flash Memory ....................................................................................................................................... 28.16.1 Operating Speed ............................................................................................................................... 28.16.2 Prohibited Instructions ...................................................................................................................... 28.16.3 Interrupts (EW0 Mode) .................................................................................................................... 28.16.4 Interrupts (EW1 Mode) .................................................................................................................... 28.16.5 How to Access .................................................................................................................................. 28.16.6 Rewriting User ROM Area (EW0 Mode) ......................................................................................... 28.16.7 Rewriting User ROM Area (EW1 Mode) ......................................................................................... A-7
28.16.8 Boot Mode ........................................................................................................................................ 28.16.9 Writing Command and Data ............................................................................................................. 28.16.10 Block Erase ...................................................................................................................................... 28.16.11 Wait Mode ....................................................................................................................................... 28.16.12 Stop Mode ........................................................................................................................................ 28.16.13 Low-Power Consumption Mode and On-Chip Oscillator Low-Power Consumption Mode ........... 28.17 Difference Between Flash Memory Version and Mask ROM Version ................................................
580 580 580 580 580 580 581
Appendix 1. Package Dimensions ........................................................................................................ 582 Index ......................................................................................................................................... 584
A-8
Special Function Register (SFR) Page Reference
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh Register Symbol Page Address 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h PLL Control Register 0 PLL Control Register 1 Address Match Interrupt Register 4 PLC0 PLC1 RMAD4 86 86 127 0072h 0073h 0074h 0075h Address Match Interrupt Register 5 Vdet4 Detection Interrupt Register RAMD5 D4INT 127 53 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h Address Match Interrupt Register 6 RMAD6 127 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3 EWCR0 EWCR1 EWCR2 EWCR3 69 69 69 69 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h Register Symbol Page
Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 Processor Mode Register 2 Address Match Interrupt Register 1 Voltage Detection Register 2 Address Match Interrupt Register 2 Voltage Detection Register 1 Address Match Interrupt Register 3
PM0 PM1 CM0 CM1 AIER PRCR DS MCD CM2 WDTS WDC RMAD0 PM2 RMAD1 VCR2 RMAD2 VCR1 RMAD3
60 61 82, 136 83 127 105 63 84 85 137 54, 137 127 87 127 52 127 52 127
Flash Memory Control Register 1 Flash Memory Control Register 0
FMR1 FMR0
500 498
DMA0 Control Register Timer B5 Interrupt Control Register DMA2 Control Register UART2 Receive/ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive/ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive/ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detection Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register II/O Interrupt Control Register 0/ CAN1 Interrupt Control Register 0 Timer B1 Interrupt Control Register II/O Interrupt Control Register 2 Timer B3 Interrupt Control Register II/O Interrupt Control Register 4 INT5 Interrupt Control Register II/O Interrupt Control Register 6 INT3 Interrupt Control Register II/O Interrupt Control Register 8 INT1 Interrupt Control Register II/O Interrupt Control Register 10/ CAN0 Interrupt Control Register 1 II/O Interrupt Control Register 11/ CAN0 interrupt control register 2
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/ BCN3IC S0RIC AD0IC S1RIC IIO0IC/ CAN3IC TB1IC IIO2IC TB3IC IIO4IC INT5IC IIO6IC INT3IC IIO8IC INT1IC IIO10IC/ CAN1IC IIO11IC/ CAN2IC 114
115 114 115 114 115 114 114
Address Match Interrupt Register 7
RMAD7
127
Blank spaces are reserved. No access is allowed.
DMA1 Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detection Interrupt Control Register UART0 Transmit/NACK Interrupt Control Register UART1/UART4 Bus Conflict Detection Interrupt Control Register UART1 Transmit /NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC S0TIC BCN1IC/ BCN4IC S1TIC KUPIC TB0IC 114
Blank spaces are reserved. No access is allowed.
B-1
Special Function Register (SFR) Page Reference
Address 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh to 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh Register II/O Interrupt Control Register 1/ CAN1 Interrupt Control Register 1 Timer B2 Interrupt Control Register II/O Interrupt Control Register 3 Timer B4 Interrupt Control Register II/O Interrupt Control Register 5/ CAN1 Interrupt Control Register 2 INT4 Interrupt Control Register II/O Interrupt Control Register 7 INT2 Interrupt Control Register II/O Interrupt Control Register 9/ CAN0 Interrupt Control register 0 INT0 Interrupt Control Register Exit Priority Register Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Request Register 2 Interrupt Request Register 3 Interrupt Request Register 4 Interrupt Request Register 5 Interrupt Request Register 6 Interrupt Request Register 7 Interrupt Request Register 8 Interrupt Request Register 9 Interrupt Request Register 10 Interrupt Request Register 11 Symbol IIO1IC/ CAN4IC TB2IC IIO3IC TB4IC IIO5IC/ CAN5IC INT4IC IIO7IC INT2IC IIO9IC/ CAN0IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Page Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 129 0112h 0113h 0114h 0115h 0116h Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Enable Register 4 Interrupt Enable Register 5 Interrupt Enable Register 6 Interrupt Enable Register 7 Interrupt Enable Register 8 Interrupt Enable Register 9 Interrupt Enable Register 10 Interrupt Enable Register 11 IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah Group 0 SI/O Receive Buffer Register Group 0 Transmit Buffer/Receive Data Register Group 0 Receive Input Register Group 0 SI/O Communication Mode Register Group 0 Transmit Output Register Group 0 SI/O Communication Control Register Group 0 Data Compare Register 0 Group 0 Data Compare Register 1 Group 0 Data Compare Register 2 Group 0 Data Compare Register 3 Group 0 Data Mask Register 0 Group 0 Data Mask Register 1 Communication Clock Select Register Group 0 Receive CRC Code Register Group 0 Transmit CRC Code Register Group 0 SI/O Expansion Mode Register Group 0 SI/O Extended Receive Control Register Group 0 SI/O Special Communication Interrupt Detection Register Group 0 SI/O Extended Transmit Control Register G0RB G0TB/ G0DR G0RI G0MR G0TO G0CR G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1 CCS G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC 376 373 374 375 373 378 377 378 371 378 372 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Register Group 1 Time Measurement/Waveform Generation Register 0 Group 1 Time Measurement/Waveform Generation Register 1 Group 1 Time Measurement/Waveform Generation Register 2 Group 1 Time Measurement/Waveform Generation Register 3 Group 1 Time Measurement/Waveform Generation Register 4 Group 1 Time Measurement/Waveform Generation Register 5 Group 1 Time Measurement/Waveform Generation Register 6 Group 1 Time Measurement/Waveform Generation Register 7 Group 1 Waveform Generation Control Register 0 Group 1 Waveform Generation Control Register 1 Group 1 Waveform Generation Control Register 2 Group 1 Waveform Generation Control Register 3 Group 1 Waveform Generation Control Register 4 Group 1 Waveform Generation Control Register 5 Group 1 Waveform Generation Control Register 6 Group 1 Waveform Generation Control Register 7 Group 1 Time Measurement Control Register 0 Group 1 Time Measurement Control Register 1 Group 1 Time Measurement Control Register 2 Group 1 Time Measurement Control Register 3 Group 1 Time Measurement Control Register 4 Group 1 Time Measurement Control Register 5 Group 1 Time Measurement Control Register 6 Group 1 Time Measurement Control Register 7 Group 1 Base Timer Register Group 1 Base Timer Control Register 0 Group 1 Base Timer Control Register 1 Group 1 Time Measurement Prescaler Register 6 Group 1 Time Measurement Prescaler Register 7 Group 1 Function Enable Register Group 1 Function Select Register Group 1 SI/O Receive Buffer Register Group 1 Transmit Buffer/Receive Data Register Group 1 Receive Input Register Group 1 SI/O Communication Mode Register Group 1 Transmit Output Register Group 1 SI/O Communication Control Register Group 1 Data Compare Register 0 Group 1 Data Compare Register 1 Group 1 Data Compare Register 2 Group 1 Data Compare Register 3 Group 1 Data Mask Register 0 Group 1 Data Mask Register 1 Symbol G1TM0/ G1PO0 G1TM1/ G1PO1 G1TM2/ G1PO2 G1TM3/ G1PO3 G1TM4/ G1PO4 G1TM5/ G1PO5 G1TM6/ G1PO6 G1TM7/ G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1 G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1RB G1TB/ G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1 327 Page
114
115 114 115 114 115 116, 152
327/328
326
130
324 324 325 326 329 378 377 378 371 378 372
376
376
Group 1 Receive CRC Code Register Group 1 Transmit CRC Code Register Group 1 SI/O Expansion Mode Register Group 1 SI/O Extended Receive Control Register Group 1 SI/O Special Communication Interrupt Detection Register Group 1 SI/O Extended Transmit Control Register
G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC
376 373 374 375 373
370
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed.
B-2
Special Function Register (SFR) Page Reference
Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh to 01BFh Register Group 2 Waveform Generation Control Register 0 Group 2 Waveform Generation Control Register 1 Group 2 Waveform Generation Control Register 2 Group 2 Waveform Generation Control Register 3 Group 2 Waveform Generation Control Register 4 Group 2 Waveform Generation Control Register 5 Group 2 Waveform Generation Control Register 6 Group 2 Waveform Generation Control Register 7 Group 2 Waveform Generation Control Register 0 Group 2 Waveform Generation Control Register 1 Group 2 Waveform Generation Control Register 2 Group 2 Waveform Generation Control Register 3 Group 2 Waveform Generation Control Register 4 Group 2 Waveform Generation Control Register 5 Group 2 Waveform Generation Control Register 6 Group 2 Waveform Generation Control Register 7 Symbol G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7 G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7 332 Page Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh Register UART5 Transmit/Receive Mode Register UART5 Baud Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register UART6 Transmit/Receive Mode Register UART6 Baud Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART5 Receive Buffer Register UART5, UART6 Transmit/Receive Control Register UART5, UART6 Input Pin Function Select Register Symbol U5MR U5BRG U5TB U5C0 U5C1 U5RB U6MR U6BRG U6TB U6C0 U6C1 U6RB U56CON U56IS Page 274 275 277 275 276 277 274 275 277 275 276 277 276 273
333
RTP Output Buffer Register 0 RTP Output Buffer Register 1 RTP Output Buffer Register 2 RTP Output Buffer Register 3
RTP0R RTP1R RTP2R RTP3R
459
Group 2 Base Timer Register Group 2 Base Timer Control Register 0 Group 2 Base Timer Control Register 1 Base Timer Start Register Group 2 Function Enable Register Group 2 RTP Output Buffer Register
G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP
330 330 331 335 334
Group 2 SI/O Communication Mode Register Group 2 SI/O Communication Control Register Group 2 SI/O Transmit Buffer Data Register Group 2 SI/O Receive Buffer Register Group 2 IEBus Address Register Group 2 IEBus Control Register Group 2 IEBus Transmit Interrupt Source Detection Register Group 2 IEBus Receive Interrupt Source Detection Register
G2MR G2CR G2TB G2RB IEAR IECR IETIF IERIF
394 395
393
396
397
Input Function Select Register B Input Function Select Register Input Function Select Register A
IPSB IPS IPSA
486 485 486
CAN0 Message Slot Buffer 0 Standard ID0 CAN0 Message Slot Buffer 0 Standard ID1 CAN0 Message Slot Buffer 0 Extended ID0 CAN0 Message Slot Buffer 0 Extended ID1 CAN0 Message Slot Buffer 0 Extended ID2 CAN0 Message Slot Buffer 0 Data Length Code CAN0 Message Slot Buffer 0 Data 0 CAN0 Message Slot Buffer 0 Data 1 CAN0 Message Slot Buffer 0 Data 2 CAN0 Message Slot Buffer 0 Data 3 CAN0 Message Slot Buffer 0 Data 4 CAN0 Message Slot Buffer 0 Data 5 CAN0 Message Slot Buffer 0 Data 6 CAN0 Message Slot Buffer 0 Data 7 CAN0 Message Slot Buffer 0 Time Stamp High-Order CAN0 Message Slot Buffer 0 Time Stamp Low-Order CAN0 Message Slot Buffer 1 Standard ID0 CAN0 Message Slot Buffer 1 Standard ID1 CAN0 Message Slot Buffer 1 Extended ID0 CAN0 Message Slot Buffer 1 Extended ID1 CAN0 Message Slot Buffer 1 Extended ID2 CAN0 Message Slot Buffer 1 Data Length Code CAN0 Message Slot Buffer 1 Data 0 CAN0 Message Slot Buffer 1 Data 1 CAN0 Message Slot Buffer 1 Data 2 CAN0 Message Slot Buffer 1 Data 3 CAN0 Message Slot Buffer 1 Data 4 CAN0 Message Slot Buffer 1 Data 5 CAN0 Message Slot Buffer 1 Data 6 CAN0 Message Slot Buffer 1 Data 7 CAN0 Message Slot Buffer 1 Time Stamp High-Order CAN0 Message Slot Buffer 1 Time Stamp Low-Order
C0SLOT0_0 C0SLOT0_1 C0SLOT0_2 C0SLOT0_3 C0SLOT0_4 C0SLOT0_5 C0SLOT0_6 C0SLOT0_7 C0SLOT0_8 C0SLOT0_9 C0SLOT0_10 C0SLOT0_11 C0SLOT0_12 C0SLOT0_13 C0SLOT0_14 C0SLOT0_15 C0SLOT1_0 C0SLOT1_1 C0SLOT1_2 C0SLOT1_3 C0SLOT1_4 C0SLOT1_5 C0SLOT1_6 C0SLOT1_7 C0SLOT1_8 C0SLOT1_9 C0SLOT1_10 C0SLOT1_11 C0SLOT1_12 C0SLOT1_13 C0SLOT1_14 C0SLOT1_15
443 444 445
446
443 444 445
446
Blank spaces are reserved. No access is allowed
Blank spaces are reserved. No access is allowed.
B-3
Special Function Register (SFR) Page Reference
.
Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h Register CAN0 Control Register 0 CAN0 Status Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Time Stamp Register CAN0 Transmit Error Count Register CAN0 Receive Error Count Register CAN0 Slot Interrupt Status Register Symbol C0CTLR0 C0STR C0IDR C0CONR C0TSR C0TEC C0REC C0SISTR Page 405 410 413 414 417 418 419 Address 0246h 0247h 0248h 0249h 024Ah 024Bh 024Ch 024Dh 024Eh 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh Register Symbol Page
CAN1 Slot Buffer Select Register CAN1 Control Register 1 CAN1 Sleep Control Register CAN1 Acceptance Filter Support Register
C1SBS C1CTLR1 C1SLPR C1AFS
442 408 409 447
CAN0 Slot Interrupt Mask Register
C0SIMKR
421
CAN0 Error Interrupt Mask Register CAN0 Error Interrupt Status Register CAN0 Error Source Register CAN0 Baud Rate Prescaler CAN0 Mode Register
C0EIMKR C0EISTR C0EFR C0BRP C0MDR
422 423 424 416 426
CAN0 Single Shot Control Register
C0SSCTLR
428
CAN0 Single Shot Status Register
C0SSSTR
430
CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 CAN0 Global Mask Register Extended ID2
C0GMR0 C0GMR1 C0GMR2 C0GMR3 C0GMR4
432 433 434 435 436
CAN0 Message Slot 0 Control Register/ CAN0 Local Mask Register A Standard ID0 CAN0 Message Slot 1 Control Register/ CAN0 Local Mask Register A Standard ID1 CAN0 Message Slot 2 Control Register/ CAN0 Local Mask Register A Extended ID0 CAN0 Message Slot 3 Control Register/ CAN0 Local Mask Register A Extended ID1 CAN0 Message Slot 4 Control Register/ CAN0 Local Mask Register A Extended ID2 CAN0 Message Slot 5 Control Register CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register CAN0 Message Slot 8 Control Register/ CAN0 Local Mask Register B Standard ID0 CAN0 Message Slot 9 Control Register/ CAN0 Local Mask Register B Standard ID1 CAN0 Message Slot 10 Control Register/ CAN0 Local Mask Register B Extended ID0 CAN0 Message Slot 11 Control Register/ CAN0 Local Mask Register B Extended ID1 CAN0 Message Slot 12 Control Register/ CAN0 Local Mask Register B Extended ID2 CAN0 Message Slot 13 Control Register CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register CAN0 Slot Buffer Select Register CAN0 Control Register 1 CAN0 Sleep Control Register CAN0 Acceptance Filter Support Register
C0MCTL0/ C0LMAR0 C0MCTL1/ C0LMAR1 C0MCTL2/ C0LMAR2 C0MCTL3/ C0LMAR3 C0MCTL4/ C0LMAR4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8/ C0LMBR0 C0MCTL9/ C0LMBR1 C0MCTL10/ C0LMBR2 C0MCTL11/ C0LMBR3 C0MCTL12/ C0LMBR4 C0MCTL13 C0MCTL14 C0MCTL15 C0SBS C0CTLR1 C0SLPR C0AFS
438/432 438/433 438/434 438/435 438/436 438 438/432 438/433 438/434 438/435 438/436 438 442 408 409 447
CAN1 Message Slot Buffer 0 Standard ID0 CAN1 Message Slot Buffer 0 Standard ID1 CAN1 Message Slot Buffer 0 Extended ID0 CAN1 Message Slot Buffer 0 Extended ID1 CAN1 Message Slot Buffer 0 Extended ID2 CAN1 Message Slot Buffer 0 Data Length Code CAN1 Message Slot Buffer 0 Data 0 CAN1 Message Slot Buffer 0 Data 1 CAN1 Message Slot Buffer 0 Data 2 CAN1 Message Slot Buffer 0 Data 3 CAN1 Message Slot Buffer 0 Data 4 CAN1 Message Slot Buffer 0 Data 5 CAN1 Message Slot Buffer 0 Data 6 CAN1 Message Slot Buffer 0 Data 7 CAN1 Message Slot Buffer 0 Time Stamp High-Order CAN1 Message Slot Buffer 0 Time Stamp Low-Order CAN1 Message Slot Buffer 1 Standard ID0 CAN1 Message Slot Buffer 1 Standard ID1 CAN1 Message Slot Buffer 1 Extended ID0 CAN1 Message Slot Buffer 1 Extended ID1 CAN1 Message Slot Buffer 1 Extended ID2 CAN1 Message Slot Buffer 1 Data Length Code CAN1 Message Slot Buffer 1 Data 0 CAN1 Message Slot Buffer 1 Data 1 CAN1 Message Slot Buffer 1 Data 2 CAN1 Message Slot Buffer 1 Data 3 CAN1 Message Slot Buffer 1 Data 4 CAN1 Message Slot Buffer 1 Data 5 CAN1 Message Slot Buffer 1 Data 6 CAN1 Message Slot Buffer 1 Data 7 CAN1 Message Slot Buffer 1 Time Stamp High-Order CAN1 Message Slot Buffer 1 Time Stamp Low-Order CAN1 Control Register 0 CAN1 Status Register CAN1 Extended ID Register CAN1 Configuration Register CAN1 Time Stamp Register CAN1 Transmit Error Count Register CAN1 Receive Error Count Register CAN1 Slot Interrupt Status Register
C1SLOT0_0 C1SLOT0_1 C1SLOT0_2 C1SLOT0_3 C1SLOT0_4 C1SLOT0_5 C1SLOT0_6 C1SLOT0_7 C1SLOT0_8 C1SLOT0_9 C1SLOT0_10 C1SLOT0_11 C1SLOT0_12 C1SLOT0_13 C1SLOT0_14 C1SLOT0_15 C1SLOT1_0 C1SLOT1_1 C1SLOT1_2 C1SLOT1_3 C1SLOT1_4 C1SLOT1_5 C1SLOT1_6 C1SLOT1_7 C1SLOT1_8 C1SLOT1_9 C1SLOT1_10 C1SLOT1_11 C1SLOT1_12 C1SLOT1_13 C1SLOT1_14 C1SLOT1_15 C1CTLR0 C1STR C1IDR C1CONR C1TSR C1TEC C1REC C1SISTR
443 444 445
446
443 444 445
446
405 410 413 414 417 418 419
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed.
B-4
Special Function Register (SFR) Page Reference
Address 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h Register CAN1 Slot Interrupt Mask Register Symbol C1SIMKR Page 421 Address 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh Register X10 Register, Y10 Register X11 Register, Y11 Register X12 Register, Y12 Register X13 Register, Y13 Register X14 Register, Y14 Register X15 Register, Y15 Register X/Y Control Register Symbol X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC Page
CAN1 Error Interrupt Mask Register CAN1 Error Interrupt Status Register CAN1 Error Source Register CAN1 Baud Rate Prescaler CAN1 Mode Register
C1EIMKR C1EISTR C1EFR C1BRP C1MDR
422 423 424 416 426
318
318
CAN1 Single Shot Control Register
C1SSCTLR
428
CAN1 Single Shot Status Register
C1SSSTR
430
UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
220 219 218 217 216 222 224 221 222 224
CAN1 Global Mask Register Standard ID0 CAN1 Global Mask Register Standard ID1 CAN1 Global Mask Register Extended ID0 CAN1 Global Mask Register Extended ID1 CAN1 Global Mask Register Extended ID2
C1GMR0 C1GMR1 C1GMR2 C1GMR3 C1GMR4
432 433 434 435 436
CAN1 Message Slot 0 Control Register/ CAN1 Local Mask Register A Standard ID0 CAN1 Message Slot 1 Control Register/ CAN1 Local Mask Register A Standard ID1 CAN1 Message Slot 2 Control Register/ CAN1 Local Mask Register A Extended ID0 CAN1 Message Slot 3 Control Register/ CAN1 Local Mask Register A Extended ID1 CAN1 Message Slot 4 Control Register/ CAN1 Local Mask Register A Extended ID2 CAN1 Message Slot 5 Control Register CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register CAN1 Message Slot 8 Control Register/ CAN1 Local Mask Register B Standard ID0 CAN1 Message Slot 9 Control Register/ CAN1 Local Mask Register B Standard ID1 CAN1 Message Slot 10 Control Register/ CAN1 Local Mask Register B Extended ID0 CAN1 Message Slot 11 Control Register/ CAN1 Local Mask Register B Extended ID1 CAN1 Message Slot 11 Control Register/ CAN1 Local Mask Register B Extended ID1 CAN1 Message Slot 13 Control Register CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register X0 Register, Y0 Register X1 Register, Y1 Register X2 Register, Y2 Register X3 Register, Y3 Register X4 Register, Y4 Register X5 Register, Y5 Register X6 Register, Y6 Register X7 Register, Y7 Register X8 Register, Y8 Register X9 Register, Y9 Register
C1MCTL0/ C1LMAR0 C1MCTL1/ C1LMAR1 C1MCTL2/ C1LMAR2 C1MCTL3/ C1LMAR3 C1MCTL4/ C1LMAR4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8/ C1LMBR0 C1MCTL9/ C1LMBR1 C1MCTL10/ C1LMBR2 C1MCTL11/ C1LMBR3 C1MCTL12/ C1LMBR4 C1MCTL13 C1MCTL14 C1MCTL15 X0R, Y0R X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R
438/432 438/433 438/434 438/435 438/436 438 438/432 438/433 438/434 438/435 438/436 438
UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Flag Timer A11 Register Timer A21 Register Timer A41 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
220 219 218 217 216 222 224 221 222 224 189
205
198 199 205 205 204 203
Timer B3 Register Timer B4 Register Timer B5 Register
TB3 TB4 TB5 188
318
Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Source Select Register 1 External Interrupt Source Select Register
TB3MR TB4MR TB5MR IFSRA IFSR
185, 186, 187 125 124, 223
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed.
B-5
Special Function Register (SFR) Page Reference
Address 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 044Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh Register Symbol Page Address 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh Register Symbol Page
IrDA Control Register
IRCON
270
UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
220 219 218 217 216 222 224 221 222 224
DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
DM0SL DM1SL DM2SL DM3SL CRCD CRCIN AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07
140
316 316
UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Register Clock Prescaler Reset Register One-Shot Start Register Trigger Select Register Up/Down Select Register Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF TA0 TA1 TA2 TA3 TA4 TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR
220 219 218 217 216 222 224 221 222 224 170, 189, 206 88 171 169, 202 168 167 167, 205 167, 205 167 167, 205 188 188 188, 204
299
A/D0 Control Register 4 A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 D/A Register 1 D/A Control Register D/A Control Register 1
AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON DACON1
299 297 298 295 296 314 314 314 314
Function Select Register A8 Function Select Register A9 Function Select Register B9 Function Select Register E2
PS8 PS9 PSL9 PSE2
472 476 480
163, 164, 165, 166
Function Select Register D1 Function Select Register D2 Function Select Register C6 Function Select Register E1 Function Select Register C2 Function Select Register C3 Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 Function Select Register A4 Function Select Register A5 Function Select Register B5 Function Select Register A6 Function Select Register A7 Function Select Register B6 Function Select Register B7
PSD1 PSD2 PSC6 PSE1 PSC2 PSC3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 PS4 PS5 PSL5 PS6 PS7 PSL6 PSL7
479 478 480 477 478 477 468 473 469 474 470 475 471 471 475 476
185, 186, 187 203 88, 162
UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Baud Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
220 219 218 217 216 222 224 221 222 224
Blank spaces are reserved. No access is allowed.
Blank spaces are reserved. No access is allowed
B-6
Special Function Register (SFR) Page Reference
..
Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Register Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register Port P10 Direction Register Port P11 Direction Register Port P12 Register Port P13 Register Port P12 Direction Register Port P13 Direction Register Port P14 Register Port P15 Register Port P14 Direction Register Port P15 Direction Register Symbol P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13 P14 P15 PD14 PD15 Page 467 466 467 466 467 466 467 466 467 466
Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4
PUR2 PUR3 PUR4
482 483 484
Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
467 466 467 466 467 466
Pull-Up Control Register 0 Pull-Up Control Register 1
PUR0 PUR1
481
Port Control Register
PCR
485
Blank spaces are reserved. No access is allowed.
B-7
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
RENESAS MCU
1.
1.1
Overview
Features
The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) is a single-chip control MCU, fabricated using highperformance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/87 Group (M32C/ 87, M32C/87A, M32C/87B) is housed in 144-pin and 100-pin plastic molded LQFP/QFP packages. With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process complex instructions by less bytes and execute instructions at higher speed. The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has a multiplier and DMAC adequate for office automation, communication devices and industrial equipment, and other high-speed processing applications.
1.1.1
Applications
Audio components, cameras, office equipment, communication devices, mobile devices, etc.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 1 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.1.2
Specifications
Tables 1.1 to 1.4 list the specifications of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). Table 1.1 Item CPU Specifications (144-Pin Package) (1/2) Function Central processing unit Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V) 41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V) * Operating modes: Single-chip mode, memory expansion mode, and microprocessor mode See Tables 1.5 to 1.7 Product List. Vdet3 detection function, Vdet4 detection function, cold start/warm start determination function * Address space: 16 Mbytes * External bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detection function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode * Interrupt vectors: 70 * External interrupt inputs: 14 (NMI, INT x 9, key input x 4) * Interrupt priority levels: 7 15-bit x 1 channel (with prescaler) * 4 channels, cycle steal method * Trigger sources: 43 * Transfer modes: 2 (single transfer and repeat transfer) * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode, Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, and timer B2) On-chip dead time timer
ROM, RAM, data flash Power Supply Voltage Detection External Bus Expansion Bus/memory expansion function
Memory
Clock
Clock generation circuits
Interrupts Watchdog Timer DMA DMAC DMACII
Timer
Timer A
Timer B Timer function for 3-phase motor control
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 2 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.2 Specifications (144-Pin Package) (2/2)
1. Overview
Item Function Serial Interface UART0 to UART4
UART5, UART6 A/D Converter
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits Intelligent I/O 16-bit timer x 2 * Time measurement function (input capture): 8 channels * Waveform generation function (output compare): 16 channels * Communication function: Clock synchronous mode, clock asynchronous mode, HDLC data processing mode, IEBus (optional)(1)(3) * 2-phase pulse signal processing (2-phase encoder input) x 1 ROM Correction Function Address match interrupt x 8 CAN modules Supporting CAN 2.0B specification M32C/87: 16 slots x 2 channels, M32C/87A: 16 slots x 1 channel M32C/87B: none I/O Ports Programmable I/O * Input only: 1 ports * CMOS I/O: 121 with selectable pull-up resistor * N channel open drain ports: 2 Flash Memory * Erase and program voltage: 3.3 V 0.3 V or 5.0 V 0.5 V * Erase and program endurance: 100 times (all areas) * Program security: ROM code protect and ID code check * Debug functions: On-chip debug and on-board flash reprogram Operating Frequency/Supply Voltage 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 V to VCC1 24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1 Current Consumption 32 mA (32 MHz, VCC1 = VCC2 = 5 V) 23 mA (24 MHz, VCC1 = VCC2 = 3.3 V) 45 A (approx. 1 MHz, VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 0.8 A (VCC1 = VCC2 = 3.3 V, stop mode) Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(3) Package 144-pin LQFP (PLQP0144KA-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Available in UART0. 3. Please contact a Renesas sales office for optional features.
D/A Converter CRC Calculation Circuit
Specification Clock synchronous/asynchronous x 5 I2C bus, special mode 2, GCI mode, SIM mode, IrDA mode(2), IEBus (optional)(1)(3) Clock synchronous/asynchronous x 2 10-bit resolution x 34 channels (in single-chip mode) 10-bit resolution x 18 channels (in memory expansion mode and microprocessor mode) Including sample and hold function 8-bit resolution x 2 channels
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 3 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.3 Item CPU Specifications (100-Pin Package) (1/2) Function Central processing unit
1. Overview
ROM, RAM, data flash Power Supply Voltage Detection External Bus Expansion Bus/memory expansion function
Memory
Specification M32C/80 core (multiplier: 16 bits x 16 bits 32 bits multiply-addition operation instructions: 16 x 16 + 48 48 bits) * Basic instructions: 108 * Minimum instruction execution time: 31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V) 41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V) * Operating mode: Single-chip mode, memory expansion mode, and microprocessor mode See Tables 1.5 to 1.7 Product List. Vdet3 detection function, Vdet4 detection function, cold start/warm start determination function * Address space: 16 Mbytes * External bus interface: 1 to 7 wait states can be inserted, 4 chip select outputs, 3 V and 5 V interfaces * Bus format: Switchable between separate bus and multiplexed bus formats, switchable data bus width (8-bit or 16-bit) * 4 circuits: Main clock, sub clock, on-chip oscillator, PLL frequency synthesizer * Oscillation stop detection: Main clock oscillation stop detection function * Frequency divider circuit: Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16 * Low power consumption features: Wait mode, stop mode * Interrupt vectors: 70 * External interrupt inputs: 11 (NMI, INT x 6, key input x 4) * Interrupt priority levels: 7 15-bit x 1 channel (with prescaler) * 4 channels, cycle steal method * Trigger sources: 43 * Transfer modes: 2 (single transfer and repeat transfer) * Can be activated by all peripheral function interrupt sources * Transfer modes: 2 (single transfer and burst transfer) * Immediate transfer, calculation transfer, and chain transfer functions 16-bit timer x 5 Timer mode, event counter mode, one-shot timer mode, pulse width modulation (PWM) mode, Event counter 2-phase pulse signal processing (2-phase encoder input) x 3 16-bit timer x 6 Timer mode, event counter mode, pulse period measurement mode, pulse width measurement mode 3-phase inverter control x 1 (using timer A1, timer A2, timer A4, and timer B2) On-chip dead time timer
Clock
Clock generation circuits
Interrupts Watchdog Timer DMA DMAC DMACII
Timer
Timer A
Timer B Timer function for 3-phase motor control
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 4 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.4 Specifications (100-Pin Package) (2/2)
1. Overview
Item Function Serial Interface UART0 to UART4
UART5 A/D Converter
CRC-CCITT (X16 + X12 + X5 + 1) compliant X/Y Converter 16 bits x 16 bits Intelligent I/O 16-bit timer x 2 * Time measurement function (input capture): 8 channels * Waveform generation function (output compare): 10 channels * Communication function: Clock synchronous mode, clock asynchronous mode, HDLC data processing mode, IEBus (optional)(1)(3) * 2-phase pulse signal processing (2-phase encoder input) x 1 ROM Correction Function Address match interrupt x 8 CAN modules Supporting CAN 2.0B specification M32C/87: 16 slots x 2 channels, M32C/87A: 16 slots x 1 channel M32C/87B: none I/O Ports Programmable I/O * Input only: 1 ports * CMOS I/O: 85, selectable pull-up resistor * N channel open drain ports: 2 Flash Memory * Erase and program voltage: 3.3 V 0.3 V or 5.0 V 0.5 V * Erase and program endurance: 100 times (all areas) * Program security: ROM code protect and ID code check * Debug functions: On-chip debug and on-board flash reprogram Operating Frequency/Supply Voltage 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 V to VCC1 24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1 Current Consumption 32 mA (32 MHz, VCC1 = VCC2 = 5 V) 23 mA (24 MHz, VCC1 = VCC2 = 3.3 V) 45 A (approx. 1 MHz, VCC1 = VCC2 = 3.3 V, on-chip oscillator low-power consumption mode wait mode) 0.8 A (VCC1 = VCC2 = 3.3 V, stop mode) Operating Ambient Temperature (C) -20 to 85C, -40 to 85C (optional)(3) Package 100-pin LQFP (PLQP0100KB-A) 100-pin QFP (PRQP0100JB-A) NOTES: 1. IEBus is a registered trademark of NEC Electronics Corporation. 2. Available in UART0. 3. Please contact a Renesas sales office for optional features.
D/A Converter CRC Calculation Circuit
Specification Clock synchronous/asynchronous x 5 I2C bus, special mode 2, GCI mode, SIM mode, IrDA mode(2), IEBus (optional)(1)(3) Clock synchronous/asynchronous x 1 10-bit resolution x 26 channels (in single-chip mode) 10-bit resolution x 10 channels (in memory expansion mode and microprocessor mode) Including sample and hold function 8-bit resolution x 2 channels
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 5 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.2
Product List
Tables 1.5 to 1.7 list product information. Figure 1.1 shows product numbering system. Table 1.5 M32C/87 Group (1) (M32C/87: 2-channel CAN module)
Package Code PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) 384 KB 24 KB 512 KB 31 KB Mask ROM ROM Capacity 1 MB + 4 KB(1) 768 KB + 4 KB(1) 512 KB + 4 KB(1) 384 KB + 4 KB(1) 31 KB 24 KB RAM Capacity
Current as of Jul. 2008
Remarks
Part Number M3087BFLGP M30879FLFP M30879FLGP M3087BFKGP M30879FKGP M30878FJGP M30876FJGP M30875FHGP M30873FHGP M30878MJ-XXXGP M30876MJ-XXXFP M30876MJ-XXXGP M30875MH-XXXGP M30873MH-XXXGP
48 KB Flash memory
NOTE: 1. Additional 4-Kbyte space is available for data flash memory.
Table 1.6
M32C/87 Group (2) (M32C/87A: 1-channel CAN module)
Package Code PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) 384 KB 24 KB 512 KB 31 KB ROM Capacity 1 MB + 4 KB(1) 768 KB + 4 KB(1) 512 KB + 4 KB(1) 384 KB + 4 KB(1) 31 KB 24 KB RAM Capacity
Current as of Jul. 2008
Remarks
Part Number M3087BFLAGP M30879FLAFP M30879FLAGP M3087BFKAGP M30879FKAGP M30878FJAGP M30876FJAGP M30875FHAGP M30873FHAGP M30878MJA-XXXGP M30876MJA-XXXFP M30876MJA-XXXGP M30875MHA-XXXGP M30873MHA-XXXGP
48 KB Flash memory
Mask ROM
NOTE: 1. Additional 4-Kbyte space is available for data flash memory.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 6 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.7 M32C/87 Group (3) (M32C/87B: no CAN module)
Package Code PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PRQP0100JB-A (100P6S-A) PLQP0100KB-A (100P6Q-A) PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) 384 KB 24 KB 512 KB 31 KB ROM Capacity 1 MB + 4 KB(1) 768 KB + 4 KB(1) 512 KB + 4 KB(1) 384 KB + 4 KB(1) 31 KB 24 KB
1. Overview Current as of Jul. 2008
RAM Capacity Remarks
Part Number M3087BFLBGP M30879FLBFP M30879FLBGP M3087BFKBGP M30879FKBGP M30878FJBGP M30876FJBGP M30875FHBGP M30873FHBGP M30878MJB-XXXGP M30876MJB-XXXFP M30876MJB-XXXGP M30875MHB-XXXGP M30873MHB-XXXGP
48 KB Flash memory
Mask ROM
NOTE: 1. Additional 4-Kbyte space is available for data flash memory.
Part No.
M30 87 6 M J
-XXX GP
Package type option FP: PRQP0100JB-A (100P6S-A) GP: PLQP0144KA-A (144P6Q-A) PLQP0100KB-A (100P6Q-A) ROM Number: Omitted for the Flash Memory Version Classification Blank: M32C/87 A: M32C/87A B: M32C/87B ROM capacity H: 384 Kbytes J: 512 Kbytes K: 768 Kbytes L: 1024 Kbytes Memory type M: Mask ROM version F: Flash memory version RAM capacity, pin count, etc (The value itself has no specific meaning.) M32C/87 Group M16C Family
Figure 1.1
Product Numbering System
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 7 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.3
Block Diagram
Figure 1.2 shows a block diagram of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B).
8
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7

Internal peripheral functions
Timers (16 bits) Output (timer A): 5 Input (timer B): 6 Three-phase motor control circuit Watchdog timer (15 bits) Serial interface: 7 channels(3) 10-bit A/D converter: 1 circuit 34 channels for input(2) 8-bit D/A converters: 2 circuits X/Y converter: 16 bits X 16 bits DMAC: 4 channels Clock generation circuits: XIN-XOUT XCIN-XCOUT On-chip oscillator PLL frequency synthesizer CRC calculation circuit (CCITT): X16 + X12 + X5 + 1 DMACII
Intelligent I/O Time measurement function: 8 channels Waveform generation function: 16 channels(4) Communication function: clock synchronous serial interface, UART, HDLC data processing, IEBus CAN modules:2 channels(5)
Port P13(1) Port P12(1) Port P11(1)
M32C/80 Series CPU core
R1H R1L R0H R0L R1H R1L R1H R1L R2 R3 A0 A1 FB SB FLG INTB ISP USP PC SVF SVP VCT
Memory
ROM
RAM
Multiplier

Port P15(1) Port P14(1) Port P10 Port P9 P8_5 Port P8
8
8
5
8
7
8
8
7
NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. 34 channels are available in the 144-pin package. 26 channels are available in the 100-pin package. 3. 6 channels are available in the 100-pin package. 4. 10 channels are available in the 100-pin package. 5. M32C/87A has 1 channel. M32C/87B has no CAN module.
Figure 1.2
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Block Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 8 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.4
Pin Assignments
Figures 1.3 to 1.5 show pin assignments (top view).
( note 7) ( note 7)
P1_1 / D9 P1_2 / D10 P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0, [A0/D0] P2_1 / AN2_1 / A1, [A1/D1] P2_2 / AN2_2 / A2, [A2/D2] P2_3 / AN2_3 / A3, [A3/D3] P2_4 / AN2_4 / A4, [A4/D4] P2_5 / AN2_5 / A5, [A5/D5] P2_6 / AN2_6 / A6, [A6/D6] P2_7 / AN2_7 / A7, [A7/D7] VSS P3_0/ A8, [A8/D8](7) VCC2 P12_0 / TXD6 P12_1 / CLK6 P12_2 / RXD6 P12_3 / CTS6 / RTS6 P12_4 P3_1 / A9, [A9/D9] P3_2 / A10, [A10/D10] P3_3 / A11, [A11/D11] P3_4 / A12, [A12/D12] P3_5/ A13, [A13/D13] P3_6/ A14, [A14/D14] P3_7 / A15, [A15/D15] P4_0 / A16 P4_1 / A17 VSS P4_2 / A18 VCC2 P4_3 / A19
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 P11_4 OUTC1_3 / INPC1_3 / P11_3 ISRXD1 / OUTC1_2 / INPC1_2 / P11_2 ISCLK1 / OUTC1_1 / INPC1_1 / P11_1 ISTXD1 / OUTC1_0 / INPC1_0 / P11_0 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN15_7 / RTS6 / CTS6 / P15_7 AN15_6 / CLK6 / P15_6 AN15_5 / RXD6 / P15_5 AN15_4 / TXD6 / P15_4 AN15_3 / RTS5 / CTS5 / P15_3 AN15_2 / ISRXD0 / RXD5 / P15_2 AN15_1 / ISCLK0 / CLK5 / P15_1 VSS AN15_0 / ISTXD0 / TXD5 / P15_0 VCC1 AN_7 / RTP3_3 / KI3 / P10_7 AN_6 / RTP3_2 / KI2 / P10_6 AN_5 / RTP3_1 / KI1 / P10_5 AN_4 / RTP3_0 / KI0 / P10_4 AN_3 / RTP1_3 / P10_3 AN_2 / RTP1_2 / P10_2 AN_1 / RTP1_1 / P10_1 AVSS AN_0 / RTP1_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144

(M32C/87, M32C/87A, M32C/87B) PLQP0144KA-A (144P6Q-A) (top view)
M32C/87 Group

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P12_5 P12_6 P12_7 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P13_0 / OUTC2_4 P13_1 / OUTC2_5 VCC2 P13_2 / OUTC2_6 VSS P13_3 / OUTC2_3 P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P13_4 / OUTC2_0 / ISTXD2 / IEOUT P13_5 / OUTC2_2 / ISRXD2 / IEIN P13_6 / OUTC2_1 / ISCLK2 P13_7 / OUTC2_7 P6_0 / RTP0_0 / CTS0 / RTS0 / SS0 P6_1 / RTP0_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT P6_4(3) P6_5 / CLK1 VSS P6_6 / RXD1 / SCL1 / STXD1 VCC1 P6_7 / TXD1 / SDA1 / SRXD1 P7_0(2) (4)
(note 6)
1
2
3
4
5
6
7
8
NOTES: 1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN 2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT 3. P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 4. P7_0 and P7_1 are N-channel open drain output ports. 5. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. 6. Refer to Package Dimensions for the pin1 position on the package. 7. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.3
Pin Assignment for 144-Pin Package
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 9 of 587
/ P9_6 / P9_5 / P9_4 / P9_3 / P9_2 / P9_1 / P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 (5) CAN1IN / CAN0IN / INT1 / P8_3 (5) CAN1OUT / CAN0OUT / INT0 / P8_2 OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1 ISRXD0 / RXD5 / U / TA4OUT / P8_0 ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7 ISTXD0 / OUTC1_3 / INPC1_3 / TXD5 / CAN0OUT / TA3OUT / P7_6 ISRXD0 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5 ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4 ISTXD1 / OUTC1_0 / INPC1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 (1) (4) P7_1 ANEX1 / SRXD4 / SDA4 / TXD4 / CAN1OUT (5) ANEX0 / CAN1WU / CAN1IN / CLK4 DA1 / SS4 / RTS4 / CTS4 / TB4IN DA0 / SS3 / RTS3 / CTS3 / TB3IN ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN CLK3 / TB0IN INT8 / INT7 / INT6 / OUTC1_7 / INPC1_7 / OUTC1_6 / INPC1_6 / OUTC1_5 / INPC1_5 / OUTC1_4 / INPC1_4 /
(5)
9
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.8
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BYTE 16 CNVSS 17 XCIN 18 XCOUT 19 RESET 20 XOUT 21 VSS 22 XIN 23 VCC1 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 VCC1 40 P6_6 RXD1/SCL1/STXD1 NOTE: 1. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 NMI INT2 INT1 INT0 TA4OUT/U TA3IN/RTP2_2 TA3OUT TA2IN/W/RTP2_1 TA2OUT/W/ RTP2_0 TA1IN/V TA1OUT/V TA0IN/TB5IN/ RTP0_3 CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 INPC1_7/OUTC1_7/ OUTC2_2/ISRXD2/IEIN INPC1_6/OUTC1_6/ OUTC2_0/ISTXD2/IEOUT CAN0IN/CAN1IN CAN0OUT/CAN1OUT TA4IN/U/RTP2_3 CTS5/RTS5 RXD5 CLK5/CAN0IN TXD5/CAN0OUT INPC1_5/OUTC1_5 ISRXD0 INPC1_4/OUTC1_4/ ISCLK0 INPC1_3/OUTC1_3/ ISTXD0 INPC1_2/OUTC1_2/ ISRXD1 INPC1_1/OUTC1_1/ ISCLK1 INPC1_0/OUTC1_0/ ISTXD1 P8_7 P8_6 Control Pin
1. Overview
144-Pin Package List of Pin Names (1/4)
Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 P14_6 P14_5 P14_4 P14_3 P14_2 P14_1 P14_0 INT8 INT7 INT6 INPC1_7/OUTC1_7 INPC1_6/OUTC1_6 INPC1_5/OUTC1_5 INPC1_4/OUTC1_4 TB4IN TB3IN TB2IN TB1IN TB0IN Interrupt Pin Timer Pin UART/CAN Pin(1) TXD4/SDA4/SRXD4/ CAN1OUT CLK4/CAN1IN/CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3 OUTC2_0/IEOUT/ISTXD2 IEIN/ISRXD2 Intelligent I/O Pin Analog Pin ANEX1 ANEX0 DA1 DA0 Bus Control Pin
TA0OUT/RTP0_2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.9
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 VSS 58 59 VCC2 60 61 63 64 65 66 67 68 69 70 71 72 73 74 VCC2 75 76 VSS 77 78 79 80 P4_1 P4_0 P3_7 P3_6 A17 A16 P4_2 A18 P13_1 P13_0 P5_2 P5_1 P5_0 P12_7 P12_6 P12_5 P4_7 P4_6 P4_5 P4_4 P4_3 OUTC2_5 OUTC2_4 P13_2 OUTC2_6 Control Pin
1. Overview
144-Pin Package List of Pin Names (2/4)
Port P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P13_7 P13_6 P13_5 P13_4 P5_7 P5_6 P5_5 P5_4 P13_3 OUTC2_3 RTP0_1 RTP0_0 Interrupt Pin Timer Pin UART/CAN Pin CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0/ IrDAOUT RXD0/SCL0/STXD0/ IrDAIN CLK0 CTS0/RTS0/SS0 OUTC2_7 OUTC2_1/ISCLK2 OUTC2_2/ISRXD2/ IEIN OUTC2_0/ISTXD2/ IEOUT RDY ALE HOLD HLDA/ALE OUTC2_1/ISCLK2 Intelligent I/O Pin Analog Pin Bus Control Pin
41 VSS
62 CLKOUT P5_3
BCLK/ALE RD WRH/BHE WRL/WR
CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19
A15,[A15/D15] A14,[A14/D14]
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.10
Pin No. 81 82 83 84 85 86 87 88 89 90 91 VCC2 92 93 VSS 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P11_4 P11_3 P11_2 P11_1 P11_0 P0_3 P0_2 INPC1_3/OUTC1_3 INPC1_2/OUTC1_2/ ISRXD1 INPC1_1/OUTC1_1/ ISCLK1 INPC1_0/OUTC1_0/ ISTXD1 AN0_3 AN0_2 D3 D2 AN0_7 AN0_6 AN0_5 AN0_4 INT5 INT4 INT3 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0 P3_0 Control Pin
1. Overview
144-Pin Package List of Pin Names (3/4)
Port P3_5 P3_4 P3_3 P3_2 P3_1 P12_4 P12_3 P12_2 P12_1 P12_0 CTS6/RTS6 RXD6 CLK6 TXD6 A8,[A8/D8] A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A0,[A0/D0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin Bus Control Pin A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9]
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 12 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Table 1.11
Pin No. 121 122 123 124 125 126 127 128 129 130 VSS 131 132 VCC1 133 134 135 136 137 138 139 140 AVSS 141 142 VREF 143 AVCC 144 P9_7 RXD4/SCL4/STXD4 ADTRG P10_0 RTP1_0 AN_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1 KI3 KI2 KI1 KI0 RTP3_3 RTP3_2 RTP3_1 RTP3_0 RTP1_3 RTP1_2 RTP1_1 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1 P15_0 TXD5 ISTXD0 AN15_0 Control Pin
1. Overview
144-Pin Package List of Pin Names (4/4)
Port P0_1 P0_0 P15_7 P15_6 P15_5 P15_4 P15_3 P15_2 P15_1 CTS6/RTS6 CLK6 RXD6 TXD6 CTS5/RTS5 RXD5 CLK5 ISRXD0 ISCLK0 Interrupt Pin Timer Pin UART/CAN Pin Intelligent I/O Pin Analog Pin AN0_1 AN0_0 AN15_7 AN15_6 AN15_5 AN15_4 AN15_3 AN15_2 AN15_1 Bus Control Pin D1 D0
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
( note 6) ( note 6)
P1_0 / D8 P1_1 / D9 P1_2 / D10 P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0, [A0/D0] P2_1 / AN2_1 / A1, [A1/D1] P2_2 / AN2_2 / A2, [A2/D2] P2_3 / AN2_3 / A3, [A3/D3] P2_4 / AN2_4 / A4, [A4/D4] P2_5 / AN2_5 / A5, [A5/D5] P2_6 / AN2_6 / A6, [A6/D6] P2_7 / AN2_7 / A7, [A7/D7] VSS P3_0 / A8, [A8/D8](6) VCC2 P3_1 / A9, [A9/D9] P3_2 / A10, [A10/D10] P3_3 / A11, [A11/D11] P3_4 / A12, [A12/D12] P3_5 / A13, [A13/D13] P3_6 / A14, [A14/D14] P3_7 / A15, [A15/D15] P4_0 / A16 P4_1 / A17 P4_2 / A18 P4_3 / A19
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN_7 / RTP3_3 / KI3 / P10_7 AN_6 / RTP3_2 / KI2 / P10_6 AN_5 / RTP3_1 / KI1 / P10_5 AN_4 / RTP3_0 / KI0 / P10_4 AN_3 / RTP1_3 / P10_3 AN_2 / RTP1_2 / P10_2 AN_1 / RTP1_1 / P10_1 AVSS AN_0 / RTP1_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
51

M32C/87 Group
(M32C/87,M32C/87A,M32C/87B) PRQP0100JB-A (100P6S-A) (top view)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P6_0 / RTP0_1 / CTS0 / RTS0 / SS0 P6_1 / RTP0_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 /TXD1 / SDA1 / SRXD1
( note 5)
NOTES: 1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN 2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT 3. P7_0 and P7_1 are N-channel open drain output ports. 4. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. 5. Refer to Package Dimensions for the pin1 position on the package. 6. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.4
Pin Assignment for 100-Pin Package
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 14 of 587
ANEX1 / CAN1OUT / SRXD4 / SDA4 / TXD4 / P9_6 (4) ANEX0 / CAN1WU / CAN1IN / CLK4 / P9_5 DA1 / SS4 / RTS4 / CTS4 / TB4IN / P9_4 DA0 / SS3 / RTS3 / CTS3 / TB3IN / P9_3 ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2 ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN / P9_1 CLK3 / TB0IN / P9_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 (4) CAN1IN / CAN0IN / INT1 / P8_3 (4) CAN1OUT / CAN0OUT / INT0 / P8_2 OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1 ISRXD0 / RXD5 / U / TA4OUT / P8_0 (4) ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7 (4) ISTXD0 / OUTC1_3 / INPC1_3 / CAN0OUT / TXD5 / TA3OUT / P7_6 ISRXD1 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5 ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4 ISTXD1 / OUTC1_0 / INPC1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3 CLK2 / V / TA1OUT / P7_2 (1)(3) P7_1 (2)(3) P7_0
(4)
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
( note 6) ( note 6) P1_3 / D11 P1_4 / D12 P1_5 / INT3 / D13 P1_6 / INT4 / D14 P1_7 / INT5 / D15 P2_0 / AN2_0 / A0, [A0/D0] P2_1 / AN2_1 / A1, [A1/D1] P2_2 / AN2_2 / A2, [A2/D2] P2_3 / AN2_3 / A3, [A3/D3] P2_4 / AN2_4 / A4, [A4/D4] P2_5 / AN2_5 / A5, [A5/D5] P2_6 / AN2_6 / A6, [A6/D6] P2_7 / AN2_7 / A7, [A7/D7] VSS P3_0 / A8, [A8/D8](6) VCC2 P3_1 / A9, [A9/D9] P3_2 / A10, [A10/D10] P3_3 / A11, [A11/D11] P3_4 / A12, [A12/D12] P3_5 / A13, [A13/D13] P3_6 / A14, [A14/D14] P3_7 / A15, [A15/D15] P4_0 / A16 P4_1 / A17
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
D10 / P1_2 D9 / P1_1 D8 / P1_0 D7 / AN0_7 / P0_7 D6 / AN0_6 / P0_6 D5 / AN0_5 / P0_5 D4 / AN0_4 / P0_4 D3 / AN0_3 / P0_3 D2 / AN0_2 / P0_2 D1 / AN0_1 / P0_1 D0 / AN0_0 / P0_0 AN_7 / RTP3_3 / KI3 / P10_7 AN_6 / RTP3_2 / KI2 / P10_6 AN_5 / RTP3_1 / KI1 / P10_5 AN_4 / RTP3_0 / KI0 / P10_4 AN_3 / RTP1_3 P10_3 AN_2 / RTP1_2 / P10_2 AN_1 / RTP1_1 / P10_1 AVSS AN_0 / RTP1_0 / P10_0 VREF AVCC ADTRG / STXD4 / SCL4 / RXD4 / P9_7 (4) ANEX1 / CAN1OUT / SRXD4 / SDA4 / TXD4 / P9_6 (4) ANEX0 / CAN1WU / CAN1IN / CLK4 / P9_5
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

M32C/87 Group
(M32C/87,M32C/87A,M32C/87B) PLQP0100KB-A (100P6Q-A) (top view)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
P4_2 / A18 P4_3 / A19 P4_4 / CS3 / A20 P4_5 / CS2 / A21 P4_6 / CS1 / A22 P4_7 / CS0 / A23 P5_0 / WRL / WR P5_1 / WRH / BHE P5_2 / RD P5_3 / CLKOUT / BCLK / ALE P5_4 / HLDA / ALE P5_5 / HOLD P5_6 / ALE P5_7 / RDY P6_0 / RTP0_0 / CTS0 / RTS0 / SS0 P6_1 / RTP0_1 / CLK0 P6_2 / RXD0 / SCL0 / STXD0 / IrDAIN P6_3 / TXD0 / SDA0 / SRXD0 / IrDAOUT P6_4 / CTS1 / RTS1 / SS1 / OUTC2_1 / ISCLK2 P6_5 / CLK1 P6_6 / RXD1 / SCL1 / STXD1 P6_7 /TXD1 / SDA1 / SRXD1 P7_0(2)(3) P7_1(1)(3) P7_2 / TA1OUT / V / CLK2
( note 5)
NOTES: 1. P7_1 / TA0IN / TB5IN / RTP0_3 / RXD2 / SCL2 / STXD2 / INPC1_7 / OUTC1_7 / OUTC2_2 / ISRXD2 / IEIN 2. P7_0 / TA0OUT / RTP0_2 / TXD2 / SDA2 / SRXD2 / INPC1_6 / OUTC1_6 / OUTC2_0 / ISTXD2 / IEOUT 3. P7_0 and P7_1 are N-channel open drain output ports. 4. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A. 5. Refer to Package Dimensions for the pin1 position on the package. 6. Pin names in brackets [ ] represent a single functional signal. They should not be considered as two separate functional signals.
Figure 1.5
Pin Assignment for 100-Pin Package
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 15 of 587
DA1 / SS4 / RTS4 / CTS4 / TB4IN / P9_4 DA0 / SS3 / RTS3 / CTS3 / TB3IN / P9_3 ISTXD2 / IEOUT / OUTC2_0 / SRXD3 / SDA3 / TXD3 / TB2IN / P9_2 ISRXD2 / IEIN / STXD3 / SCL3 / RXD3 / TB1IN / P9_1 CLK3 / TB0IN / P9_0 BYTE CNVSS XCIN / P8_7 XCOUT / P8_6 RESET XOUT VSS XIN VCC1 NMI / P8_5 INT2 / P8_4 (4) CAN1IN / CAN0IN / INT1 / P8_3 (4) CAN1OUT / CAN0OUT / INT0 / P8_2 OUTC1_5 / INPC1_5 / RTS5 / CTS5 / RTP2_3 / U / TA4IN / P8_1 ISRXD0 / RXD5 / U / TA4OUT / P8_0 (4)ISCLK0 / OUTC1_4 / INPC1_4 / CAN0IN / CLK5 / RTP2_2 / TA3IN / P7_7 (4) ISTXD0 / OUTC13 / INPC13 / CAN0OUT / TXD5 / TA3OUT / P7_6 ISRXD1 / OUTC1_2 / INPC1_2 / RTP2_1 / W / TA2IN / P7_5 ISCLK1 / OUTC1_1 / INPC1_1 / RTP2_0 / W / TA2OUT / P7_4 ISTXD1 / OUTC1_0 / INPC1_0 / SS2 / RTS2 / CTS2 / V / TA1IN / P7_3
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.12
Pin No. FP GP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 99 100 1 2 3 4 5 6 7 8 9 BYTE CNVSS XCIN XCOUT P8_7 P8_6
1. Overview
100-Pin Package List of Pin Names (1/3)
Port P9_6 P9_5 P9_4 P9_3 P9_2 P9_1 P9_0 TB4IN TB3IN TB2IN TB1IN TB0IN
Interrupt Pin
Control Pin
Timer Pin
UART/CAN Pin(1) TXD4/SDA4/SRXD4/ CAN1OUT CLK4/CAN1IN/ CAN1WU CTS4/RTS4/SS4 CTS3/RTS3/SS3 TXD3/SDA3/SRXD3 RXD3/SCL3/STXD3 CLK3
Intelligent I/O Pin
Analog Bus Control Pin Pin ANEX1 ANEX0 DA1 DA0
OUTC2_0/IEOUT/ISTXD2
IEIN/ISRXD2
10 RESET 11 XOUT 12 VSS 13 XIN 14 VCC1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 P8_5 P8_4 P8_3 P8_2 P8_1 P8_0 P7_7 P7_6 P7_5 P7_4 P7_3 P7_2 P7_1 P7_0 P6_7 P6_6 P6_5 P6_4 P6_3 P6_2 P6_1 P6_0 P5_7 P5_6 RTP0_1 RTP0_0 NMI INT2 INT1 INT0 TA4OUT/U TA3IN/RTP2_2 TA3OUT TA2IN/W/RTP2_1 TA2OUT/W/ RTP2_0 TA1IN/V TA1OUT/V TA0IN/TB5IN/ RTP0_3 CTS2/RTS2/SS2 CLK2 RXD2/SCL2/STXD2 INPC1_7/OUTC1_7/ OUTC2_2/ISRXD2/IEIN
INPC1_6/OUTC1_6/ OUTC2_0/ISTXD2/IEOUT
CAN0IN/CAN1IN CAN0OUT/CAN1OUT TA4IN/U/RTP2_3 CTS5/RTS5 RXD5 CLK5/CAN0IN TXD5/CAN0OUT INPC1_5/OUTC1_5 ISRXD0 INPC1_4/OUTC1_4/ ISCLK0 INPC1_3/OUTC1_3/ ISTXD0 INPC1_2/OUTC1_2 ISRXD1 INPC1_1/OUTC1_1/ ISCLK1 INPC1_0/OUTC1_0/ ISTXD1
TA0OUT/RTP0_2 TXD2/SDA2/SRXD2 TXD1/SDA1/SRXD1 RXD1/SCL1/STXD1 CLK1 CTS1/RTS1/SS1 TXD0/SDA0/SRXD0/ IrDAOUT RXD0/SCL0/STXD0/ IrDAIN CLK0 CTS0/RTS0/SS0
OUTC2_1/ISCLK2
RDY ALE
NOTE: 1. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.13
Pin No. FP GP 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 39 40 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VCC2 61 62 VSS 63 64 65 66 67 68 69 70
1. Overview
100-Pin Package List of Pin Names (2/3)
Port P5_5 P5_4 P5_2 P5_1 P5_0 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_7 P3_6 P3_5 P3_4 P3_3 P3_2 P3_1 P3_0 P2_7 P2_6 P2_5 P2_4 P2_3 P2_2 P2_1 P2_0 AN2_7 AN2_6 AN2_5 AN2_4 AN2_3 AN2_2 AN2_1 AN2_0
Interrupt Pin
Control Pin
Timer Pin
UART/CAN Pin
Intelligent I/O Pin
Analog Pin
Bus Control Pin HOLD HLDA/ALE BCLK/ALE RD WRH/BHE WRL/WR CS0/A23 CS1/A22 CS2/A21 CS3/A20 A19 A18 A17 A16 A15,[A15/D15] A14,[A14/D14] A13,[A13/D13] A12,[A12/D12] A11,[A11/D11] A10,[A10/D10] A9,[A9/D9] A8,[A8/D8] A7,[A7/D7] A6,[A6/D6] A5,[A5/D5] A4,[A4/D4] A3,[A3/D3] A2,[A2/D2] A1,[A1/D1] A0,[A0/D0]
41 CLKOUT P5_3
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.14
Pin No. FP GP 73 71 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 AVSS 95 96 VREF 97 AVCC 98 P10_0 RTP1_0 AN_0
1. Overview
100-Pin Package List of Pin Names (3/3)
Port P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P1_0 P0_7 P0_6 P0_5 P0_4 P0_3 P0_2 P0_1 P0_0 P10_7 P10_6 P10_5 P10_4 P10_3 P10_2 P10_1
Interrupt Pin
Control Pin
Timer Pin
UART/CAN Pin
Intelligent I/O Pin
Analog Bus Control Pin Pin D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
INT5 INT4 INT3
KI3 KI2 KI1 KI0
RTP3_3 RTP3_2 RTP3_1 RTP3_0 RTP1_3 RTP1_2 RTP1_1
AN0_7 AN0_6 AN0_5 AN0_4 AN0_3 AN0_2 AN0_1 AN0_0 AN_7 AN_6 AN_5 AN_4 AN_3 AN_2 AN_1
P9_7
RXD4/SCL4/STXD4
ADTRG
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.5
Pin Functions
Pin Functions (100-Pin and 144-Pin Packages) (1/4)
Symbol VCC1,VCC2 VSS AVCC AVSS RESET CNVSS I/O Supply Description Type Voltage - - Apply 3.0 to 5.5 V to pins VCC1 and VCC2, and 0 V to the VSS pin. The input condition of VCC1 VCC2 must be met. - VCC1 Power supply input pins to the A/D converter and D/A converter. Connect the AVCC pin to VCC1, and the AVSS pin to VSS. I I VCC1 VCC1 The MCU is placed in the reset state while applying an "L" signal to the RESET pin. This pin switches processor mode. Apply an "L" to the CNVSS pin to start up in single-chip mode, or an "H" to start up in microprocessor mode (mask ROM, flash memory version) and boot mode (flash memory version). This pin switches a data bus width in external memory space 3. A data bus is 16 bits wide when the BYTE pin is held "L" and 8 bits wide when it is held "H". Fix to either "L" or "H". Apply an "L" to the BYTE pin in single-chip mode. Data (D0 to D7) input/output pins while accessing an external memory space with separate bus. Data (D8 to D15) input/output pins while accessing an external memory space with 16-bit separate bus. Address bits (A0 to A22) output pins. Inverted address bit (A23) output pin. Data (D0 to D7) input/output and 8 low-order address bits (A0 to A7) output are performed by time-sharing these pins while accessing an external memory space with multiplexed bus. Data (D8 to D15) input/output and 8 middle-order address bits (A8 to A15) output are performed by time-sharing these pins while accessing an external memory space with 16-bit multiplexed bus. Chip-select signal output pins used to specify external devices. WRL, WRH, (WR, BHE) and RD signal output pins. WRL and WRH can be switched with WR and BHE by a program. * WRL, WRH and RD are selected: If external data bus is 16 bits wide, data is written to an even address in external memory space while an "L" is output from the WRL pin. Data is written to an odd address while an "L" is output from the WRH pin. Data is read while an "L" is output from the RD pin. * WR, BHE and RD are selected: Data is written while an "L" is output from the WR pin. Data is read while an "L" is output from the RD pin. Data in odd address is accessed while an "L" is output from the BHE pin. Select WR, BHE and RD when an external data bus is 8 bits wide. ALE signal is used for the external devices to latch address signals when the multiplexed bus is selected. The MCU is placed in a hold state while an "L" signal is applied to the HOLD pin. The HLDA pin outputs an "L" while the MCU is placed in a hold state. Bus is placed in a wait state while an "L" signal is applied to the RDY pin.
Table 1.15
Type Power supply Analog power supply input Reset input CNVSS
External data bus width select input Bus control Pins
BYTE
I
VCC1
D0 to D7 D8 to D15 A0 to A22 A23 A0/D0 to A7/D7 A8/D8 to A15/D15 CS0 to CS3 WRL/WR WRH/BHE RD
I/O I/O O O I/O
VCC2 VCC2 VCC2 VCC2 VCC2
I/O
VCC2
O O
VCC2 VCC2
ALE HOLD HLDA RDY
O I O I
VCC2 VCC2 VCC2 VCC2
I: Input
O: Output
I/O: Input and output
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.16
Type Main clock input Main clock output Sub clock input Sub clock output BCLK output Clock output INT interrupt input NMI interrupt input Timer A XIN XOUT XCIN XCOUT BCLK CLKOUT INT0 to INT2 INT3 to INT5 NMI TA0OUT to TA4OUT TA0IN to TA4IN TB0IN to TB5IN U, U, V, V, W, W CTS0 to CTS5 RTS0 to RTS5 CLK0 to CLK5 RXD0 to RXD5 TXD0 to TXD5 SDA0 to SDA4 SCL0 to SCL4 STXD0 to Serial STXD4 interface special function SRXD0 to SRXD4 SS0 to SS4 IrDA CAN(1) IrDAIN IrDAOUT CAN0IN, CAN1IN CAN0OUT, CAN1OUT CAN1WU
1. Overview
Pin Functions (100-Pin and 144-Pin Packages) (2/4)
Symbol I/O Supply Description Type Voltage I VCC1 Input/output pins for the main clock oscillation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To O VCC1 apply an external clock, apply it to XIN and leave XOUT open. I O O O I I I I/O I I O VCC1 VCC1 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 NMI interrupt input pin. Connect the NMI pin to VCC1 via a resistor when the NMI interrupt is not used. Timer A0 to A4 input/output pins. (TA0OUT is N-channel open drain output.) Timer A0 to A4 input pins. Timer B0 to B5 input pins. Three-phase motor control timer output pins. Input/output pins for the sub clock oscillation circuit. Connect a crystal oscillator between XCIN and XCOUT. To apply an external clock, apply it to XCIN and leave XCOUT open. Bus clock output pin. The CLKOUT pin outputs the clock having the same frequency as fC, f8, or f32. INT interrupt input pins.
Timer B Three-phase motor control timer output Serial interface
I O I/O I O I/O I/O O I I I O I O I
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1
Input pins to control data transmission. Output pins to control data reception. Serial clock input/output pins. Serial data input pins. Serial data output pins. (TXD2 is N-channel open drain output.) Serial data input/output pins. (SDA2 is N-channel open drain output.) Serial clock input/output pins. (SCL2 is N-channel open drain output.) Serial data output pins when slave mode is selected. (STXD2 is N-channel open drain output.) Serial data input pins when slave mode is selected. Control input pins used in the serial interface special mode. IrDA serial data input pin. IrDA serial data output pin. Received data input pins for the CAN communication function. Transmit data output pins for the CAN communication function. CAN wake-up interrupt input pin.
I2C mode
I: Input O: Output I/O: Input and output NOTE: 1. The CAN pins cannot be used in M32C/87B. Only CAN0 pins can be used in M32C/87A.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.17
Type Intelligent I/O
1. Overview
Pin Functions (100-Pin and 144-Pin Package) (3/4)
Symbol INPC1_0 to INPC1_3 INPC1_4 to INPC1_7 OUTC1_0 to OUTC1_3 OUTC1_4 to OUTC1_7 OUTC2_0 to OUTC2_2 ISCLK0 ISCLK1, ISCLK2 ISRXD0 ISRXD1, ISRXD2 ISTXD0 ISTXD1, ISTXD2 IEIN IEOUT I/O Supply Description Type Voltage I VCC1/ Input pins for the time measurement function. VCC2(1) I VCC1 O VCC1/ Output pins for the waveform generation function. VCC2(1) (OUTC1_6/OUTC2_0 and OUTC1_7/OUTC2_2 assigned to ports 7_0 and 7_1 are N-channel open drain output.) VCC1 VCC1/ VCC2(1) VCC1 VCC1/ VCC2(1) VCC1 VCC1/ VCC2(1) VCC1 VCC1/ VCC2(1) VCC1/ VCC2(1) VCC1/ VCC2(1) - VCC1 VCC2
O O I/O I/O I I O O I O I I I
Clock input/output pins for the intelligent I/O communication function. Data input pins for the intelligent I/O communication function.
Data output pins for the intelligent I/O communication function. (ISTXD2 assigned to port 7_0 is N-channel open drain output.) Data input pin for the intelligent I/O communication function. Data output pin for the intelligent I/O communication function. (IEOUT assigned to port 7_0 is N-channel open drain output.) The VREF pin supplies the reference voltage to the A/D converter and D/A converter. Analog input pins for the A/D converter.
Reference voltage input A/D converter
VREF AN_0 to AN_7 AN0_0 to AN0_7, AN2_0 to AN2_7 ADTRG ANEX0
I I/O I O O
VCC1 VCC1 VCC1 VCC1 VCC1
External trigger input pin for the A/D converter. Extended analog input pin for the A/D converter or output pin in external op-amp connection mode. Extended analog input pin for the A/D converter. Output pins for the D/A converter. These pins function as real-time ports. (RTP0_2 and RTP0_3 are N-channel open drain output.)
ANEX1 D/A converter DA0, DA1 Real-time port RTP0_0 to RTP0_3 RTP1_0 to RTP1_3 RTP2_0 to RTP2_3 RTP3_0 to RTP3_3
I: Input O: Output I/O: Input and output NOTE: 1. Only VCC1 can be used in the 100-pin package.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.18
Type I/O port
1. Overview
Pin Functions (100-Pin and 144-Pin Package) (4/4)
I/O Supply Description Type Voltage P0_0 to P0_7, I/O VCC2 8-bit CMOS I/O ports. The Port Pi Direction Register (i = 0 to 15) P1_0 to P1_7, determines if each pin is used as an input port or an output port. P2_0 to P2_7, The Pull-Up Control Registers determine if the input ports, divided P3_0 to P3_7, into groups of four, are pulled up or not. P4_0 to P4_7, P5_0 to P5_7 P6_0 to P6_7, I/O VCC1 These 8-bit I/O ports are functionally equivalent to P0. P7_0 to P7_7, (P7_0 and P7_1 are N-channel open drain output.) P9_0 to P9_7, P10_0 to P10_7 P8_0 to P8_4 I/O VCC1 These I/O ports are functionally equivalent to P0. P8_6, P8_7 P8_5 I VCC1 Shares the pin with NMI. Input port to read NMI pin level. Symbol KI0 to KI3 I VCC1 Key input interrupt input pins.
Input port Key input interrupt input I: Input
O: Output
I/O: Input and output
Table 1.19
Type INT Interrupt Input Serial interface
Pin Functions (144-Pin Package Only)
Symbol INT6 to INT8 CTS6 RTS6 CLK6 RXD6 TXD6 I/O Supply Type Voltage I VCC1 INT interrupt input pins. I O I/O I O O I I/O VCC1/ VCC2 VCC1/ VCC2 VCC1/ VCC2 VCC1/ VCC2 VCC1/ VCC2 VCC2 VCC1 VCC2 Description
Input pin to control data transmission. Output pin to control data reception. Serial clock input/output pin. Serial data input pin. Serial data output pin. Output pins for the waveform generation function. Analog input pins for the A/D converter. These I/O ports are functionally equivalent to P0.
Intelligent I/O A/D converter I/O port
OUTC2_3 to OUTC2_7 AN15_0 to AN15_7 P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7 P14_0 to P14_6, P15_0 to P15_7
I/O
VCC1
These I/O ports are functionally equivalent to P0.
I: Input
O: Output
I/O: Input and output
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
2. Central Processing Unit (CPU)
2.
Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of eight registers (R0, R1, R2, R3, A0, A1, SB, and FB) out of 28 CPU registers. There are two sets of register banks.
b31
b15
General registers
R2 R2 R3 R3
b23
R0H R0H R1H R1H A0 A0 A1 A1 SB SB FB FB USP ISP INTB PC
b15
R2 R2 R3 R3
R0L R0L R1L R1L
b0
Data registers(1)
Address registers(1) Static base register(1) Frame base register(1) User stack pointer Interrupt stack pointer Interrupt table register Program counter
FLG
IPL
b8 b7
Flag register
b0
U I OBSZDC
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved Processor interrupt priority level Reserved
High-speed interrupt registers
b15 b23
SVP VCT
SVF
b0
Flag save register PC save register Vector register
DMAC-associated registers
b15
b7
b23
DMA0 DMA1 DRA0 DRA1 DSA0 DSA1
DCT0 DCT1 DRC0 DRC1
DMD0 DMD1
b0
DMA mode registers DMA transfer count registers DMA transfer count reload registers DMA memory address registers DMA memory address reload registers DMA SFR address registers
NOTE: 1. These registers comprise a register bank. There are two sets of register banks (register bank 0 and register bank 1).
Figure 2.1
CPU Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
2. Central Processing Unit (CPU)
2.1 2.1.1
General Registers Data Registers (R0, R1, R2, and R3)
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers. R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
2.1.2
Address Registers (A0 and A1)
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer, arithmetic and logic operations.
2.1.3
Static Base Register (SB)
SB is a 24-bit register used for SB-relative addressing.
2.1.4
Frame Base Register (FB)
FB is a 24-bit register used for FB-relative addressing.
2.1.5
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP. Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an interrupt sequence efficiently.
2.1.6
Interrupt Table Register (INTB)
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
2.1.7
Program Counter (PC)
PC is 24 bits wide and indicates the address of the next instruction to be executed.
2.1.8
Flag Register (FLG)
FLG is a 16-bit register indicating the CPU state.
2.1.8.1
Carry Flag (C)
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
2.1.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.1.8.3
Zero Flag (Z)
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
2.1.8.4
Sign Flag (S)
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
2.1.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
2.1.8.6
Overflow Flag (O)
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
2. Central Processing Unit (CPU)
2.1.8.7
Interrupt Enable Flag (I)
The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0 and enabled when it is set to 1. The I flag becomes 0 when an interrupt request is acknowledged.
2.1.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0. USP is selected when the U flag is set to 1. The U flag becomes 0 when a hardware interrupt request is acknowledged or the INT instruction specifying software interrupt numbers 0 to 31 is executed.
2.1.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority level than IPL, the interrupt is enabled.
2.1.8.10 Reserved Space
Only write 0 to bits assigned to the reserved space. When read, the bits return undefined values.
2.2
High-Speed Interrupt Registers
Registers associated with the high-speed interrupt are as follows: * Flag save register (SVF) * PC save register (SVP) * Vector register (VCT) Refer to 11.4 High-Speed Interrupt for details.
2.3
DMAC-Associated Registers
Registers associated with the DMAC are as follows: * DMA mode register (DMD0, DMD1) * DMA transfer count register (DCT0, DCT1) * DMA transfer count reload register (DRC0, DRC1) * DMA memory address register (DMA0, DMA1) * DMA memory address reload register (DRA0, DRA1) * DMA SFR address register (DSA0, DSA1) Refer to 13. DMAC for details.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
3. Memory
3.
Memory
Figure 3.1 shows a memory map of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has 16-Mbyte address space from addresses 000000h to FFFFFFh. The internal ROM is allocated in lower addresses, beginning with address FFFFFFh. For example, a 512-Kbyte internal ROM area is allocated in addresses F80000h to FFFFFFh. The fixed interrupt vectors are allocated in addresses FFFFDCh to FFFFFFh. They store the starting address of each interrupt routine. Refer to 11. Interrupts for details. The internal RAM is allocated higher addresses, beginning with address 000400h. For example, a 48-Kbyte internal RAM area is allocated in addresses 000400h to 00C3FFh. The internal RAM is used not only for storing data but for the stacks when subroutines are called or when interrupt requests are acknowledged. SFRs are allocated in addresses 000000h to 0003FFh. The peripheral function control registers such as for I/O ports, A/D converters, serial interfaces, timers are allocated here. All blank spaces within SFRs are reserved and cannot be accessed by users. The special page vectors are allocated addresses FFFE00h to FFFFDBh. They are used for the JMPS instruction and JSRS instruction. Refer to the Renesas publication M32C/80 Series Software Manual for details.
000000h SFR 000400h Internal RAM Capacity 24 Kbytes 31 Kbytes 48 Kbytes XXXXXXh 0063FFh 007FFFh 00C3FFh Internal RAM XXXXXXh Reserved 00F000h 00FFFFh Internal ROM(3) (Data space) External space(1) Internal ROM Capacity 384 Kbytes 512 Kbytes 768 Kbytes 1024 Kbytes YYYYYYh FA0000h F80000h F40000h F00000h F00000h YYYYYYh Internal ROM(4) FFFFFFh FFFFFFh FFFFDCh FFFE00h Special page vector table
Undefined instruction
Overflow BRK instruction Address match
Watchdog timer (5)
Reserved(2)
NMI Reset
NOTES: 1. The space is used as the external space in memory expansion mode and in microprocessor mode. It is reserved in single-ship mode. 2. The space is reserved in memory expansion mode. It is used as the external space in microprocessor mode. 3. Additional 4-Kbyte space is provided in the flash memory version to store data. This space is used in single-chip mode and memory expansion mode. It is reserved in microprocessor mode. 4. This space is used in single-chip mode and memory expansion mode. It is used as the external space in microprocessor mode. 5. The watchdog timer interrupt, oscillation stop detection interrupt, and Vdet4 detection interrupt use the same vector.
Figure 3.1
Memory Map
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
4. Special Function Registers (SFRs)
4.
Special Function Registers (SFRs)
Special Function Registers (SFRs) are the control registers of peripheral functions. Tables 4.1 to 4.20 list SFR address maps. Table 4.1
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh Vdet4 Detection Interrupt Register D4INT XX00 0000b X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. Bits PM01 and PM00 in the PM0 register maintain values set before reset, even after software reset or watchdog timer reset has been performed. Address Match Interrupt Register 5 RMAD5 000000h Address Match Interrupt Register 4 RMAD4 000000h PLL Control Register 0 PLL Control Register 1 PLC0 PLC1 0001 X010b 000X 0000b Address Match Interrupt Register 3 RMAD3 000000h Voltage Detection Register 1 VCR1 0000 1000b Address Match Interrupt Register 2 RMAD2 000000h Voltage Detection Register 2 VCR2 00h Address Match Interrupt Register 1 RMAD1 000000h Processor Mode Register 2 PM2 00h Address Match Interrupt Register 0 RMAD0 000000h Address Match Interrupt Enable Register Protect Register External Data Bus Width Control Register Main Clock Division Register Oscillation Stop Detection Register Watchdog Timer Start Register Watchdog Timer Control Register AIER PRCR DS MCD CM2 WDTS WDC 00h XXXX 0000b XXXX 1000b(BYTE="L") XXXX 0000b(BYTE="H") XXX0 1000b 00h XXh 00XX XXXXb Processor Mode Register 0(1) Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1
1000 0000b(CNVSS="L") 0000 0011b(CNVSS="H")
SFR Address Map (1/20)
Register Symbol After Reset
00h 0000 1000b 0010 0000b
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.2
Address 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh X: Undefined Blank spaces are all reserved. No access is allowed. Flash Memory Control Register 0 Flash Memory Control Register 1 External Space Wait Control Register 0 External Space Wait Control Register 1 External Space Wait Control Register 2 External Space Wait Control Register 3 Address Match Interrupt Register 7 Address Match Interrupt Register 6
4. Special Function Registers (SFRs)
SFR Address Map (2/20)
Register Symbol After Reset
RMAD6
000000h
RMAD7
000000h
EWCR0 EWCR1 EWCR2 EWCR3
X0X0 0011b X0X0 0011b X0X0 0011b X0X0 0011b
FMR1 FMR0
0000 0X0Xb
0000 0001b(Flash Memory) XXXX XXX0b(Mask ROM)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 28 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.3
Address 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh DMA1 Interrupt Control Register UART2 Transmit/NACK Interrupt Control Register DMA3 Interrupt Control Register UART3 Transmit/NACK Interrupt Control Register Timer A1 Interrupt Control Register UART4 Transmit/NACK Interrupt Control Register Timer A3 Interrupt Control Register UART2 Bus Conflict Detection Interrupt Control Register II/O Interrupt Control Register 11 / CAN0 Interrupt Control Register 2 DMA0 Interrupt Control Register Timer B5 Interrupt Control Register DMA2 Interrupt Control Register UART2 Receive/ACK Interrupt Control Register Timer A0 Interrupt Control Register UART3 Receive/ACK Interrupt Control Register Timer A2 Interrupt Control Register UART4 Receive/ACK Interrupt Control Register Timer A4 Interrupt Control Register UART0/UART3 Bus Conflict Detection Interrupt Control Register UART0 Receive/ACK Interrupt Control Register A/D0 Conversion Interrupt Control Register UART1 Receive/ACK Interrupt Control Register II/O Interrupt Control Register 0 / CAN1 interrupt Control Register 0 Timer B1 Interrupt Control Register II/O Interrupt Control Register 2 Timer B3 Interrupt Control Register II/O Interrupt Control Register 4 INT5 Interrupt Control Register II/O Interrupt Control Register 6 INT3 Interrupt Control Register II/O Interrupt Control Register 8 INT1 Interrupt Control Register II/O Interrupt Control Register 10 / CAN0 Interrupt Control Register 1
4. Special Function Registers (SFRs)
SFR Address Map (3/20)
Register Symbol After Reset
DM0IC TB5IC DM2IC S2RIC TA0IC S3RIC TA2IC S4RIC TA4IC BCN0IC/BCN3IC S0RIC AD0IC S1RIC IIO0IC/CAN3IC TB1IC IIO2IC TB3IC IIO4IC INT5IC IIO6IC INT3IC IIO8IC INT1IC IIO10IC/CAN1IC IIO11IC/CAN2IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX X000b XXXX X000b
DM1IC S2TIC DM3IC S3TIC TA1IC S4TIC TA3IC BCN2IC
XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.4
Address 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh to 00DFh X: Undefined Blank spaces are all reserved. No access is allowed. Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Enable Register 3 Interrupt Enable Register 4 Interrupt Enable Register 5 Interrupt Enable Register 6 Interrupt Enable Register 7 Interrupt Enable Register 8 Interrupt Enable Register 9 Interrupt Enable Register 10 Interrupt Enable Register 11
4. Special Function Registers (SFRs)
SFR Address Map (4/20)
Register UART0 Transmit/NACK Interrupt Control Register UART1/UART4 Bus Conflict Detection Interrupt Control Register UART1 Transmit/NACK Interrupt Control Register Key Input Interrupt Control Register Timer B0 Interrupt Control Register II/O Interrupt Control Register 1 / CAN1 Interrupt Control Register 1 Timer B2 Interrupt Control Register II/O Interrupt Control Register 3 Timer B4 Interrupt Control Register II/O Interrupt Control Register 5 /CAN1 Interrupt Control Register 2 INT4 Interrupt Control Register II/O Interrupt Control Register 7 INT2 Interrupt Control Register II/O Interrupt Control Register 9 / CAN0 Interrupt Control Register 0 INT0 Interrupt Control Register Exit Priority Register Interrupt Request Register 0 Interrupt Request Register 1 Interrupt Request Register 2 Interrupt Request Register 3 Interrupt Request Register 4 Interrupt Request Register 5 Interrupt Request Register 6 Interrupt Request Register 7 Interrupt Request Register 8 Interrupt Request Register 9 Interrupt Request Register 10 Interrupt Request Register 11 S0TIC BCN1IC/BCN4IC S1TIC KUPIC TB0IC IIO1IC/CAN4IC TB2IC IIO3IC TB4IC IIO5IC/CAN5IC INT4IC IIO7IC INT2IC IIO9IC/CAN0IC INT0IC RLVL IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Symbol After Reset XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX X000b XX00 X000b XXXX 0000b 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb 0000 000Xb
IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE
00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.5
Address 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h Group 0 Receive CRC Code Register Group 0 Transmit CRC Code Register Group 0 SI/O Expansion Mode Register Group 0 SI/O Extended Receive Control Register Group 0 SI/O Special Communication Interrupt Detection Register Group 0 SI/O Extended Transmit Control Register Group 1 Time Measurement/Waveform Generation Register 0 Group 1 Time Measurement/Waveform Generation Register 1 Group 1 Time Measurement/Waveform Generation Register 2 Group 1 Time Measurement/Waveform Generation Register 3 Group 1 Time Measurement/Waveform Generation Register 4 Group 1 Time Measurement/Waveform Generation Register 5 Group 1 Time Measurement/Waveform Generation Register 6 Group 1 Time Measurement/Waveform Generation Register 7 Group 1 Waveform Generation Control Register 0 Group 1 Waveform Generation Control Register 1 Group 1 Waveform Generation Control Register 2 Group 1 Waveform Generation Control Register 3 Group 1 Waveform Generation Control Register 4 Group 1 Waveform Generation Control Register 5 Group 1 Waveform Generation Control Register 6 Group 1 Waveform Generation Control Register 7 Group 1 Time Measurement Control Register 0 Group 1 Time Measurement Control Register 1 Group 0 Receive Input Register Group 0 SI/O Communication Mode Register Group 0 Transmit Output Register Group 0 SI/O Communication Control Register Group 0 Data Compare Register 0 Group 0 Data Compare Register 1 Group 0 Data Compare Register 2 Group 0 Data Compare Register 3 Group 0 Data Mask Register 0 Group 0 Data Mask Register 1 Communication Clock Select Register Group 0 SI/O Receive Buffer Register Group 0 Transmit Buffer/Receive Data Register
4. Special Function Registers (SFRs)
SFR Address Map (5/20)
Register Symbol After Reset
G0RB G0TB/G0DR G0RI G0MR G0TO G0CR G0CMP0 G0CMP1 G0CMP2 G0CMP3 G0MSK0 G0MSK1 CCS
XXXX XXXXb XXX0 XXXXb XXh XXh 00h XXh 0000 X011b XXh XXh XXh XXh XXh XXh XXXX 0000b
G0RCRC G0TCRC G0EMR G0ERC G0IRF G0ETC G1TM0/G1PO0 G1TM1/G1PO1 G1TM2/G1PO2 G1TM3/G1PO3 G1TM4/G1PO4 G1TM5/G1PO5 G1TM6/G1PO6 G1TM7/G1PO7 G1POCR0 G1POCR1 G1POCR2 G1POCR3 G1POCR4 G1POCR5 G1POCR6 G1POCR7 G1TMCR0 G1TMCR1
XXXXh 0000h 00h 00h 0000 XXXXb 0000 0XXXb XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 0X00 X000b 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 31 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.6
Address 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh Group 1 Receive CRC Code Register Group 1 Transmit CRC Code Register Group 1 SI/O Expansion Mode Register Group 1 SI/O Extended Receive Control Register Group 1 SI/O Special Communication Interrupt Detection Register Group 1 SI/O Extended Transmit Control Register Group 2 Waveform Generation Register 0 Group 2 Waveform Generation Register 1 Group 2 Waveform Generation Register 2 Group 2 Waveform Generation Register 3 Group 2 Waveform Generation Register 4 Group 2 Waveform Generation Register 5 Group 2 Waveform Generation Register 6 Group 2 Waveform Generation Register 7 Group 1 Receive Input Register Group 1 SI/O Communication Mode Register Group 1 Transmit Output Register Group 1 SI/O Communication Control Register Group 1 Data Compare Register 0 Group 1 Data Compare Register 1 Group 1 Data Compare Register 2 Group 1 Data Compare Register 3 Group 1 Data Mask Register 0 Group 1 Data Mask Register 1
4. Special Function Registers (SFRs)
SFR Address Map (6/20)
Register Group 1 Time Measurement Control Register 2 Group 1 Time Measurement Control Register 3 Group 1 Time Measurement Control Register 4 Group 1 Time Measurement Control Register 5 Group 1 Time Measurement Control Register 6 Group 1 Time Measurement Control Register 7 Group 1 Base Timer Register Group 1 Base Timer Control Register 0 Group 1 Base Timer Control Register 1 Group 1 Time Measurement Prescaler Register 6 Group 1 Time Measurement Prescaler Register 7 Group 1 Function Enable Register Group 1 Function Select Register Group 1 SI/O Receive Buffer Register Group 1 Transmit Buffer/Receive Data Register Symbol G1TMCR2 G1TMCR3 G1TMCR4 G1TMCR5 G1TMCR6 G1TMCR7 G1BT G1BCR0 G1BCR1 G1TPR6 G1TPR7 G1FE G1FS G1RB G1TB/G1DR G1RI G1MR G1TO G1CR G1CMP0 G1CMP1 G1CMP2 G1CMP3 G1MSK0 G1MSK1 00h 00h 00h 00h 00h 00h XXXXh 00h X000 000Xb 00h 00h 00h 00h XXXX XXXXb X000 XXXXb XXh XXh 00h XXh 0000 X011b XXh XXh XXh XXh XXh XXh After Reset
G1RCRC G1TCRC G1EMR G1ERC G1IRF G1ETC G2PO0 G2PO1 G2PO2 G2PO3 G2PO4 G2PO5 G2PO6 G2PO7
XXXXh 0000h 00h 00h 0000 XXXXb 0000 0XXXb XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.7
Address 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh to 01BFh X: Undefined Blank spaces are all reserved. No access is allowed. Input Function Select Register B Input Function Select Register Input Function Select Register A Group 2 SI/O Communication Mode Register Group 2 SI/O Communication Control Register Group 2 SI/O Transmit Buffer Register Group 2 SI/O Receive Buffer Register Group 2 IEBus Address Register Group 2 IEBus Control Register Group 2 IEBus Transmit Interrupt Source Detection Register Group 2 IEBus Receive Interrupt Source Detection Register Group 2 Function Enable Register Group 2 RTP Output Buffer Register Group 2 Base Timer Register Group 2 Base Timer Control Register 0 Group 2 Base Timer Control Register 1 Base Timer Start Register
4. Special Function Registers (SFRs)
SFR Address Map (7/20)
Register Group 2 Waveform Generation Control Register 0 Group 2 Waveform Generation Control Register 1 Group 2 Waveform Generation Control Register 2 Group 2 Waveform Generation Control Register 3 Group 2 Waveform Generation Control Register 4 Group 2 Waveform Generation Control Register 5 Group 2 Waveform Generation Control Register 6 Group 2 Waveform Generation Control Register 7 Symbol G2POCR0 G2POCR1 G2POCR2 G2POCR3 G2POCR4 G2POCR5 G2POCR6 G2POCR7 00h 00h 00h 00h 00h 00h 00h 00h After Reset
G2BT G2BCR0 G2BCR1 BTSR G2FE G2RTP
XXXXh 00h 00h XXXX 0000b 00h 00h
G2MR G2CR G2TB G2RB IEAR IECR IETIF IERIF
00XX X000b 0000 X000b XXXXh XXXXh XXXXh 00XX X000b XXX0 0000b XXX0 0000b
IPSB IPS IPSA
00h 00h 00h
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.8
Address 01C0h 01C1h 01C2h 01C3h 01C4h 01C5h 01C6h 01C7h 01C8h 01C9h 01CAh 01CBh 01CCh 01CDh 01CEh 01CFh 01D0h 01D1h 01D2h 01D3h 01D4h 01D5h 01D6h 01D7h 01D8h 01D9h 01DAh 01DBh 01DCh 01DDh 01DEh 01DFh 01E0h 01E1h 01E2h 01E3h 01E4h 01E5h 01E6h 01E7h 01E8h 01E9h 01EAh 01EBh 01ECh 01EDh 01EEh 01EFh CAN0 Message Slot Buffer 0 Standard ID0(1)(2) CAN0 Message Slot Buffer 0 Standard ID1(1)(2) CAN0 Message Slot Buffer 0 Extended ID0(1)(2) CAN0 Message Slot Buffer 0 Extended ID1(1)(2) CAN0 Message Slot Buffer 0 Extended ID2(1)(2) CAN0 Message Slot Buffer 0 Data Length Code(1)(2) CAN0 Message Slot Buffer 0 Data 0(1)(2) CAN0 Message Slot Buffer 0 Data 1(1)(2) CAN0 Message Slot Buffer 0 Data 2(1)(2) CAN0 Message Slot Buffer 0 Data 3(1)(2) CAN0 Message Slot Buffer 0 Data 4(1)(2) CAN0 Message Slot Buffer 0 Data 5(1)(2) CAN0 Message Slot Buffer 0 Data 6(1)(2) CAN0 Message Slot Buffer 0 Data 7(1)(2) CAN0 Message Slot Buffer 0 Time Stamp High-Order(1)(2) CAN0 Message Slot Buffer 0 Time Stamp Low-Order(1)(2) RTP Output Buffer Register 0 RTP Output Buffer Register 1 RTP Output Buffer Register 2 RTP Output Buffer Register 3 UART5 Baud Rate Register UART5 Transmit Buffer Register UART5 Transmit/Receive Control Register 0 UART5 Transmit/Receive Control Register 1 UART5 Receive Buffer Register UART6 Transmit/Receive Mode Register UART6 Baud Rate Register UART6 Transmit Buffer Register UART6 Transmit/Receive Control Register 0 UART6 Transmit/Receive Control Register 1 UART6 Receive Buffer Register UART5, UART6 Transmit/Receive Control Register UART5, UART6 Input Pin Function Select Register
4. Special Function Registers (SFRs)
SFR Address Map (8/20)
Register UART5 Transmit/Receive Mode Register U5MR U5BRG U5TB U5C0 U5C1 U5RB U6MR U6BRG U6TB U6C0 U6C1 U6RB U56CON U56IS Symbol 00h XXh XXXXh 0000 1000b XXXX 0010b XXXXh 00h XXh XXXXh 0000 1000b XXXX 0010b XXXXh X000 0000b X000 X000b After Reset
RTP0R RTP1R RTP2R RTP3R
XXh XXh XXh XXh
C0SLOT0_0 C0SLOT0_1 C0SLOT0_2 C0SLOT0_3 C0SLOT0_4 C0SLOT0_5 C0SLOT0_6 C0SLOT0_7 C0SLOT0_8 C0SLOT0_9 C0SLOT0_10 C0SLOT0_11 C0SLOT0_12 C0SLOT0_13 C0SLOT0_14 C0SLOT0_15
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 2. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 34 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.9
Address 01F0h 01F1h 01F2h 01F3h 01F4h 01F5h 01F6h 01F7h 01F8h 01F9h 01FAh 01FBh 01FCh 01FDh 01FEh 01FFh 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh CAN0 Mode Register CAN0 Error Interrupt Mask Register CAN0 Error Interrupt Status Register CAN0 Error Source Register CAN0 Baud Rate Prescaler CAN0 Slot Interrupt Mask Register
4. Special Function Registers (SFRs)
SFR Address Map (9/20)
Register(2)(3) CAN0 Message Slot Buffer 1 Standard ID0 CAN0 Message Slot Buffer 1 Standard ID1 CAN0 Message Slot Buffer 1 Extended ID0 CAN0 Message Slot Buffer 1 Extended ID1 CAN0 Message Slot Buffer 1 Extended ID2 CAN0 Message Slot Buffer 1 Data Length Code CAN0 Message Slot Buffer 1 Data 0 CAN0 Message Slot Buffer 1 Data 1 CAN0 Message Slot Buffer 1 Data 2 CAN0 Message Slot Buffer 1 Data 3 CAN0 Message Slot Buffer 1 Data 4 CAN0 Message Slot Buffer 1 Data 5 CAN0 Message Slot Buffer 1 Data 6 CAN0 Message Slot Buffer 1 Data 7 CAN0 Message Slot Buffer 1 Time Stamp High-Order CAN0 Message Slot Buffer 1 Time Stamp Low-Order CAN0 Control Register 0 CAN0 Status Register CAN0 Extended ID Register CAN0 Configuration Register CAN0 Time Stamp Register CAN0 Transmit Error Count Register CAN0 Receive Error Count Register CAN0 Slot Interrupt Status Register Symbol C0SLOT1_0 C0SLOT1_1 C0SLOT1_2 C0SLOT1_3 C0SLOT1_4 C0SLOT1_5 C0SLOT1_6 C0SLOT1_7 C0SLOT1_8 C0SLOT1_9 C0SLOT1_10 C0SLOT1_11 C0SLOT1_12 C0SLOT1_13 C0SLOT1_14 C0SLOT1_15 C0CTLR0 C0STR C0IDR C0CONR C0TSR C0TEC C0REC C0SISTR XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XX01 0X01b(1) XXXX 0000b(1) 0000 0000b(1) X000 0X01b(1) 0000h(1) 0000 XXXXb(1) 0000 0000b(1) 0000h(1) 00h(1) 00h(1) 0000h(1) After Reset
C0SIMKR
0000h(1)
C0EIMKR C0EISTR C0EFR C0BRP C0MDR
XXXX X000b(1) XXXX X000b(1) 00h(1) 0000 0001b(1) XXXX XX00b(1)
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 2. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 3. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 35 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.10
Address 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh 0240h 0241h 0242h 0243h 0244h 0245h 0246h 0247h 0248h 0249h 024Ah to 024Fh CAN0 Acceptance Filter Support Register CAN0 Message Slot 0 Control Register / CAN0 Local Mask Register A Standard ID0 CAN0 Message Slot 1 Control Register / CAN0 Local Mask Register A Standard ID1 CAN0 Message Slot 2 Control Register / CAN0 Local Mask Register A Extended ID0 CAN0 Message Slot 3 Control Register / CAN0 Local Mask Register A Extended ID1 CAN0 Message Slot 4 Control Register / CAN0 Local Mask Register A Extended ID2 CAN0 Message Slot 5 Control Register CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register CAN0 Message Slot 8 Control Register / CAN0 Local Mask Register B Standard ID0 CAN0 Message Slot 9 Control Register / CAN0 Local Mask Register B Standard ID1 CAN0 Message Slot 10 Control Register / CAN0 Local Mask Register B Extended ID0 CAN0 Message Slot 11 Control Register / CAN0 Local Mask Register B Extended ID1 CAN0 Message Slot 12 Control Register / CAN0 Local Mask Register B Extended ID2 CAN0 Message Slot 13 Control Register CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register CAN0 Slot Buffer Select Register CAN0 Control Register 1 CAN0 Sleep Control Register CAN0 Global Mask Register Standard ID0 CAN0 Global Mask Register Standard ID1 CAN0 Global Mask Register Extended ID0 CAN0 Global Mask Register Extended ID1 CAN0 Global Mask Register Extended ID2 CAN0 Single Shot Status Register CAN0 Single Shot Control Register
4. Special Function Registers (SFRs)
SFR Address Map (10/20)
Register(3)(4) Symbol C0SSCTLR After Reset 0000h(1)(2)
C0SSSTR
0000h(1)(2)
C0GMR0 C0GMR1 C0GMR2 C0GMR3 C0GMR4
XXX0 0000b(1)(2) XX00 0000b(1)(2) XXXX 0000b(1)(2) 00h(1)(2) XX00 0000b(1)(2)
C0MCTL0 / C0LMAR0 C0MCTL1 / C0LMAR1 C0MCTL2 / C0LMAR2 C0MCTL3 / C0LMAR3 C0MCTL4 / C0LMAR4 C0MCTL5 C0MCTL6 C0MCTL7 C0MCTL8 / C0LMBR0 C0MCTL9 / C0LMBR1 C0MCTL10 / C0LMBR2 C0MCTL11 / C0LMBR3 C0MCTL12 / C0LMBR4 C0MCTL13 C0MCTL14 C0MCTL15 C0SBS C0CTLR1 C0SLPR
0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2) 0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2) 00h(2) X000 00XXb(2) XXXX XXX0b 0000 0000b(2) 0000 0001b(2)
C0AFS
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register can switch functions for addresses 0220h to 023Fh. 2. Values are obtained by setting the SLEEP bit in the C0SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 3. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 4. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 36 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.11
Address 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h 0261h 0262h 0263h 0264h 0265h 0266h 0267h 0268h 0269h 026Ah 026Bh 026Ch 026Dh 026Eh 026Fh 0270h 0271h 0272h 0273h 0274h 0275h 0276h 0277h 0278h 0279h 027Ah 027Bh 027Ch 027Dh 027Eh 027Fh CAN1 Message Slot Buffer 0 Standard ID0 CAN1 Message Slot Buffer 0 Standard ID1 CAN1 Message Slot Buffer 0 Extended ID0 CAN1 Message Slot Buffer 0 Extended ID1 CAN1 Message Slot Buffer 0 Extended ID2 CAN1 Message Slot Buffer 0 Data Length Code CAN1 Message Slot Buffer 0 Data 0 CAN1 Message Slot Buffer 0 Data 1 CAN1 Message Slot Buffer 0 Data 2 CAN1 Message Slot Buffer 0 Data 3 CAN1 Message Slot Buffer 0 Data 4 CAN1 Message Slot Buffer 0 Data 5 CAN1 Message Slot Buffer 0 Data 6 CAN1 Message Slot Buffer 0 Data 7 CAN1 Message Slot Buffer 0 Time Stamp High-Order CAN1 Message Slot Buffer 0 Time Stamp Low-Order CAN1 Message Slot Buffer 1 Standard ID0 CAN1 Message Slot Buffer 1 Standard ID1 CAN1 Message Slot Buffer 1 Extended ID0 CAN1 Message Slot Buffer 1 Extended ID1 CAN1 Message Slot Buffer 1 Extended ID2 CAN1 Message Slot Buffer 1 Data Length Code CAN1 Message Slot Buffer 1 Data 0 CAN1 Message Slot Buffer 1 Data 1 CAN1 Message Slot Buffer 1 Data 2 CAN1 Message Slot Buffer 1 Data 3 CAN1 Message Slot Buffer 1 Data 4 CAN1 Message Slot Buffer 1 Data 5 CAN1 Message Slot Buffer 1 Data 6 CAN1 Message Slot Buffer 1 Data 7 CAN1 Message Slot Buffer 1 Time Stamp High-Order CAN1 Message Slot Buffer 1 Time Stamp Low-Order CAN1 Acceptance Filter Support Register CAN1 Slot Buffer Select Register CAN1 Control Register 1 CAN1 Sleep Control Register
4. Special Function Registers (SFRs)
SFR Address Map (11/20)
Register(2)(3) Symbol C1SBS C1CTLR1 C1SLPR 00h(1) X000 00XXb(1) XXXX XXX0b(1) 0000 0000b(1) 0000 0001b(1) After Reset
C1AFS
C1SLOT0_0 C1SLOT0_1 C1SLOT0_2 C1SLOT0_3 C1SLOT0_4 C1SLOT0_5 C1SLOT0_6 C1SLOT0_7 C1SLOT0_8 C1SLOT0_9 C1SLOT0_10 C1SLOT0_11 C1SLOT0_12 C1SLOT0_13 C1SLOT0_14 C1SLOT0_15 C1SLOT1_0 C1SLOT1_1 C1SLOT1_2 C1SLOT1_3 C1SLOT1_4 C1SLOT1_5 C1SLOT1_6 C1SLOT1_7 C1SLOT1_8 C1SLOT1_9 C1SLOT1_10 C1SLOT1_11 C1SLOT1_12 C1SLOT1_13 C1SLOT1_14 C1SLOT1_15
XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 2. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 3. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 37 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.12
Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh CAN1 Global Mask Register Standard ID0 CAN1 Global Mask Register Standard ID1 CAN1 Global Mask Register Extended ID0 CAN1 Global Mask Register Extended ID1 CAN1 Global Mask Register Extended ID2 CAN1 Single Shot Status Register CAN1 Single Shot Control Register CAN1 Mode Register CAN1 Error Interrupt Mask Register CAN1 Error Interrupt Status Register CAN1 Error Source Register CAN1 Baud Rate Prescaler CAN1 Slot Interrupt Mask Register CAN1 Control Register 0 CAN1 Status Register CAN1 Extended ID Register CAN1 Configuration Register CAN1 Time Stamp Register CAN1 Transmit Error Count Register CAN1 Receive Error Count Register CAN1 Slot Interrupt Status Register
4. Special Function Registers (SFRs)
SFR Address Map (12/20)
Register(3)(4) Symbol C1CTLR0 C1STR C1IDR C1CONR C1TSR C1TEC C1REC C1SISTR After Reset XX01 0X01b(2) XXXX 0000b(2) 0000 0000b(2) X000 0X01b(2) 0000h(2) 0000 XXXXb(2) 0000 0000b(2) 0000h(2) 00h(2) 00h(2) 0000h(2)
C1SIMKR
0000h(2)
C1EIMKR C1EISTR C1EFR C1BRP C1MDR
XXXX X000b(2) XXXX X000b(2) 00h(2) 0000 0001b(2) XXXX XX00b(2)
C1SSCTLR
0000h(1)(2)
C1SSSTR
0000h(1)(2)
C1GMR0 C1GMR1 C1GMR2 C1GMR3 C1GMR4
XXX0 0000b(1)(2) XX00 0000b(1)(2) XXXX 0000b(1)(2) 00h(1)(2) XX00 0000b(1)(2)
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C0CTLR1 register can switch functions for addresses 02A0h to 02BFh. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 3. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 4. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 38 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.13
Address 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh
4. Special Function Registers (SFRs)
SFR Address Map (13/20)
Register(3)(4) Symbol C1MCTL0 / C1LMAR0 C1MCTL1 / C1LMAR1 C1MCTL2 / C1LMAR2 C1MCTL3 / C1LMAR3 C1MCTL4 / C1LMAR4 C1MCTL5 C1MCTL6 C1MCTL7 C1MCTL8 / C1LMBR0 C1MCTL9 / C1LMBR1 C1MCTL10 / C1LMBR2 C1MCTL11 / C1LMBR3 C1MCTL12 / C1LMBR4 C1MCTL13 C1MCTL14 C1MCTL15 After Reset 0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2) 0000 0000b(1)(2)/ XXX0 0000b(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 0000 0000b(1)(2)/ XXXX 0000b(1)(2) 00h(1)(2)/ 00h(1)(2) 0000 0000b(1)(2)/ XX00 0000b(1)(2) 00h(1)(2) 00h(1)(2) 00h(1)(2)
CAN1 Message Slot 0 Control Register / CAN1 Local Mask Register A Standard ID0 CAN1 Message Slot 1 Control Register / CAN1 Local Mask Register A Standard ID1 CAN1 Message Slot 2 Control Register / CAN1 Local Mask Register A Extended ID0 CAN1 Message Slot 3 Control Register / CAN1 Local Mask Register A Extended ID1 CAN1 Message Slot 4 Control Register / CAN1 Local Mask Register A Extended ID2 CAN1 Message Slot 5 Control Register CAN1 Message Slot 6 Control Register CAN1 Message Slot 7 Control Register CAN1 Message Slot 8 Control Register / CAN1 Local Mask Register B Standard ID0 CAN1 Message Slot 9 Control Register / CAN1 Local Mask Register B Standard ID1 CAN1 Message Slot 10 Control Register / CAN1 Local Mask Register B Extended ID0 CAN1 Message Slot 11 Control Register / CAN1 Local Mask Register B Extended ID1 CAN1 Message Slot 12 Control Register / CAN1 Local Mask Register B Extended ID2 CAN1 Message Slot 13 Control Register CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. The BANKSEL bit in the C1CTLR1 register can switch functions for addresses 02A0h to 02BFh. 2. Values are obtained by setting the SLEEP bit in the C1SLPR register to "1" (sleep mode exited) after reset and supplying a clock to the CAN module. 3. The CAN-associated registers (allocated in addresses 01E0h to 02BFh) cannot be used in M32C/87B. In M32C/87A, only CAN0-associated registers can be used. 4. Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 39 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.14
Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02CEh 02CFh 02D0h 02D1h 02D2h 02D3h 02D4h 02D5h 02D6h 02D7h 02D8h 02D9h 02DAh 02DBh 02DCh 02DDh 02DEh 02DFh 02E0h 02E1h 02E2h 02E3h 02E4h 02E5h 02E6h 02E7h 02E8h 02E9h 02EAh 02EBh 02ECh 02EDh 02EEh 02EFh UART1 Special Mode Register 4 UART1 Special Mode Register 3 UART1 Special Mode Register 2 UART1 Special Mode Register UART1 Transmit/Receive Mode Register UART1 Baud Rate Register UART1 Transmit Buffer Register UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register X0 Register, Y0 Register X1 Register, Y1 Register X2 Register, Y2 Register X3 Register, Y3 Register X4 Register, Y4 Register X5 Register, Y5 Register X6 Register, Y6 Register X7 Register, Y7 Register X8 Register, Y8 Register X9 Register, Y9 Register X10 Register, Y10 Register X11 Register, Y11 Register X12 Register, Y12 Register X13 Register, Y13 Register X14 Register, Y14 Register X15 Register, Y15 Register X/Y Control Register
4. Special Function Registers (SFRs)
SFR Address Map (14/20)
Register Symbol
X0R, Y0R XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh
After Reset
X1R, Y1R X2R, Y2R X3R, Y3R X4R, Y4R X5R, Y5R X6R, Y6R X7R, Y7R X8R, Y8R X9R, Y9R X10R, Y10R X11R, Y11R X12R, Y12R X13R, Y13R X14R, Y14R X15R, Y15R XYC
XXXX XX00b
U1SMR4 U1SMR3 U1SMR2 U1SMR U1MR U1BRG U1TB U1C0 U1C1 U1RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 40 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.15
Address 02F0h 02F1h 02F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh Timer B3 Mode Register Timer B4 Mode Register Timer B5 Mode Register External Interrupt Source Select Register 1(1) External Interrupt Source Select Register Timer B3 Register Timer B4 Register Timer B5 Register Timer A11 Register Timer A21 Register Timer A41 Register Three-Phase PWM Control Register 0 Three-Phase PWM Control Register 1 Three-Phase Output Buffer Register 0 Three-Phase Output Buffer Register 1 Dead Time Timer Timer B2 Interrupt Generation Frequency Set Counter UART4 Special Mode Register 4 UART4 Special Mode Register 3 UART4 Special Mode Register 2 UART4 Special Mode Register UART4 Transmit/Receive Mode Register UART4 Baud Rate Register UART4 Transmit Buffer Register UART4 Transmit/Receive Control Register 0 UART4 Transmit/Receive Control Register 1 UART4 Receive Buffer Register Timer B3, B4, B5 Count Start Register
4. Special Function Registers (SFRs)
SFR Address Map (15/20)
Register Symbol After Reset
U4SMR4 U4SMR3 U4SMR2 U4SMR U4MR U4BRG U4TB U4C0 U4C1 U4RB TBSR
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 000X XXXXb
TA11 TA21 TA41 INVC0 INVC1 IDB0 IDB1 DTT ICTB2
XXXXh XXXXh XXXXh 00h 00h XX11 1111b XX11 1111b XXh XXh
TB3 TB4 TB5
XXXXh XXXXh XXXXh
TB3MR TB4MR TB5MR IFSRA IFSR
00XX 0000b 00XX 0000b 00XX 0000b 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. The IFSRA register is included in the 144-pin package only.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 41 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.16
Address 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 044Ch 034Dh 034Eh 034Fh Timer A0 Register Timer A1 Register Timer A2 Register Timer A3 Register Timer A4 Register UART2 Special Mode Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit/Receive Mode Register UART2 Baud Rate Register UART2 Transmit Buffer Register UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register Count Start Register Clock Prescaler Reset Register One-Shot Start Register Trigger Select Register Up/Down Select Register UART3 Special Mode Register 4 UART3 Special Mode Register 3 UART3 Special Mode Register 2 UART3 Special Mode Register UART3 Transmit/Receive Mode Register UART3 Baud Rate Register UART3 Transmit Buffer Register UART3 Transmit/Receive Control Register 0 UART3 Transmit/Receive Control Register 1 UART3 Receive Buffer Register
4. Special Function Registers (SFRs)
SFR Address Map (16/20)
Register Symbol After Reset
U3SMR4 U3SMR3 U3SMR2 U3SMR U3MR U3BRG U3TB U3C0 U3C1 U3RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
U2SMR4 U2SMR3 U2SMR2 U2SMR U2MR U2BRG U2TB U2C0 U2C1 U2RB TABSR CPSRF ONSF TRGSR UDF
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh 00h 0XXX XXXXb 00h 00h 00h
TA0 TA1 TA2 TA3 TA4
XXXXh XXXXh XXXXh XXXXh XXXXh
X: Undefined Blank spaces are all reserved. No access is allowed.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 42 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.17
Address 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh DMA0 Request Source Select Register DMA1 Request Source Select Register DMA2 Request Source Select Register DMA3 Request Source Select Register CRC Data Register CRC Input Register IrDA Control Register UART0 Special Mode Register 4 UART0 Special Mode Register 3 UART0 Special Mode Register 2 UART0 Special Mode Register UART0 Transmit/Receive Mode Register UART0 Baud Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register Timer B0 Register Timer B1 Register Timer B2 Register Timer A0 Mode Register Timer A1 Mode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register Count Source Prescaler Register(1)
4. Special Function Registers (SFRs)
SFR Address Map (17/20)
Register TB0 TB1 TB2 TA0MR TA1MR TA2MR TA3MR TA4MR TB0MR TB1MR TB2MR TB2SC TCSPR Symbol After Reset XXXXh XXXXh XXXXh 00h 00h 00h 00h 00h 00XX 0000b 00XX 0000b 00XX 0000b XXXX XXX0b 0XXX 0000b
U0SMR4 U0SMR3 U0SMR2 U0SMR U0MR U0BRG U0TB U0C0 U0C1 U0RB
00h 00h 00h 00h 00h XXh XXXXh 0000 1000b 0000 0010b XXXXh
IRCON
X000 0000b
DM0SL DM1SL DM2SL DM3SL CRCD CRCIN
0X00 0000b 0X00 0000b 0X00 0000b 0X00 0000b XXXXh XXh
X: Undefined Blank spaces are all reserved. No access is allowed. NOTE: 1. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 43 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.18
Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh X: Undefined Blank spaces are all reserved. No access is allowed. D/A Control Register D/A Control Register 1 D/A Register 1 A/D0 Control Register 2 A/D0 Control Register 3 A/D0 Control Register 0 A/D0 Control Register 1 D/A Register 0 A/D0 Control Register 4 A/D0 Register 0 A/D0 Register 1 A/D0 Register 2 A/D0 Register 3 A/D0 Register 4 A/D0 Register 5 A/D0 Register 6 A/D0 Register 7
4. Special Function Registers (SFRs)
SFR Address Map (18/20)
Register AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 Symbol 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh 00XXh After Reset
AD0CON4 AD0CON2 AD0CON3 AD0CON0 AD0CON1 DA0 DA1 DACON DACON1
XXXX 00XXb XX0X X000b XXXX X000b 00h 00h XXh XXh XXXX XX00b XXXX 0000b
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 44 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.19
Address 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh Function Select Register B5(1) Function Select Register A6(1) Function Select Register A7(1) Function Select Register B6(1) Function Select Register B7(1) Port P6 Register Port P7 Register Port P6 Direction Register Port P7 Direction Register Port P8 Register Port P9 Register Port P8 Direction Register Port P9 Direction Register Port P10 Register Port P11 Register(1) Port P10 Direction Register Port P11 Direction Register(1)(2) Port P12 Register(1) Port P13 Register(1) Port P12 Direction Register(1)(2) Port P13 Direction Register(1)(2) Function Select Register C Function Select Register A0 Function Select Register A1 Function Select Register B0 Function Select Register B1 Function Select Register A2 Function Select Register A3 Function Select Register B2 Function Select Register B3 Function Select Register A4 Function Select Register A5(1) Function Select Register C6(1) Function Select Register E1 Function Select Register C2 Function Select Register C3 Function Select Register D1 Function Select Register D2 Function Select Register B9(1) Function Select Register E2 Function Select Register A8(1) Function Select Register A9(1)
4. Special Function Registers (SFRs)
SFR Address Map (19/20)
Register PS8 PS9 PSL9 PSE2 Symbol 00h XXX0 XX00b XXXX XX0Xb After Reset X000 0000b
PSD1 PSD2 PSC6 PSE1 PSC2 PSC3 PSC PS0 PS1 PSL0 PSL1 PS2 PS3 PSL2 PSL3 PS4 PS5 PSL5 PS6 PS7 PSL6 PSL7 P6 P7 PD6 PD7 P8 P9 PD8 PD9 P10 P11 PD10 PD11 P12 P13 PD12 PD13
00X0 XX00b XXXX XX0Xb XXXX 0X00b 00XX XX00b XXXX X00Xb X0XX XXXXb 00h 00h 00h 00h 00h 00X0 0000b 00h 00X0 0000b 00h 00h XXX0 0000b XXX0 0000b 00h 00h 00h 00h XXh XXh 00h 00h XXh XXh 00X0 0000b 00h XXh XXh 00h XXX0 0000b XXh XXh 00h 00h
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 4.20
Address 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh Port Control Register Pull-Up Control Register 0 Pull-Up Control Register 1 Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register Port P5 Register Port P4 Direction Register Port P5 Direction Register Pull-Up Control Register 2 Pull-Up Control Register 3 Pull-Up Control Register 4(1)(3) Port P14 Register(1) Port P15 Register(1) Port P14 Direction Register(1)(2) Port P15 Direction Register(1)(2)
4. Special Function Registers (SFRs)
SFR Address Map (20/20)
Register P14 P15 PD14 PD15 Symbol XXh XXh X000 0000b 00h After Reset
PUR2 PUR3 PUR4
00h 00h XXXX 0000b
P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 P5 PD4 PD5
XXh XXh 00h 00h XXh XXh 00h 00h XXh XXh 00h 00h
PUR0 PUR1
00h XXXX 0000b
PCR
XXXX X000b
X: Undefined Blank spaces are all reserved. No access is allowed. NOTES: 1. These registers cannot be used in the 100-pin package. 2. Set to FFh in the 100-pin package. 3. Set to 00h in the 100-pin package.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Reset
5.
Reset
Hardware reset 1, hardware reset 2 (Vdet3 detection function), software reset and watchdog timer reset are implemented to reset the MCU.
5.1
Hardware Reset 1
Pins, CPU, and SFRs are reset by using the RESET pin. When a low-level ("L") signal is applied to the RESET pin while the supply voltage meets the recommended operating conditions, ports and I/O pins for peripheral functions are reset. (Refer to Table 5.1 Pin states while RESET pin is held "L".) Also, the oscillation circuit is reset and the main clock starts oscillating. CPU and SFRs are reset when the signal applied to the RESET pin changes from "L" to high-level ("H") signal, and then the MCU executes a program beginning with the address indicated by the reset vector. The WDC5 bit in the WDC register and the internal RAM are not reset by hardware reset 1. When an "L" signal is applied to the RESET pin while writing data to the internal RAM, the value written to the internal RAM becomes undefined. Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin states while the RESET pin is held "L".
5.1.1
Reset at a Stable Supply Voltage
(1) Apply an "L" signal to the RESET pin. (2) Input 20 clock cycles or more into the XIN pin. (3) Apply an "H" signal to the RESET pin.
5.1.2
Power-on Reset
(1) Apply an "L" signal to the RESET pin. (2) Increase the supply voltage until it meets the recommended operating condition. (3) Wait for td(P-R) (internal power supply stabilization time) or more to allow the internal power supply to stabilize. (4) Inputs 20 clock cycles or more into the XIN pin. (5) Apply an "H" signal to the RESET pin.
Recommended operating voltage VCC1 VCC1 0V
RESET
RESET 0V
0.2VCC1 or below
0.2VCC1 or below Input td(P-R) + 20 clock cycles or more to the XIN pin
NOTE: 1. If operating at VCC1 > VCC2, VCC2 voltage must be lower than VCC1 voltage when powering up and down.
Figure 5.1
Example of Reset Circuit
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Reset
VCC1, VCC2 XIN
Td(P-R) ms or more is required 20 or more clock cycles are required
RESET
168 to 173 BCLK cycles (Flash Memory Version) 40 to 45 BCLK cycles (Mask ROM Version)
BCLK
Microprocessor mode BYTE = "H" Address A23 RD WR "H" "L" "H" "L" "H" "L"
FFFFFCh FFFFFDh FFFFFEh FFFFFFh
Content of reset vector
Microprocessor mode BYTE = "L" Address A23 RD WR "H" "L" "H" "L" "H" "L"
FFFFFCh FFFFFEh
Content of reset vector
Single-chip mode Address(1)
FFFFFCh
Content of reset vector
FFFFFEh NOTE: 1. Address data is not output from pins in single-chip mode.
Figure 5.2
Reset Sequence
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 5.1
Pin Name P0 P1 P2 to P4 P5_0 P5_1 P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 P6 to P15(1)
5. Reset
Pin States while RESET Pin is Held "L"(2)
Single-Chip Mode CNVSS = "L" Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Input port (high-impedance) Microprocessor Mode CNVSS = "H"(4) BYTE = "L" Data input (high-impedance) Data input (high-impedance) Address output (undefined) WR signal output ("H")(3) BHE signal output (undefined) RD signal output ("H")(3) BCLK output(3) HLDA signal output (output level depends on an input level to the HOLD pin)(3) HOLD signal input (high-impedance) "H" signal output(3) RDY signal input (high-impedance) Input port (high-impedance) Input port (high-impedance) BYTE = "H"
NOTES: 1. Ports P11 to P15 are provided in the 144-pin package only. 2. The availability of the pull-up resistors is undefined until the internal supply voltage stabilizes. 3. These pin states are defined after the power is turned on and the internal supply voltage stabilizes. Until then, the pin states are undefined. 4. EPM (P5_5) must be "H" in the flash memory version.
5.2
Hardware Reset 2 (Vdet3 detection function)
Pins, CPU, and SFRs are reset by the Vdet3 detection function, when the voltage applied to the VCC1 pin drops to Vdet3 (V) or below. The states of the pins, CPU, and SFRs after reset are the same as the hardware reset 1. Refer to 6. Power Supply Voltage Detection Function for details on Vdet3 detection function.
5.3
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU is reset), the MCU resets the CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector. Set the PM03 bit to 1 while the main clock is selected as the clock source for the CPU clock and the main clock oscillation is stable. The software reset does not reset the following SFRs; bits PM01 and PM00 in the PM0 register, the WDC5 bit in the WDC register, and the TCSPR register. Processor mode remains unchanged since bits PM01 and PM00 are not reset.
5.4
Watchdog Timer Reset
When the CM06 bit in the CM0 register is set to 1 (reset) and the watchdog timer underflows, the MCU resets the CPU, SFRs, ports, and I/O pins for peripheral functions. And then the MCU executes a program in an address indicated by the reset vector. The watchdog timer reset does not reset the following SFRs; bits PM01 and PM00 in the PM0 register, the WDC5 bit in the WDC register, and the TCSPR register. Processor mode remains unchanged since bits PM01 and PM00 are not reset.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
5. Reset
5.5
Internal Registers
Figure 5.3 shows CPU register states after reset. Refer to 4. Special Function Registers (SFRs) for SFR states after reset.
0: 0 after reset X: Undefined after reset
General registers
b15 b15 b8 b7 b0
High-speed interrupt registers
Flag register (FLG)
b0 b15 b23 b0
XXXXh XXXXXXh XXXXXXh
Flag save register (SVF) PC save register (SVP) Vector register (VCT)
X000XXXX00000000 IPL
b15
U I OBSZDC
b0
DMAC-associated registers
Data register (R0H/R0L) Data register (R1H/R1L) Data register (R2) Data register (R3) Address register (A0) Address register (A1) Static base register (SB) Frame base register (FB) User stack pointer (USP) Interrupt stack pointer (ISP) Interrupt table register (INTB) Program counter (PC)
b23 b15 b7 b0
00h R0H 00h R1H
b23
00h R0L 00h R1L
00h 00h XXXXh XXXXh XXXXh XXXXh XXXXXXh XXXXXXh XXXXXXh XXXXXXh XXXXXXh XXXXXXh
DMA mode register (DMD0) DMA mode register (DMD1) DMA transfer count register (DCT0) DMA transfer count register (DCT1) DMA transfer count reload register (DRC0) DMA transfer count reload register (DRC1) DMA memory address register (DMA0) DMA memory address register (DMA1) DMA memory address reload register (DRA0) DMA memory address reload register (DRA1) DMA SFR address register (DSA0) DMA SFR address register (DSA1)
0000h R2 0000h R3
000000h A0 000000h A1 000000h SB 000000h FB 000000h 000000h
000000h Contents of addresses FFFFFEh to FFFFFCh
Figure 5.3
CPU Register States after Reset
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
6.
Power Supply Voltage Detection Function
The power supply voltage detection function has the Vdet3 detection function, Vdet4 detection function, and cold start/warm start determination function. The Vdet3 detection function and Vdet4 detection function detect the changes in voltage and trigger the events. The cold start/warm start determination function determines whether the MCU is reset at power-on or reset while running. The power supply voltage detection function is available only with VCC1 = 4.2V to 5.5V standard. Figure 6.1 shows a block diagram of the voltage detection circuit. Figures 6.2 to 6.4 show registers associated with the voltage detection function.
Vdet3 detection function
Wait time to release hardware reset 2: td(S-R)
Q Internal reset signal (active "L")
1 shot
VCC1
+ Vdet3 VC26 CM10 E
T
Vdet4 detection function
+ Vdet3 E Analog Filter (rejection range: 200 ns) Vdet4 detection signal(1) DF1 to DF0 00b 01b 10b VC13
VC27
CPU clock
1/8
1/2
1/2
1/2
11b
Digital filter
D42 bit
Output one-shot pulse when the D42 bit becomes 0 to 1. Vdet4 detection interrupt signal Watchdog timer interrupt request
CM10 WAIT instruction (wait mode)
Latch
D41 D40
Oscillation stop detection interrupt signal Watchdog timer interrupt signal
Cold start/warm start determination function
Write a given value to the WDC register Hardware reset 1 at power-on WDC5 S R Q
COLD/WARM (Cold start, warm start)
CM10: bit in the CM1 register VC13: bit in the VCR1 register VC26, VC27: bits in the VCR2 register DF1 and DF0, D40, D41, D42: bits in the D4INT register WDC5: bit in the WDC register NOTE: 1. When the VC27 bit in the VCR2 register is set to 0 (Vdet4 detection function not used), the Vdet4 detection signal becomes "H".
Figure 6.1
Power Supply Voltage Detection Function Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
Voltage Detection Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0000
000
Symbol VCR1
Bit Symbol - (b2-b0) VC13 - (b7-b4) Bit Name Reserved bits
Address 001Bh
Function Set to 0 0: VCC1 < Vdet4 1: VCC1 Vdet4 Set to 0
After Reset 0000 1000b
RW RW
Voltage change monitor flag(1)
RO
Reserved bits
RW
NOTE: 1. The VC13 bit is enabled when the VC27 bit in the VCR2 register is set to 1 (Vdet4 detection function used). The VC13 bit becomes 1 when the VC27 bit is set to 0 (Vdet4 detection function not used).
Voltage Detection Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
000000
Symbol VCR2
Bit Symbol - (b5-b0) VC26 Bit Name Reserved bits Vdet3 detection function select bit(2, 4, 5) Vdet4 detection function select bit(3, 4)
Address 0017h
Function Set to 0 0: Vdet3 detection function not used 1: Vdet3 detection function used 0: Vdet4 detection function not used 1: Vdet4 detection function used
After Reset 00h
RW RW
RW
VC27
RW
NOTES: 1. Set the VCR2 register after the PRC3 bit in the PRCR register is set to 1 (write enable). 2. To use the hardware reset 2 (Vdet3 detection function), set the VC26 bit to 1. 3. To use the Vdet4 detection function, set the VC27 bit to 1 and the D40 bit in the D4INT register to 1 (Vdet4 detection interrupt used). The VC13 bit in the VCR1 register and the D42 bit in the D4INT register are enabled when the VC27 bit is set to 1. 4. After the VC26 or VC27 bit is set to 1, the detection circuit waits for td(E-A) to elapse before starting operation. 5. The VC26 bit is disabled when the MCU is in stop mode. (The hardware reset 2 is not performed even if the voltage applied to the VCC1 pin drops below Vdet3.)
Figure 6.2
VCR1 Register, VCR2 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
Vdet4 Detection Interrupt Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol D4INT
Bit Symbol D40 Bit Name Vdet4 detection interrupt enable bit(2)
Address 002Fh
Function 0: Vdet4 detection interrupt disabled 1: Vdet4 detection interrupt enabled
After Reset XX00 0000b
RW RW
D41
Wait mode/Stop mode exit control bit(3)
0: Vdet4 detection interrupt is not used to exit wait/stop mode 1: Vdet4 detection interrupt is used to exit wait/stop mode 0: Not detected 1: Voltage has crossed Vdet4 0: Not detected 1: Detected
b5 b4
RW
D42
Voltage change detect flag(4, 5)
RW
D43
WDT underflow detect flag (5)
RW
DF0 Sampling clock select bits DF1
0 0: CPU clock divided-by-8 0 1: CPU clock divided-by-16 1 0: CPU clock divided-by-32 1 1: CPU clock divided-by-64
RW
RW
- (b7-b6)
Unimplemented. Read as undefined value.
-
NOTES: 1. Set the D4INT register after the PRC3 bit in the PRCR register is set to 1 (write enable). 2. Use the following procedure to set the D40 bit to 1: (1) Set the VC27 bit in the VCR2 register to 1 (2) Wait for td(E-A) before the voltage detection circuit starts operating (3) Wait for required sampling time (See Table "Sampling Period") (4) Set the D40 bit to 1 3. If the Vdet4 detection interrupt has been used to exit wait mode or stop mode, set the D41 bit to 0 and then set it to 1 to use the Vdet4 detection interrupt again to exit these modes. 4. The D42 bit is enabled when the VC27 bit is set to 1 (Vdet4 detection function used ). The D42 bit becomes 0 when the VC27 bit is set to 0 (Vdet4 detection function not used). 5. The D43 bit can be set to 0 by a program. Writing a 1 has no effect.
Figure 6.3
D4INT Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol WDC
Bit Symbol - (b4-b0) WDC5 - (b6) WDC7 Bit Name
Address 000Fh
Function
After Reset 00XX XXXXb
RW RO
High-order bits of watchdog timer Cold start/warm start determine flag(1) Reserved bit 0: Cold start 1: Warm start Set to 0 0: Divide-by-16 1: Divide-by-128
RW
RW
Prescaler select bit
RW
NOTE: 1. The WDC5 bit is 0 after power-on. It can be set to 1 only by a program. The bit becomes 1 by writing either a 0 or 1. The bit remains a value set before reset, even after reset has been performed.
Figure 6.4
WDC Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
6.1
Vdet3 Detection Function
The hardware reset 2 is performed if the voltage applied to the VCC1 pin drops to Vdet3 (V) or below. Set the VC26 bit in the VCR2 register to 1 to use this Vdet3 detection function. When the hardware reset 2 occurs, ports and I/O pins for peripheral functions are reset. The CPU and SFRs are reset when td(S-R) elapses after the voltage applied to the VCC1 pin reaches Vdet3r (V) or above. Then, the MCU executes a program in an address indicated by the reset vector. The states of pins and SFRs after reset are the same as the hardware reset 1. Use the Vdet3 detection function while operating at or above Vdet3s. If the applied voltage drops below Vdet3s, perform the hardware reset 1 (refer to 5.1.2 Power-on Reset). The Vdet3 detection function cannot be used while the MCU is in stop mode. Figure 6.5 shows a Vdet3 detection function operation example.
5.0 V 3.1 V(1) 3.0 V(1)
5.0 V
Vdet3r VCC1 Vdet3 Vdet3s 2.0V(2) VSS
RESET VC26 bit in the VCR2 register Internal reset signal NOTES: 1. Typical value. 2. Minimum value.
"H" "L" 1 0 "H" "L" Wait time to release hardware reset 2: td(S-R) Undefined Set to 1 (Vdet3 detection function used) by a program
Figure 6.5
Vdet3 Detection Function Operation Example
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
6.2
Vdet4 Detection Function
Vdet4 detection interrupt is generated if the voltage applied to the VCC1 pin crosses the Vdet4 (V) level, either by dropping below or by rising above Vdet4. Set the VC27 bit in the VCR2 register to 1 (Vdet4 detection function used) and the D40 bit in the D4INT register to 1 (Vdet4 detection interrupt enabled) to use the Vdet4 detection function. The D42 bit becomes 1 (voltage has crossed Vdet4) as soon as the applied voltage crosses Vdet4. When the D42 bit changes from 0 to 1, a Vdet4 detection interrupt request is generated. The D42 bit does not become 0 automatically when the interrupt is acknowledged. Set it to 0 (not detected) by a program. Whether the voltage has dropped below Vdet4 or risen above Vdet4 can be determined by reading the VC13 bit in the VCR1 register. Set the D41 bit in the D4INT register to 1 to use the Vdet4 detection interrupt to exit wait mode or stop mode. The MCU exits wait mode or stop mode if the Vdet4 detection signal is generated even if the D42 bit is 1. The Vdet4 detection interrupt shares the same interrupt vector with watchdog timer interrupt and oscillation stop detection interrupt. When using the Vdet4 detection interrupt simultaneously with these interrupts, determine whether the Vdet4 detection interrupt is generated by reading the D42 bit in the interrupt routine. Table 6.1 shows conditions to generate Vdet4 detection interrupt request. Figure 6.6 shows a Vdet4 detection function operation example. Bits DF1 and DF0 in the D4INT register determine the sampling clock which is used to detects if the voltage applied to the VCC1 pin has crossed Vdet4. Table 6.2 shows the sampling periods. Table 6.1 Conditions to Generate Vdet4 Detection Interrupt Request
VC27 Bit 1 D40 Bit 1 D41 Bit 0 or 1 1 D42 Bit(1) 0 to 1 0 or 1 VC13 Bit(2) 0 to 1 1 to 0 0 to 1
Operating Mode CPU operating mode(3) Wait mode, Stop mode(4)
NOTES:
1. Set to 0 by a program before generating an interrupt. 2. An interrupt request is generated when the sampling period elapses after the value of the VC13 bit is changed. See Figure 6.6 Vdet4 Detection Function Operation Example for details. 3. CPU operating mode includes main clock mode, main clock direct mode, PLL mode, low speed mode, lowpower consumption mode, on-chip oscillator mode, on-chip oscillator low-power consumption mode. (Refer to 9. Clock Generation Circuits.) 4. Refer to 6.2.1 Usage Notes on Vdet4 Detection Interrupt.
Table 6.2
CPU Clock (MHz) 16 24
Sampling Periods
Sampling Clock (s) Divided-by-8 3.0 2.0 Divided-by-16 6.0 4.0 Divided-by-32 12.0 8.0 Divided-by-64 24.0 16.0
NOTE: 1. Set the CPU clock 24 MHz or lower to use the voltage detection function.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
Voltage applied to VCC1
Vdet4 (V) 3 (V)
Time RESET VC27 bit VC13 bit
"H" "L" 1 0 1 0 (note 1)

Sampling period
Output from digital filter D42 bit Vdet4 detection interrupt request signal from D42 bit
"H" "L" Set to 0 by a program 1 0 "H" "L" (note 2)

Sampling period
Output from digital filter D42 bit Vdet4 detection interrupt request signal from D42 bit D41 bit Vdet4 detection interrupt request signal when D41 bit is 1
"H" "L" 1 0 "H" "L" 1 0 "H" "L" (note 3)
Set to 0 by a program
VC27 bit: bit in the VCR2 register VC13 bit: bit in the VCR1 register VC41 bit, VC42 bit: bits in the D4INT register
Wait mode or stop mode
Wait mode or stop mode
NOTES: 1. Apply an "L" to the RESET pin when the voltage input to the VCC1 pin drops to 3.0 V or below. After the voltage rises above 3.0 V, and the output voltage from the main voltage regulator and the main clock oscillation stabilize, apply an "H" to the RESET pin. 2. When the D42 bit is set to 1, the Vdet4 detection interrupt request signal is not generated even if the Vdet4 detection signal is output from the digital filter. 3. If the Vdet4 detection interrupt has been used to exit wait mode or stop mode, set the D41 bit to 0 and then set it back to 1 to use the Vdet4 detection interrupt again to exit wait/stop mode.
Figure 6.6
Vdet4 Detection Function Operation Example
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
6. Power Supply Voltage Detection Function
6.2.1
Usage Notes on Vdet4 Detection Interrupt
When all the conditions below are met, the Vdet4 detection interrupt is generated and the MCU exits wait mode as soon as the WAIT instruction is executed or exits stop mode as soon as the CM10 bit in the CM1 register is set to 1 (all clocks stopped).
* * * *
the VC27 bit in the VCR2 register is set to 1 (Vdet4 detection function used) the D40 bit in the D4INT register is set to 1 (Vdet4 detection interrupt enabled) the D41 bit in the D4INT register is set to 1 (Vdet4 detection interrupt is used to exit wait/stop mode) the voltage applied to the VCC1 pin is Vdet4 or above (the VC13 bit in the VCR1 register is 1)
Execute the WAIT instruction or set the CM10 bit to 1 (all clocks stop) while the VC13 bit is 0 (VCC1 < Vdet4), if the MCU is configured to enter wait/stop mode when voltage applied to the VCC1 pin drops Vdet4 or below and to exit wait/stop mode when the voltage applied rises to Vdet4 or above. If the Vdet4 detection interrupt has been used to exit wait mode or stop mode, set the D41 bit to 0 and then set it back to 1 to use the Vdet4 detection interrupt again to exit wait/stop mode.
6.3
Cold Start/Warm Start Determination Function
The WDC5 bit in the WDC register determines whether it is a reset process when power-on (cold start) or a reset process when the RESET signal is input during MCU running (warm start). Default value of the WDC5 bit is 0 (cold start) when power-on, and the bit is set to 1 (warm start) by writing given values to the WDC register. The WDC5 bit does not become 0 even if the hardware reset 1, hardware reset 2, software reset, or watchdog timer reset is performed. Figure 6.7 shows an example of cold start/warm start determination function operation.
5V
VCC1
0V 5V
RESET
0V T1 1 T2
Pch transistor ON (Approx. 4 V) CPU comes out of reset Set to 1 by a program T > 100 s
WDC5 bit
0
Program starts running Reset sequence (Approx.20 s@16 MHz)
The WDC5 bit remains set to 1 even if voltage applied to RESET becomes 0 V.
NOTE: 1. If the time difference between T1 and T2 is greater, it may take longer to set the WDC5 bit to 1.
Figure 6.7
Cold Start/Warm Start Determination Function Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
7. Processor Mode
7.
7.1
Processor Mode
Processor Mode
Single-chip mode, memory expansion mode, microprocessor mode, or boot mode can be selected as the processor mode. Table 7.1 lists the features of the processor mode. Table 7.1 Processor Mode Features
Accessible Space SFR, internal RAM, internal ROM (user ROM area) Pins assigned to I/O Port Used as I/O ports or I/O pins for peripheral functions P0 to P5 become bus control pins P0 to P5 become bus control pins Used as I/O ports or I/O pins for peripheral functions
Processor Mode Single-chip mode
Memory expansion mode(1) SFR, internal RAM, internal ROM (user ROM area), external space Microprocessor mode(1) Boot mode(2) SFR, internal RAM, external space SFR, internal RAM, internal ROM (boot ROM area)
NOTES: 1. Refer to 8. Bus for details. 2. Refer to 26. Flash Memory for details.
7.2
Setting of Processor Mode
The CNVSS pin, EPM(P5_5) pin, and bits PM01 and PM00 in the PM0 register determine which processor mode to select. Table 7.2 lists processor mode after hardware reset. Table 7.3 lists the processor mode selected by bits PM01 and PM00. Table 7.2 Processor Mode after Hardware Reset
Input to EPM(P5_5) H or L H or L H L Memory Type Mask ROM version Flash memory version Mask ROM version Flash memory version Flash memory version Processor Mode Single-chip mode Microprocessor mode Microprocessor mode Boot mode
Input to CNVSS pin L H H H
Table 7.3
00b 01b 11b
PM01 and PM00 Bits Setting and Processor Mode
Processor Mode Single-chip mode Memory expansion mode Microprocessor mode
Bits PM01 and PM00
Rewriting bits PM01 and PM00 in the PM0 register places the MCU in the corresponding processor mode regardless of the CNVSS input level. When using memory expansion mode or microprocessor mode, first set bits PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the PM1 register. Then, set bits PM01 and PM00. Do not enter microprocessor mode while the CPU is executing the program in the internal ROM. Do not enter single-chip mode from microprocessor mode while the CPU is executing the program in an external space. The internal ROM cannot be accessed regardless of the PM01 and PM00 bits setting if the MCU starts up in microprocessor mode after reset. Figures 7.1 and 7.2 show the PM0 register and PM1 register. Figure 7.3 shows a memory map in each processor mode.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
7. Processor Mode
Processor Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol PM0
Address 0004h
After Reset 1000 0000b (CNVSS = "L") 0000 0011b (CNVSS = "H")
Function RW
Bit Symbol PM00
Bit Name
b1 b0
Processor mode bits(2, 3) PM01
0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Do not set to this value 1 1: Microprocessor mode 0: RD/BHE/WR 1: RD/WRH/WRL The MCU is reset when this bit is set to 1. Read as 0.
b5 b4
RW RW RW RW RW RW RW RW
PM02
R/W mode select bit
PM03
Software reset bit
PM04 Multiplexed bus space select bits(4) PM05 - (b6) PM07
0 0: Multiplexed bus is not used 0 1: Access the CS2 area using multiplexed bus 1 0: Access the CS1 area using multiplexed bus 1 1: Access all CS areas using multiplexed bus
Reserved bit
Set to 0 0: BCLK output (5) 1: No BCLK output
BCLK output function select bit
NOTES: 1. Set the PM0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. Bits PM01 and PM00 maintain values set before reset, even after software reset or watchdog timer reset has performed. 3. When using memory expansion mode or microprocessor mode, first set bits PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the PM1 register. Then, set bits PM01 and PM00. 4. The PM05 and PM04 bits setting is enabled in memory expansion mode and microprocessor mode. Set these bits in the combination with bits PM11 and PM10 in the PM 1 register. Do not set bits PM05 and PM04 to 11b in microprocessor mode since the MCU starts up with the separate bus after reset. Refer to the Table "Multiplexed Bus Settings and Chip-Select Areas" in the Bus chapter. 5. No BCLK is output in single-chip mode even if the PM07 bit is set to 0. To output BCLK from P5_3 in memory expansion mode and microprocessor mode, set the PM07 bit to 0, bits CM01 and CM00 in the CM0 register to "00b" (I/O port P5_3), and bits PM15 and PM14 in the PM1 register to 00b, 10b, or 11b.
Figure 7.1
PM0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
7. Processor Mode
Processor Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PM1
Bit Symbol Bit Name
Address 0005h
Function
b1 b0
After Reset 00h
RW
PM10 External space mode bits PM11
(2)
0 0: Mode 0 (A20 to A23 for P4_4 to P4_7) 0 1: Mode 1 (A20 for P4_4, CS2 to CS0 for P4_5 to P4_7) 1 0: Mode 2 (A20 and A21 for P4_4 and P4_5, CS1 and CS0 for P4_6 and P4_7) 1 1: Mode 3 (CS3 to CS0 for P4_4 to P4_7) 0: No wait state 1: 1 wait state 0: 1 wait state 1: 2 wait states(3)
b5 b4
RW
RW RW RW RW RW RW
PM12
Internal memory wait bit
PM13
SFR area wait bit
PM14 ALE pin select PM15 - (b7-b6) bits(2)
0 0: No ALE 0 1: P5_3(4) 1 0: P5_6 1 1: P5_4 Set to 0
Reserved bits
NOTES: 1. Set the PM1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. The PM11 and PM10 bits settings are enabled in memory expansion mode and microprocessor mode. Set bits PM01 and PM00 after setting bits PM15 and PM14, and bits PM11 and PM10. 3. Set the PM13 bit to 1 before accessing CAN-associated registers. 4. To output ALE signal from P5_3, set bits PM15 and PM14 to 01b, and bits CM01 and CM00 in the CM0 register to 00b (I/O port P5_3).
Figure 7.2
PM1 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
7. Processor Mode
Single-chip mode
000000h 000400h Mode 0 SFR Internal RAM Reserved 00F000h 010000h 100000h 200000h 300000h 400000h Not used External space 1 Block A(3) SFR Internal RAM Reserved Block A(3) External space 0
Memory expansion mode
Mode 1 SFR Internal RAM Reserved Block A(3) CS1 2-Mbyte external space 0(1) CS2 2-Mbyte external space 1 Mode 2 SFR Internal RAM Reserved Block A(3) Mode 3 SFR Internal RAM Reserved Block A(3) Not used CS1 4-Mbyte external space 0(2)
CS1 1-Mbyte external space 0 CS2 1-Mbyte external space 1
Not used External space 2 Not used Not used
C00000h D00000h E00000h F00000h FFFFFFh Internal ROM(4) Reserved Internal ROM(4) CS0 2-Mbyte external space 3 Not used Reserved Internal ROM(4) Reserved Internal ROM(4) CS0 3-Mbyte external space 3
CS3 1-Mbyte external space 2
External space 3
Not used
CS0 1-Mbyte external space 3
Reserved Internal ROM(4)
Microprocessor mode
000000h 000400h Mode 0 SFR Internal RAM Reserved 010000h 100000h CS area controlled by the EWCRi register (i = 0 to 3): CS0 controlled by EWCR3 CS1 controlled by EWCR0 CS2 controlled by EWCR1 CS3 controlled by EWCR2 NOTES: 1. 200000h to 010000h = 1984 Kbytes. 64K bytes less than 2 Mbytes. 2. 400000h to 010000h = 4032 Kbytes. 64K bytes less than 4 Mbytes. 3. Additional 4-Kbyte space provided in the flash memory version to store data. 4. In 1024-Kbyte ROM capacity version, internal ROM is allocated from address F00000h to FFFFFFh. 200000h 300000h 400000h Not used External space 2 Not used Not used External space 1 CS2 2-Mbyte external space 1 External space 0 CS1 2-Mbyte external space 0(1) Mode 1 SFR Internal RAM Reserved Mode 2 SFR Internal RAM Reserved Mode 3 SFR Internal RAM Reserved
Not used CS1 4-Mbyte external space 0(2) CS1 1-Mbyte external space 0 CS2 1-Mbyte external space 1
C00000h D00000h E00000h F00000h FFFFFFh External space 3 CS0 2-Mbyte external space 3 Not used CS0 4-Mbyte external space 3
CS3 1-Mbyte external space 2 Not used
CS0 1-Mbyte external space 3
Figure 7.3
Memory Map in Each Processor Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.
Bus
In memory expansion mode or microprocessor mode, the following pins become bus control pins: D0 to D15, A0 to A22, A23, CS0 to CS3, WRL/WR, WRH/BHE, RD, CLKOUT/BCLK/ALE, HLDA/ALE, HOLD, ALE, and RDY.
8.1
Bus Settings
Bus setting is determined by the BYTE pin, the DS register, bits PM05 and PM04 in the PM0 register, and bits PM11 and PM10 in the PM1 register. Table 8.1 lists bus settings. Figure 8.1 shows the DS register. Table 8.1 Bus Settings
Bus Setting Selecting external data bus width Setting bus width after reset Selecting separate bus or multiplexed bus Number of chip-select pins Pin & Registers Used for Setting DS register BYTE pin (for external space 3 only) Bits PM05 and PM04 in the PM0 register Bits PM11 and PM10 in the PM1 register
External Data Bus Width Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DS
Address 000Bh
After Reset XXXX 1000b (BYTE pin = "L") XXXX 0000b (BYTE pin = "H")
Function RW RW
Bit Symbol DS0
Bit Name External space 0 data bus width select bit External space 1 data bus width select bit External space 2 data bus width select bit External space 3 data bus width select bit Unimplemented. Write 0. Read as undefined value. 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide 0: 8 bits wide 1: 16 bits wide
DS1
RW
DS2
RW
DS3 - (b7-b4)
RW
-
Figure 8.1
DS Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.1.1
Selecting External Address Bus
The number of external address bus pins, the number of chip-select pins, and chip-select-assigned address space (CS area) vary in each external space mode. Bits PM11 and PM10 in the PM1 register select external space mode.
8.1.2
Selecting External Data Bus
The DS register selects either external 8-bit data bus or 16-bit data bus per each external space. The data bus in the external space 3 becomes 16 bits wide when a low-level ("L") signal is applied to the BYTE pin after reset, and 8 bits wide when a high-level ("H") signal is applied. Do not change the BYTE pin level while the MCU is operating. Internal bus is always 16 bits wide.
8.1.3
Selecting Separate Bus/Multiplexed Bus
Bits PM05 and PM04 in the PM0 register select either the separate bus or multiplexed bus. The MCU starts up with the separate bus after reset.
8.1.3.1
Separate Bus
With the separate bus format, the MCU performs data input/output and address output using individual buses. The DS register selects 8-bit or 16-bit external data bus for each external space. If all DSi bits in the DS register (i = 0 to 3) are set to 0 (8-bit data bus), port P0 functions as the data bus and port P1 as the programmable I/O port. If any of the DSi bits is set to 1 (16-bit data bus), ports P0 and P1 function as the data bus. Port P1 output is undefined when the MCU accesses the space where its DSi bit is set to 0.
8.1.3.2
Multiplexed Bus
With the multiplexed bus format, the MCU performs data input/output and address output using the same bus by time-sharing. D0 to D7 are time-multiplexed with A0 to A7 in the space accessed by the 8-bit data bus. D0 to D15 are time-multiplexed with A0 to A15 in the space accessed by the 16-bit data bus. When bits PM05 and PM04 in the PM0 register are set to 11b (access all CS area using multiplexed bus), address bus has only 16 bits using A0 to A15. In this case, the accessible space is 64 Kbytes per each chip-select output. Refer to Table 8.3 Processor Mode and Pin Function for details. Table 8.2 lists multiplexed bus settings and chip-select areas. Table 8.2 Multiplexed Bus Settings and Chip-Select Areas
PM11 and PM10 Bits Setting PM05 and PM04 bits setting 00b (multiplexed bus not used) 01b (access the CS2 area using multiplexed bus) 10b (access the CS1 area using multiplexed bus) 11b (access the all CS areas using multiplexed bus)(1) Do not set to these values CS2 00b (external space mode 0 01b (external space mode 1) 10b (external space mode 2) 11b (external space mode 3)
Separate bus Do not set to this value CS1 CS2
CS1
CS1
CS0 CS1 CS2
CS0 CS1
CS0 CS1 CS2 CS3
NOTE: 1. In microprocessor mode, do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using multiplexed bus).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 8.3
Processor Mode PM05 and PM04 bits setting(1) Data bus width
8. Bus
Processor Mode and Pin Function
Single-chip Mode Memory Expansion Mode/Microprocessor Mode 00b (Multiplexed bus not used) 01b (Access CS2 area using multiplexed bus) 10b (Access CS1 area using multiplexed bus) Access all external spaces with 8-bit data bus Access any external spaces with 16-bit data bus Data bus (D8 to D15) Memory Expansion Mode 11b (Access all CS areas using multiplexed bus) Access all external spaces with 8-bit data bus I/O port Access any external spaces with 16-bit data bus
Access all external spaces with 8-bit data bus
Access any external spaces with 16-bit data bus Data bus (D8 to D15)
P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_3 P4_4 to P4_6 P4_7 P5_0 to P5_2 P5_3 P5_4 P5_5 P5_6 P5_7 I/O port/ CLKOUT I/O port
Data bus (D0 to D7) I/O port I/O port
Address bus (A0 to A7) Address bus (A8 to A15) Address Bus (A16 to A19)
Address bus/data bus (A0/D0 to A7/D7)(2) Address bus/ Address bus (A8 to A15) data bus (A8/D8 to A15/D15)(2) I/O port Address bus/ data bus (A8/D8 to A15/D15)(2)
I/O port
CS or address bus (A20 to A22) (Refer to 8.2 Bus Control for details)(6) CS or address bus (A23) (Refer to 8.2 Bus Control for details)(6) RD, WRL, WRH outputs or RD, BHE, WR outputs (Refer to 8.2 Bus Control for details)(4) CLKOUT/BCLK/ALE(7) HLDA/ALE(3) HOLD ALE(3)(5) RDY
NOTES: 1. Do not set bits PM05 and PM04 in the PM0 register to 11b (access all CS areas using multiplexed bus) in microprocessor mode since the MCU starts up with the separate bus after reset. When bits PM05 and PM04 are set to 11b in memory expansion mode, the accessible space is 64-Kbyte per each chip-select output. 2. These pins are used as address bus when selecting separate bus. 3. Bits PM15 and PM14 in the PM1 register determine which pin is used to output the ALE signal. 4. The PM02 bit in the PM0 register selects either combination, "RD, WRL, WRH" or "RD, BHE, WR". 5. P5_6 outputs undefined value when bits PM15 and PM14 are set to 00b (no ALE). In this case, it cannot be used as an I/O port. 6. Bits PM11 and PM10 in the PM1 register determine whether these pins are used as chip-select outputs or address bus. 7. Use bits CM01 and CM00 in the CM0 register, bits PM15 and PM14 in the PM1 register, and the PM07 bit in the PM0 register to select among CLKOUT, BCLK, and ALE function.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.2
Bus Control
Described below are the signals required to access external devices and the bus timing. The signals are available in memory expansion mode and microprocessor mode only.
8.2.1
Address Bus and Data Bus
Address bus is the signals to access 16-Mbyte space, and consists of 24 control pins; A0 to A22 and A23. A23 is an inverse output signal of the highest-order address bit. Data bus is the signals for data input and output. The DS register selects either an 8-bit data bus width from D0 to D7 or a 16-bit data bus width from D0 to D15 for each external space. When a high-level ("H") signal is applied to the BYTE pin, the data bus accessing the external space 3 is 8 bits wide after reset. When a low-level ("L") signal is applied to the BYTE pin, the data bus accessing the external space 3 is 16 bits wide. When changing single-chip mode to memory expansion mode, the address bus value is undefined until the MCU accesses an external space.
8.2.2
Chip-Select Output
Chip-select outputs share pins with address bus, A20 to A22 and A23. Bits PM11 and PM10 in the PM1 register determine the CS areas to be accessed and the number of chip-select outputs. Maximum of four chip-select outputs are provided. In microprocessor mode, no chip-select signal is output after reset. Only A23, however, can perform as a chipselect output. The CSi pin (i = 0 to 3) outputs an "L" signal while accessing its corresponding external space. An "H" signal is output while the MCU is accessing other external spaces. Figure 8.2 shows an example of address bus and chipselect outputs (separate bus).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
Example 1: After accessing the external space, both address bus and chip-select output change
When the MCU accesses the external space j specified by another chip-select output in the next cycle after having accessed the external space i, both address bus and chip-select output change.
Access Access another external external space j space i
Example 2: After accessing an external space, the chip-select output changes but the address bus does not.
When the MCU accesses SFR or internal ROM/ RAM area in the next cycle after having accessed an external space, the chip-select signal changes but the address bus does not.
Access external space Access SFR, internal ROM/ RAM
Data bus Address bus Chip-select: CSk Chip-select: CSp
Data Address
Data
Data bus Address bus Chip-select: CSk
Data Address
Example 3: After accessing the external space, the address bus changes but the chip-select output does not.
When the MCU accesses the space i specified by the same chip-select output in the next cycle after having accessed the external space i, the address bus changes but the chip-select output does not.
Access Access the same external external space i space i
Example 4: After accessing an external space, neither address bus nor chip-select signal changes.
When the MCU does not access any spaces in the next cycle after having accessed an external space (no instruction prefetch is performed), neither address bus nor chip-select signal changes.
Access external space No accesss to external space
Data bus Address bus Chip-select: CSk
Data Address
Data
Data bus Address bus Chip-select: CSk
Data Address
i = 0 to 3 j = 0 to 3, excluding i k = 0 to 3 p = 0 to 3, excluding k
NOTE: 1. The above examples show the address bus and chip-select output in two consecutive bus cycles. Depending on the combination, the chip-select signal can be more than two bus cycles.
CS1 outputs an "L" signal while accessing the external space 0. CS2 outputs an "L" signal while accessing the external space 1. CS3 outputs an "L" signal while accessing the external space 2. CS0 outputs an "L" signal while accessing the external space 3.
Figure 8.2
Address Bus and Chip-Select Outputs (Separate Bus)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.2.3
Read/Write Output Signals
When using a 16-bit data bus, the PM02 bit in the PM0 register selects either a combination of the "RD, WR, and BHE" outputs or the "RD, WRL, and WRH" outputs to determine the read/write output signals. When bits DS3 to DS0 in the DS register are set to 0 (8-bit external data bus width), set the PM02 bit to 0 (RD/WR/BHE). When any of bits DS3 to DS0 is set to 1 (16-bit external data bus width) to access an 8-bit space, the combination of "RD, WR, and BHE" is automatically selected regardless of the PM02 bit setting. Table 8.4 lists RD, WRL, and WRH outputs. Table 8.5 list RD, WR, and BHE outputs. The RD, WR, and BHE outputs are selected for the read/write output signals after reset. When changing to "RD, WRL, and WRH" outputs, set the PM02 bit first to write data to an external memory. Table 8.4
Data Bus Width 16 bits
RD, WRL, and WRH Outputs
RD L H H H WRL H L H L L(1) H(1) WRH H H L L Not used Not used A0 Not used Not used Not used Not used H/L H/L CPU Processing on External Space Read data Write 1-byte data to even address Write 1-byte data to odd address Write data to both even and odd addresses Write 1-byte data Read 1-byte data
8 bits
H L
NOTE: 1. These become WR output.
Table 8.5
Data Bus Width 16 bits
RD, WR, and BHE Outputs
RD H L H L H L WR L H L H L H L H BHE L L H H L L Not used Not used A0 H H L L L L H/L H/L CPU Processing on External Space Write 1-byte data to odd address Read 1-byte data from odd address Write 1-byte data to even address Read 1-byte data from even address Write data to both even and odd addresses Read data from both even and odd addresses Write 1-byte data Read 1-byte data
8 bits
H L
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.2.4
Bus Timing
Software wait states for the internal ROM and internal RAM can be set using the PM12 bit in the PM1 register, for the SFR area using the PM13 bit, and for external spaces using the EWCRi register (i = 0 to 3). Table 8.6 lists a software wait state and bus cycle. The basic bus cycle for the internal ROM, internal RAM, and SFR area is one bus clock (BCLK) cycle. A read from the internal ROM takes the basic bus cycle. A read or write to the internal RAM takes the basic bus cycle. When the PM12 bit in the PM1 register to 1 (1 wait state), an access to the internal ROM or internal RAM takes two BCLK cycles. A read or write to the SFR area takes two BCLK cycles (1 wait state). When the PM13 bit in the PM1 register is set to 1 (2 wait states), an access takes three BCLK cycles. The external bus cycle is divided into two phases: the number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L" (first ), and the number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H" (second ). The minimum read or write cycle for the external bus is two BCLK cycles (1 + 1 ). The EWCRi register (i = 0 to 3) selects an external bus cycle from 12 types for the separate bus and seven types for the multiplexed bus. For example, when bits EWCRi4 to EWCRi0 in the EWCRi register are set to 00011b (1 + 3 ), the external bus cycle is four BCLK cycles. Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show external bus timings.
External Space Wait Control Register i (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol EWCR0 to EWCR3
Bit Symbol EWCRi0 Bit Name
Address 0048h, 0049h, 004Ah, 004Bh
Function
After Reset X0X0 0011b
RW RW
EWCRi1
EWCRi2
Bus cycle select bits (3)
EWCRi3
EWCRi4 - (b5) Unimplemented. Write 0. Read as undefined value. Recovery cycle insert select bit Unimplemented. Write 0. Read as undefined value.
0 0 0 0 1: 1 + 1 0 0 0 1 0: 1 + 2 0 0 0 1 1: 1 + 3 0 0 1 0 0: 1 + 4 0 0 1 0 1: 1 + 5 0 0 1 1 0: 1 + 6 0 1 0 1 0: 2 + 2 0 1 0 1 1: 2 + 3 0 1 1 0 0: 2 + 4 0 1 1 0 1: 2 + 5 1 0 0 1 1: 3 + 3 1 0 1 0 0: 3 + 4 1 0 1 0 1: 3 + 5 1 0 1 1 0: 3 + 6 Do not set to values other than the above
b4 b3 b2 b1 b0 (1)
(2)
RW
RW
RW
RW
- 0: Insert no recovery cycle when accessing external space i 1: Insert a recovery cycle when accessing external space i
EWCRi6
RW
- (b7)
-
NOTES: 1. The number of BCLK cycles in the period from the beginning of the bus access until the read or write output signal becomes "L". 2. The number of BCLK cycles in the period from the read or write output signal becomes "L" until the signal changes to "H".
Figure 8.3
EWCR0 to EWCR3 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 8.6
Space
8. Bus
Software Wait State and Bus Cycle
PM1 Register External Bus Status PM13 Bit(1) PM12 Bit - 0 1 0 1 - EWCRi Register (i=0 to 3) Bits EWCRi4 to EWCRi0 - - 00001b 00010b 00011b 00100b 00101b Separate bus - - 00110b 01010b 01011b 01100b 10011b 10100b 10110b 01010b 01011b 01101b Multiplexed bus - - 10011b 10100b 10101b 10110b Bus Cycle 2 BCLK cycles 3 BCLK cycles 1 BCLK cycle 2 BCLK cycles 2 BCLK cycles 3 BCLK cycles 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 7 BCLK cycles 4 BCLK cycles 5 BCLK cycles 6 BCLK cycles 6 BCLK cycles 7 BCLK cycles 9 BCLK cycles 4 BCLK cycles 5 BCLK cycles 7 BCLK cycles 6 BCLK cycles 7 BCLK cycles 8 BCLK cycles 9 BCLK cycles
SFR area Internal ROM/ RAM
- -
External memory
NOTE: 1. Set the PM13 bit to 1 before accessing CAN-associated registers.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
* Bus cycle 1 + 1
1 bus cycle = 2 BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
* Bus cycle 1 + 2
1 bus cycle = 3 BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
* Bus cycle 1 + 3
1 bus cycle = 4 BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
* Bus cycle 1 + 4
1 bus cycle = 5 BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
* Bus cycle 1 + 5
1 bus cycle = 6 BCLK Address CSi Read data RD Write data WR, WRL, WRH
* Bus cycle 1 + 6
1 bus cycle = 7 BCLK Address (Note 1) CSi Read data RD Write data WR, WRL, WRH (Note 1)
i = 0 to 3
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.4
Bus Cycles when Separate Bus is Selected (1/3)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
* Bus cycle 2 + 2
1 bus cycle = 4
* Bus cycle 2 + 3
1 bus cycle = 5 BCLK Address (Note 1) CSi Read data RD Write data WR, WRL, WRH (Note 1)
BCLK Address CSi Read data RD Write data WR, WRL, WRH
* Bus cycle 2 + 4
1 bus cycle = 6 BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
i = 0 to 3 NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.5
Bus Cycles when Separate Bus is Selected (2/3)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
* Bus cycle 3 + 3
1 bus cycle = 6
BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
* Bus cycle 3 + 4
1 bus cycle = 7
BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
* Bus cycle 3 + 6
1 bus cycle = 9
BCLK Address CSi Read data RD Write data WR, WRL, WRH (Note 1)
i = 0 to 3 NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.6
Bus Cycle with Separate Bus is Selected (3/3)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
* Bus cycle 2 + 2
1 bus cycle = 4 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
* Bus cycle 2 + 3
1 bus cycle = 5 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
* Bus cycle 2 + 5
1 bus cycle = 7 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
* Bus cycle 3 + 3
1 bus cycle = 6 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
LA: Latch address i=0 to 3
RD: Read data
WD: Write data
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.7
Bus Cycles when Multiplexed Bus is Selected (1/2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
* Bus cycle 3 + 4
1 bus cycle = 7 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
* Bus cycle 3 + 5
1 bus cycle = 8 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
* Bus cycle 3 + 6
1 bus cycle = 9 BCLK CSi Read data RD Write data WR (WRL) ALE LA WD LA RD (Note 1)
LA: Latch address i = 0 to 3
RD: Read data
WD: Write data
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.8
Bus Cycles when Multiplexed Bus is Selected (2/2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.2.4.1
Bus Cycle with Recovery Cycle Inserted
The EWCRi6 bit in the EWCRi register (i = 0 to 3) determines whether the recovery cycle is inserted or not. Address output or data output is held during the recovery cycle (only when using the separate bus). Devices, which require longer address hold time or data hold time, are connectable.
- Recovery cycle when separate bus is selected (bus cycle is 1 + 2 )
Recovery cycle BCLK Address CSi Read data RD Write data WR, WRL, WRH WD Data is held RD A Address is held (Note 1)
- Recovery cycle when multiplexed bus is selected (bus cycle is 2 + 3 )
Recovery cycle BCLK CSi Read data RD Write data WR (WRL) ALE LA WD Data is held LA RD (Note 1)
A: address i = 0 to 3
LA: Latch address
RD: Read data
WD: Write data
NOTE: 1. When the MCU accesses the same CS area consecutively, the CSi pin keeps outputting "L".
Figure 8.9
Recovery Cycle
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.2.5
ALE Output
The ALE output signal is provided for the external devices to latch the address when using the multiplexed bus. Latch the address at the falling edge of the ALE output. Bits PM15 and PM14 in the PM1 register determine to what pin the ALE output is assigned. The ALE signal is output even when accessing the internal space.
(1) 8-bit data bus
ALE A0/D0 to A7/D7 A8 to A15 A16 to A19 A20/CS3 A21/CS2 A22/CS1 A23/CS0
(2) 16-bit data bus
ALE
Address Address
Data(1)
A0/D0 to A15/D15
Address
Data(1)
Address(2) Address or CS
A16 to A19 A20/CS3 A21/CS2 A22/CS1 A23/CS0
Address(2) Address or CS
NOTES: 1. A0/D0 to A15/D15 are placed in high-impedance states when read. 2. When the multiplexed bus is selected for all CS areas, A16 to A19 become I/O ports.
Figure 8.10
ALE Output and Address/Data Bus
8.2.6
RDY Input
The RDY signal facilitates access to external devices requiring longer access time. When RDY input is "L" at the falling edge of the last BCLK cycle, wait states are inserted into the bus cycle. Then, when an "H" signal is input to the RDY pin at the falling edge of BCLK, the MCU resumes executing the remaining bus clock. Table 8.7 lists MCU states when placed in wait state by RDY input. Figure 8.11 shows an example of the RD signal that is extended by the RDY signal. Table 8.7 MCU States while "L" is Input to the RDY Pin
Item Clock generation circuits RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, ALE, HLDA, programmable I/O ports Internal peripheral circuits Operating (oscillating) Maintains the same state as when "L" is input to RDY pin. Operating State
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
- Separate bus (bus cycle is 1 + 2 )
BCLK
- Multiplexed bus (bus cycle is 2 + 2 )
BCLK
CSi(1)
CSi(1)
RD
RD
RDY tsu(RDY-BCLK)
RDY tsu(RDY-BCLK)
Timing to input RDY signal i = 0 to 3 : Wait states inserted by RDY input tsu(RDY-BCLK): RDY input setup time
Timing to input RDY signal
NOTE: 1. Chip-select output (CSi) may be extended depending on the CPU state such as the instruction queue buffer.
Figure 8.11
RD Output Signal Extended by RDY Input
8.2.7
HOLD Input
The HOLD input signal is used to transfer ownership of the bus from the CPU to external devices. When a lowlevel ("L") signal is applied to the HOLD pin, the MCU enters a hold state after the bus access in progress is completed. While the HOLD pin is held "L", the MCU remains in a hold state and the HLDA pin outputs an "L" signal. Table 8.8 lists the MCU states in hold state. Bus is used in the following priority order: HOLD, DMAC, CPU. Table 8.8 MCU States in Hold State
Item Clock generation circuits CPU Internal peripheral circuits RD, WR, A0 to A22, A23, D0 to D15, CS0 to CS3, BHE HLDA ALE Programmable I/O ports Operating (oscillating) Stopped Operating (Watchdog timer is stopped)(1) High-impedance Outputs "L" Outputs "L" Maintains the same state as when "L" is input to HOLD pin. State
NOTE: 1. When the PM22 bit in the PM2 register is set to 1 (selects the on-chip oscillator clock as count source for the watchdog timer), watchdog timer does not stop.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
8. Bus
8.2.8
External Bus States when Accessing Internal Space
Table 8.9 lists external bus states when the internal space is accessed. Table 8.9
A0 to A22, A23 D0 to D15 RD, WR, WRL, WRH BHE CS ALE
External Bus States when Accessing Internal Space
Item State when Accessing SFR, Internal ROM, and Internal RAM Hold the last accessed address in the external space High-impedance Outputs "H" Holds the output level at the time when the MCU accessed the external space or SFR area for the last time Outputs "H" Outputs ALE signal
8.2.9
BCLK Output
The bus clock can be output from the BCLK pin in memory expansion mode and microprocessor mode. To output the bus clock, set the PM07 bit in the PM0 register to 0 (BCLK output) and bits CM01 and CM00 in the CM0 register to 00b (I/O port P5_3). No BCLK is output in single-chip mode. Refer to 9. Clock Generation Circuits for details.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
9.
9.1
Clock Generation Circuits
Types of the Clock Generation Circuit
The MCU has four on-chip clock generation circuits to generate system clock signals. * Main clock oscillation circuit * Sub clock oscillation circuit * On-chip oscillator * PLL frequency synthesizer Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 shows a block diagram of the clock generation circuit. Figures 9.2 to 9.8 show clock-associated registers. Table 9.1
Item Applications
Clock Generation Circuit Specifications
Main Clock Oscillation Circuit * CPU clock source * Peripheral function clock source Up to 32 MHz * Ceramic resonator * Crystal oscillator XIN, XOUT Sub Clock Oscillation Circuit * CPU clock source * Count source for timer A and timer B 32.768 kHz Crystal oscillator On-chip Oscillator * CPU clock source * Peripheral function clock source Approx. 1 MHz - PLL Frequency Synthesizer * CPU clock source * Peripheral function clock source Up to 32 MHz (see Table 9.3) -
Clock frequency Connectable oscillator or resonator Oscillator or resonator connect pins Oscillation stop/ restart function Oscillator state after reset Other
XCIN, XCOUT
-
-
Available Oscillating Externally generated clock can be used.
Available Stopped Externally generated clock can be used.
Available Stopped
Available Stopped
Oscillation stop detect 30 MHz or 20 MHz: function: Input 10 MHz to the When the main clock main clock stops, the on-chip 32 MHz or 21.3 MHz oscillator starts Input 8 MHz to the oscillating main clock automatically and becomes the CPU and peripheral function clock source
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
PM21 Interrupt priority level decision output Vdet4 detection interrupt signal NMI RESET S WAIT instruction Logic 1 write signal to CM10 bit
CM10 SQ R
Stop mode
RQ
CM02
Clock stop signal in wait mode
Main clock oscillation circuit
XIN XOUT fXIND CM05 Stop mode PM26 Clock stop signal in wait mode PM22 PM26 PM27 CM21 Stop mode Main clock
0 1
Software reset Watchdog timer reset Hardware reset 2 CM05 CM21 Stop mode fCAN CM17 CM21 Clock stop signal in wait mode Peripheral function clock source: fPFC Reset the divider (divideby-8 mode) 1 Divider 0 (divide-by-m) 0 1 (3) MCD register(2) CM07 PM24 fAD f1 f8 1/8
00 01
0 1
PLL frequency synthesizer fPLL On-chip oscillator fROC
CPU clock (bus clock) fCPU
Enable oscillation Clock stop signal in wait mode 1/4 CST
f32 f2n(1)
Sub clock oscillation circuit
XCIN XCOUT
VC27
fXIND 1/2n fROC 10 PM27 and PM26 1/32 CPSR=1 fC32
fC CM04
Reset the divider
Oscillation stop detection circuit
Main clock
Clock edge detect/ charge and discharge circuit control Charge and discharge circuit Oscillation stop detection interrupt request generation circuit Watchdog timer interrupt request signal Vdet4 detection interrupt request signal
Oscillation stop detection interrupt request (non-maskable interrupt requst)
CM21
PLL frequency synthesizer
VCO clock (fVCO)
Programmable counter Reference frequency counter 1/2 1/3
Phase comparator
Loop filter
Main clock
Voltage controlled oscillator (VCO)
PLL clock (fPLL) PLC12 PLC12: bit in the PLC1 register
VC27: bit in the VCR2 register CM02, CM04, CM05, and CM07: bits in the CM0 register CM10 and CM17: bits in the CM1 register CM21: bit in the CM2 regsiter PM21, PM22, PM24, PM26, and PM27: bits in the PM2 register CST: bit in the TCSPR register CPSR: bit in the CPSRF register NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Bits MCD4 to MCD0 in the MCD register select the dividing ratio (divide-by-m mode: m = 1, 2, 3, 4, 6, 8, 10, 12, 14, 16). 3. To use the XIN clock as the CAN clock, set the PM24 bit to 1 when accessing the CAN module.
Figure 9.1
Clock Generation Circuit
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0
Bit Symbol CM00 Bit Name
Address 0006h
Function
b1 b0
After Reset 0000 1000b
RW RW
Clock output function select bits (2) CM01 Peripheral function clock stop in wait mode bit(9) XCIN-XCOUT drive capability select bit(10) Port XC switch bit Main clock (XIN-XOUT) stop bit(5, 9) Watchdog timer function select bit
0 0: I/O port P5_3(2) 0 1: Outputs fC 1 0: Outputs f8 1 1: Outputs f32 0: Peripheral clocks do not stop in wait mode 1: Peripheral clocks stop in wait mode (3) 0: Low 1: High 0: I/O port function 1: XCIN-XCOUT oscillation function (4) 0: Main clock oscillates 1: Main clock stops (6) 0: Watchdog timer interrupt 1: Reset(7) 0: Clock selected by the CM21 bit divided by the MCD register 1: Sub clock
RW
CM02
RW
CM03
RW
CM04
RW
CM05
RW
CM06
RW
CM07
CPU clock select bit 0 (8, 9)
RW
NOTES: 1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. The BCLK, ALE, or "L" signal is output from the P5_3 in memory expansion mode or microprocessor mode. Port P5_3 does not function as an I/O port. 3. fC32 does not stop running. 4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the PU25 bit in the PUR2 register to 0 (not pulled up). 5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21 bit in the CM2 register to 1 (on-chip oscillator clock). When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled up to the XOUT pin via the feedback resistor. 6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1. 7. Once the CM06 bit is set to 1, it cannot be set to 0 by a program. 8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes. Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes. Do not change the CM07 bit simultaneously with the CM04 or CM05 bit. 9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect. 10. When stop mode is entered, the CM03 bit becomes 1.
Figure 9.2
CM0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
System Clock Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
010000
Symbol CM1
Bit Symbol CM10 - (b4-b1) - (b5) - (b6) CM17 Bit Name
Address 0007h
Function 0: Clock oscillates 1: All clocks stop (stop mode) Set to 0
After Reset 0010 0000b
RW RW
All clock stop control bit (2, 3, 5)
Reserved bits
RW
Reserved bit
Set to 1
RW
Reserved bit
Set to 0 0: Main clock 1: PLL clock
RW
CPU clock select bit 1 (4, 5)
RW
NOTES: 1. Set the CM1 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. When the CM10 bit is set to 1, the XOUT pin outputs "H" and the on-chip feedback resistor is disconnected. Pins XIN, XCIN, and XCOUT are placed in high-impedance states. 3. When the CM10 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). Do not set the CM10 bit to 1, when the CM20 bit in the CM2 register is set to 1 (oscillation stop detect function used) or the CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock). 4. Set the CM17 bit to 1 after the PLL clock oscillation stablilizes. 5. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), writes to bits CM10 and CM17 have no effect. If the PM22 bit in the PM2 register is set to 1 (on-chip oscillator clock as count source for watchdog timer), a write to the CM10 bit has no effect.
Figure 9.3
CM1 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
Main Clock Division Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol MCD
Bit Symbol MCD0 Bit Name
Address 000Ch
Function
After Reset XXX0 1000b
RW RW
b4 b3 b2 b1 b0
MCD1 Main clock division select bits(2, 3)
MCD2
MCD3
1 0 0 1 0: Divide-by-1 (no division) mode 0 0 0 1 0: Divide-by-2 mode 0 0 0 1 1: Divide-by-3 mode 0 0 1 0 0: Divide-by-4 mode 0 0 1 1 0: Divide-by-6 mode 0 1 0 0 0: Divide-by-8 mode 0 1 0 1 0: Divide-by-10 mode 0 1 1 0 0: Divide-by-12 mode 0 1 1 1 0: Divide-by-14 mode 0 0 0 0 0: Divide-by-16 mode Do not set values other than the above
RW
RW
RW
MCD4
- (b7-b5)
RW
Reserved bits
Read as undefined value
-
NOTES: 1. Set the MCD register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. When stop mode or low-power consumption mode is entered, bits MCD4 to MCD0 become 01000b. In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit in the CM0 register is set to 1 (main clock stops). 3. When the PM24 bit in the PM2 register is set to 0 (clock selected by the CM07 bit), access the CAN-associated registers after bits MCD4 to MCD0 are set to 10010b.
Figure 9.4
MCD Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
Oscillation Stop Detection Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol CM2
Bit Symbol CM20 Bit Name Oscillation stop detection enable bit(2) CPU clock select bit 2 (3, 4)
Address 000Dh
Function
After Reset 00h
RW RW
0: Oscillation stop detect function not used 1: Oscillation stop detect function used 0: Clock selected by the CM17 bit 1: On-chip oscillator clock 0: Loss of main clock not detected 1: Loss of main clock detected 0: Main clock oscillates 1: Main clock stops Set to 0
CM21
RW
CM22
Oscillation stop detection flag (5)
RW
CM23 - (b7-b4)
Main clock monitor flag (6)
RO
Reserved bits
RW
NOTES: 1. Set the CM2 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the CM20 bit has no effect. 3. When a loss of the main clock is detected while the CM20 bit is set to 1, the CM21 bit becomes 1. Although the main clock restarts oscillating, the CM21 bit does not become 0. To use the main clock as the CPU clock source after the main clock restarts oscillating, set the CM21 bit to 0 by a program. 4. When both the CM20 and CM23 bits are set to 1, do not set the CM21 bit to 0. 5. When a loss of the main clock is detected, the CM22 bit becomes 1. The CM22 bit can only be set to 0, not 1, by a program. If the CM22 bit is set to 0 by a program while the main clock is stopped, the CM22 bit does not become 1 until another loss of the main clock is detected after the main clock restarts oscillating. 6. Determine the main clock state by reading the CM23 bit several times after the oscillation stop detection interrupt is generated.
Figure 9.5
CM2 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
PLL Control Register 0 (1, 2, 5)
b7 b6 b5 b4 b3 b2 b1 b0
101
Symbol PLC0
Bit Symbol PLC00 Programmable counter select bits(3) Bit Name
Address 0026h
Function
After Reset 0001 X010b
RW RW
The VCO clock is the main clock multiplied by the following variables.
b2 b1 b0
PLC01
0 1 1: Multiply-by-6 1 0 0: Multiply-by-8 Do not set to values other than the above
RW
PLC02 - (b3) - (b4) - (b5) - (b6) PLC07
RW
Reserved bit
Read as undefined value
-
Reserved bit
Set to 1
RW
Reserved bit
Set to 0
RW
Reserved bit
Set to 1 0: PLL stops 1: PLL runs
RW
Operation enable bit(4)
RW
NOTES: 1. Set the PLC0 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the PLC0 register has no effect. 3. Set bits PLC02 to PLC00 while the PLC07 bit is 0. Bits PLC02 to PLC00 can be written only once. 4. Enter wait mode or stop mode after the CM17 bit is set to 0 (main clock as CPU clock source) and then the PLC07 bit to 0. 5. Set registers PLC0 and PLC1 simultaneously in 16-bit units .
PLL Control Register 1(1, 2, 3, 4)
b7 b6 b5 b4 b3 b2 b1 b0
000
0
10
Syambol PLC1
Bit Symbol - (b0) - (b1) PLC12 - (b3) - (b4) - (b7-b5) Bit Name Reserved bit
Address 0027h
Function Set to 0
After Reset 000X 0000b
RW
RW RW RW RW
-
Reserved bit
Set to 1 0: Divide-by-2 1: Divide-by-3 Set to 0
PLL clock division select bit
Reserved bit
Reserved bit
Read as undefined value
Reserved bits
Set to 0
RW
NOTES: 1. Set the PLC1 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to the the PLC1 register has no effect. 3. Set the PLC1 register while the PLC07 bit is 0 (PLL stopped).The PLC1 register can be written only once. 4. Set registers PLC0 and PLC1 simultaneously in 16-bit units.
Figure 9.6
PLC0 Register, PLC1 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
Processor Mode Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PM2
Bit Symbol - (b0) PM21 Bit Name Reserved bit
Address 0013h
Function Set to 0
After Reset 00h
RW RW
System clock protect bit (2, 3)
0: Protects a clock by the PRCR register 1: Disables a clock change 0: CPU clock as count source for the watchdog timer 1: On-chip oscillator clock as count source for the watchdog timer Set to 0 0: Clock selected by the CM07 bit 1: Main clock(5) 0: f1 1: fCAN
b7 b6
RW
PM22
WDT count source protect bit (2, 4)
RW
- (b3) PM24
Reserved bit
RW
CPU clock select bit 3
RW
PM25
CAN clock select bit
RW
PM26 f2n clock source select bits PM27
0 0: Clock selected by the CM21 bit 0 1: XIN clock (fXIND) 1 0: On-chip oscillator clock (fROC) 1 1: Do not set to this value
RW
RW
NOTES: 1. Set the PM2 register after the PRC1 bit in the PRCR register is set to 1 (write enable). 2. Once bits PM22 and PM21 are set to 1, they cannot be set to 0 by a program. 3. When the PM21 bit is set to 1; * the CPU clock does not stop even if the WAIT instruction is executed * writes to the following bits have no effect - the CM02 bit in the CM0 register - the CM05 bit in the CM0 register - the CM07 bit in the CM0 register (CPU clock source is not changed) - the CM10 bit in the CM1 register (the MCU does not enter stop mode) - the CM17 bit in the CM1 register (CPU clock source is not changed) - the CM20 bit in the CM2 register (oscillation stop detect function setting is not changed) - all bits in registers PLC0 and PLC1 (PLL frequency synthesizer setting is not changed) 4. When the PM22 bit is set to 1; * the on-chip oscillator starts oscillating and the on-chip oscillator clock becomes the count source of the watchdog timer * write to the CM10 bit in the CM1 register is disabled (writing a 1 has no effect and the MCU does not enter stop mode) * the watchdog timer keeps operating when the MCU is in wait mode or in hold state 5. When the PM25 bit is set to 1 (CAN clock is fCAN), set the PM24 bit to 1 before accessing the CAN-associated registers.
Figure 9.7
PM2 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCSPR
Bit Symbol CNT0 Bit Name
Address 035Fh
Function
After Reset(2) 0XXX 0000b
RW RW
CNT1 Division rate select bits (1) CNT2
If the setting value is n, f2n is the main clock, on-chip oscillator clock, or PLL clock divided by 2n. When n is set to 0, no division is selected
RW
RW
CNT3
- (b6-b4)
RW
Reserved bits
Read as undefined value 0: Divider stops 1: Divider operates
-
CST
Operation enable bit
RW
NOTES: 1. Set bits CNT3 to CNT0 after the CST bit is set to 0. 2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed.
Clock Prescaler Reset Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Bit Symbol
- (b6-b0)
Address 0341h
Bit Name Unimplemented. Write 0. Read as undefined value. Clock prescaler reset bit Function
After Reset 0XXX XXXXb
RW
-
CPSR
When the CPSR bit is set to 1, a divider for fC32 is reset. Read as 0.
RW
Figure 9.8
TCSPR Register, CPSRF Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
9.1.1
Main Clock
Main clock oscillation circuit generates the main clock. The main clock is used as the clock source for the CPU clock and peripheral function clocks. The main clock oscillation circuit is configured by connecting an oscillator between the XIN and XOUT pins. The circuit has an on-chip feedback resistor. The feedback resistor is disconnected from the oscillation circuit in stop mode to reduce power consumption. The main clock oscillation circuit may also be configured by feeding an externally generated clock to the XIN pin. Figure 9.9 shows examples of main clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The main clock divided-by-eight becomes the CPU clock source after reset. To reduce power consumption, set the CM05 bit in the CM0 register to 1 (main clock stopped) after the sub clock or on-chip oscillator clock is selected as the CPU clock sources. In this case, the XOUT pin outputs an "H" signal. The XIN pin is pulled up to the XOUT pin via the feedback resistor which remains on. When an external clock is input to the XIN pin, do not set the CM05 bit to 1. All clocks, including the main clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details.
MCU (On-chip feedback resistor) XIN Oscillator XOUT Rd(1) VSS
CIN
MCU (On-chip feedback resistor) XIN Externally generated clock VCC VSS
COUT XOUT Open
NOTE: 1. Insert a damping resistor if required. Resistance values vary depending on the oscillator setting. Use the resistance values recommended by the oscillator manufacturer. If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between XIN and XOUT following the instructions.
Figure 9.9
Main Clock Circuit Connection
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9. Clock Generation Circuits
9.1.2
Sub Clock
Sub clock oscillation circuit generates the sub clock. The sub clock is used as the clock source for the CPU clock and for timer A and timer B. fC, which has the same frequency as the sub clock can be output from the CLKOUT pin. The sub clock oscillation circuit is configured by connecting a crystal oscillator between the XCIN and XCOUT pins. The circuit has an on-chip feedback resistor. The feedback resistor is disconnected from the oscillation circuit in stop mode to reduce power consumption. The sub clock oscillation circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure 9.10 shows an example of sub clock circuit connection. Circuit constants vary depending on each oscillator. Use the circuit constant recommended by each oscillator manufacturer. The sub clock is stopped after reset, and the feedback resistor is disconnected from the oscillation circuit. To start oscillating the sub clock oscillation circuit, set both the PD8_7 and PD8_6 bits in the PD8 register to 0 (input mode), the PU25 bit in the PUR2 register to 0 (not pulled up), and then the CM04 bit in the CM0 register to 1 (XCIN-XCOUT oscillation function). To input the externally generated clock to the XCIN pin, set the PD8_7 bit to 0, the PU25 bit to 0, and then the CM04 bit to 1. A clock input to the XCIN pin becomes the clock source for the sub clock. When the CM07 bit in the CM0 register is set to 1 (sub clock) after the sub clock oscillation stabilizes, the sub clock becomes the CPU clock source. All clocks, including the sub clock, stop in stop mode. Refer to 9.5 Power Consumption Control for details.
MCU (On-chip feedback resistor) XCIN Oscillator XCOUT RCd(1) VSS
CCIN
MCU (On-chip feedback resistor) XCIN Externally generated clock VCC VSS
CCOUT XCOUT Open
NOTE: 1. Insert a damping resistor if required. Resistance values vary depending on the oscillator setting. Use the resistance values recommended by the oscillator manufacturer. If the oscillator manufacturer recommends that a feedback resistor be added to the chip externally, insert a feedback resistor between XCIN and XCOUT following the instructions.
Figure 9.10
Sub Clock Circuit Connection
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9. Clock Generation Circuits
9.1.3
On-Chip Oscillator Clock
On-chip oscillator generates the 1-MHz on-chip oscillator clock. The on-chip oscillator clock is used as the clock source for the CPU clock and peripheral function clocks. The on-chip oscillator clock is stopped after reset. When the CM21 bit in the CM2 register is set to 1 (on-chip oscillator clock), the on-chip oscillator starts oscillating and becomes the clock source for the CPU clock and peripheral function clocks in place of the main clock. Table 9.2 lists on-chip oscillator start conditions. Table 9.2
CM2 Register CM21 1 0 0 0 1 0
On-Chip Oscillator Start Condition
PM2 Register PM22 PM27, PM26 00b 00b 10b Applications Clock source for the CPU clock and peripheral function clock Count source for the watchdog timer Clock source for f2n
9.1.3.1
Oscillation Stop Detect Function
When the main clock is terminated running by an external factor, the on-chip oscillator automatically starts oscillating to provide the clock. When the CM 20 bit in the CM2 register is set to 1 (oscillation stop detect function used), an oscillation stop detection interrupt request is generated as soon as the main clock is lost. Simultaneously, the on-chip oscillator starts oscillating. The on-chip oscillator clock takes the place of the main clock as the clock source for the CPU clock and peripheral function clocks. Associated bits in the CM2 register are changed as follows: * CM21 bit becomes 1 (on-chip oscillator clock becomes the CPU clock) * CM22 bit becomes 1 (loss of main clock stop is detected) * CM23 bit becomes 1 (main clock stops) The oscillation stop detection interrupt shares the vector with the watchdog timer interrupt and the Vdet4 detection interrupt. When these interrupts are used simultaneously, verify the CM22 bit in the interrupt routine to determine if an oscillation stop detection interrupt request has been generated. When the main clock resumes its operation after a loss of the main clock is detected, the main clock can be selected as the clock source for the CPU clock and peripheral function clocks by a program. Figure 9.11 shows the procedure to switch the clock source from the on-chip oscillator clock to the main clock. In low-speed mode, when the main clock is lost while the CM20 bit is set to 1, an oscillation stop detection interrupt request is generated, and the on-chip oscillator starts oscillating. The sub clock remains as the source for the CPU clock. The on-chip oscillator clock becomes the source for the peripheral function clocks. When the peripheral function clocks are stopped, the oscillation stop detect function cannot be used. To enter wait mode while using the oscillation stop detect function, set the CM02 bit in the CM0 register to 0 (peripheral clocks do not stop in wait mode). The oscillation stop detect function is a precaution against the unintended termination of the main clock by an external factor. Set the CM20 bit to 0 (oscillation stop detect function not used) when the main clock is stopped by a program, i.e., entering stop mode or setting the CM05 bit in the CM0 register to 1 (main clock stops). When the main clock frequency is 2 MHz or lower, the oscillation stop detect function is not available. In this case, set the CM20 bit to 0.
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9. Clock Generation Circuits
Start
Read the CM23 bit in the CM2 register 1 (Main clock stops) 0 (Main clock oscillates)
Verified several times? YES PRCR register: PRC0 bit = 1 MCD register: bits MCD4 to MCD0 = 01000b CM2 register: CM22 bit = 0 CM2 register: CM21 bit = 0 PRC0 bit = 0
NO
Enable writing to registers associated with clocks Divide-by-8 mode Loss of the main clock is not detected Select the main clock as the CPU clock source Disable writing to registers associated with clocks
End
Figure 9.11
Procedure to Switch from On-chip Oscillator Clock to Main Clock
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9. Clock Generation Circuits
9.1.4
PLL Clock
The PLL frequency synthesizer generates the PLL clock by multiplying the main clock. The PLL clock can be used as the clock source for the CPU clock and peripheral function clocks. The PLL frequency synthesizer is stopped after reset. When the PLC07 bit in the PLC0 register is set to 1 (PLL runs), the PLL frequency synthesizer starts operating. Waiting time, tsu(PLL), is required before the PLL clock is stabilized. The PLL clock is the VCO clock divided by either 2 or 3. When the PLL clock is used as the clock source for the CPU clock or peripheral function clocks, set each bit as shown in Table 9.3. Figure 9.12 shows the procedure to use the PLL clock as the CPU clock source. Prior to entering wait mode or stop mode, set the CM17 bit in the CM1 register to 0 (main clock as CPU clock source) and then the PLC07 bit to 0 (PLL stops). Table 9.3
Multiplication factor 2 3 8/3 4
Bit Settings to Use PLL Clock as CPU Clock Source
PLC0 Register PLC02 bit 0 1 PLC01 bit 1 0 PLC00 bit 1 0 PLC1 Register PLC12 bit 1 0 1 0 PLL Clock fPLL = 2 x fXIN fPLL = 3 x fXIN fPLL = 8/3 x fXIN fPLL = 4 x fXIN
Start
PRCR register: PRC0 bit = 1 CM2 register: CM21 bit = 0 CM0 register: CM07 bit = 0
Enable writing to registers associated with clocks Select the main clock as the CPU clock source (Set after a main clock oscillation stabilizes) Select the multiplication factor for the PLL clock (Set registers PLC0 and PLC1 simultaneously in 16-bit units) PLC1 PLC0 Multiplication factor for PLL clock 00000010 01010011b x 6/2 = 3 00000010 01010100b x 8/2 = 4 00000110 01010011b x 6/3 = 2 00000110 01010100b x 8/3 = 2.66 PLL runs Wait for PLL frequency synthesizer to stabilize Select the PLL clock as the clock source for the CPU clock and peripheral function clock Disable writing to registers associated with clocks
Set registers PLC0 and PLC1
PLC0 register: PLC07 bit = 1 Wait for tsu(PLL) CM1 register : CM17 bit = 1 PRC0 bit = 0 End
Figure 9.12
Procedure to Use PLL Clock as CPU Clock Source
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9. Clock Generation Circuits
9.2
CPU Clock and BCLK
The CPU clock is used to operate the CPU and also used as the count source for the watchdog timer. After reset, the CPU clock is the main clock divided by eight. The bus clock (BCLK) has the same frequency as the CPU clock and can be output from the BCLK pin in memory expansion mode or microprocessor mode. Refer to 9.4 Clock Output Function for details. The main clock, sub clock, on-chip oscillator clock, or PLL clock can be selected as the clock source for the CPU clock. When the main clock, on-chip oscillator clock, or PLL clock is selected as the clock source for the CPU clock, the selected clock source divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 becomes the CPU clock. Bits MCD4 to MCD0 in the MCD register select the clock division. When the MCU enters stop mode or low-power consumption mode, bits MCD4 to MCD0 are set to 01000b (divide-by-8 mode). Therefore, when the CPU clock source is switched to the main clock next time, the CPU clock is the main clock divided by eight. Refer to 9.5 Power Consumption Control for details.
9.3
Peripheral Function Clock
The peripheral function clocks are used to operate the peripheral functions excluding the watchdog timer. The clock selected by the CM17 bit in the CM1 register and the CM21 bit in the CM2 register (any of the main clock, PLL clock, or on-chip oscillator clock) becomes the peripheral function clock source (fPFC).
9.3.1
f1, f8, f32, and f2n
f1, f8 and f32 are fPFC divided by 1, 8, or 32. Bits PM27 and PM 26 in the PM2 register select the f2n clock source from fPFC, XIN clock (fXIND), and the on-chip oscillator clock (fROC). Bits CNT3 to CNT0 in the TCSPR register select the f2n division. (n = 1 to 15. No division when n = 0.) When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fPFC stops. When bits PM27 and PM26 in the PM2 register are set to 10b (on-chip oscillator clock is selected for the f2n clock source), f2n does not stop in wait mode. f1, f8, and f2n are used to operate the serial interface and also is used as the count source for timer A and timer B. f1 is also used to operate the intelligent I/O and CAN modules. The CLKOUT pin outputs f8 and f32. Refer to 9.4 Clock Output Function for details.
9.3.2
fAD
fAD is used to operate the A/D converter and has the same frequency as fPFC. When wait mode is entered while the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode) or when the CM05 bit is set to 1 using the main clock as the peripheral function clock source, fAD stops.
9.3.3
fC32
fC32 is the sub clock divided by 32. fC32 is used as the count source for timer A and timer B. fC32 is available if the sub clock is running.
9.3.4
fCAN
fCAN has the same frequency as the main clock. It is the clock for the CAN module only.
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9. Clock Generation Circuits
9.4
Clock Output Function
The CLKOUT pin outputs fC, f8, or f32. The BCLK clock, which has the same frequency as the CPU clock, can be output from the BCLK pin in memory expansion mode or microprocessor mode. Table 9.4 lists CLKOUT pin function in single-chip mode. Table 9.5 lists CLKOUT pin function in memory expansion mode and microprocessor mode. Table 9.4 CLKOUT Pin Function in Single-Chip Mode
P5_3/CLKOUT Pin Function I/O port P5_3 Outputs fC Outputs f8 Outputs f32
CM0 Register(1) Bits CM01 and CM00 00b 01b 10b 11b
NOTE: 1. Rewrite the CM0 register after setting the PRC0 bit in the PRCR register to 1 (write enable).
Table 9.5
CLKOUT Pin Function in Memory Expansion Mode and Microprocessor Mode
PM1 Register(2) 00b 10b 11b 01b 0 or 1 0 or 1 0 or 1 PM0 Register(2) PM07 bit 0 1 0 or 1 0 or 1 0 or 1 0 or 1 CLKOUT/BCLK/ALE Pin Function Outputs BCLK Outputs "L" (does not function as P5_3) Outputs ALE Outputs fC Outputs f8 Outputs f32
CM0 Register(1)
Bits CM01 and CM00 Bits PM15 and PM14
00b
01b 10b 11b
NOTES: 1. Change the CM0 register after setting the PRC0 bit in the PRCR register to 1 (write enable). 2. Change registers PM0 and PM1 after setting the PRC1 bit in the PRCR register to 1 (write enable).
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9. Clock Generation Circuits
9.5
Power Consumption Control
The power consumption control is enabled by controlling a CPU clock frequency. The higher the CPU clock frequency is, the more the processing power is available. The lower the CPU clock frequency is, the less power is consumed. When unnecessary oscillation circuits are stopped, power consumption is further reduced. CPU operating mode, wait mode, and stop mode are provided as the power consumption control. CPU operating mode is further separated into the following modes; main clock mode, PLL mode, low-speed mode, low-power consumption mode, on-chip oscillator mode, on-chip oscillator low-power consumption mode, and main clock direct mode. Figure 9.13 shows a mode transition diagram.
Reset
(note 1)
Main clock direct mode
PLL clock PLL mode
Stop mode
CM10 = 1 Interrupt
Main clock mode
Wait mode
T A I ion W uct r st in pt ru er t In WAIT instruction
On-chip oscillator mode
On-chip oscillator clock
Interrupt
Low-speed mode
Sub clock
On-chip oscillator low-power consumption mode
Low-power consumption mode
WAIT instruction Interrupt CM10: bit in the CM1 register NOTE: 1. Bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) after reset.
Figure 9.13
Mode Transition
9.5.1
CPU operating mode
The CPU clock can be selected from the main clock, sub clock, on-chip oscillator clock, or PLL clock. When switching the CPU clock source, wait until the new CPU clock source stabilizes. To change the CPU clock source from the sub clock, on-chip oscillator clock, or PLL clock, set it to the main clock once and then switch it to another clock. To switch the CPU clock source from the on-chip oscillator clock to the main clock, set bits MCD4 to MCD0 in the MCD register to 01000b (divided-by-8 mode) in on-chip oscillator mode. Table 9.6 lists bit setting and operation mode associated with clocks.
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9. Clock Generation Circuits
9.5.1.1
Main Clock Mode
The main clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The main clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.2
PLL Mode
The PLL clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The PLL clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.3
Low-Speed Mode
The sub clock is used as the source for the CPU clock. The main clock, PLL clock, or on-chip oscillator clock can be selected as the source for fPFC by setting bits CM17 and CM21 after the CPU clock is switched to the sub clock using the CM07 bit. In low-speed mode, fC32 can be used as the count source for timer A and timer B. Out of CPU operating modes, only main clock mode and low-power consumption mode can be entered from low-speed mode. Enter main clock mode first prior to entering different CPU operating modes other than the low-power consumption mode.
9.5.1.4
Low-Power Consumption Mode
The MCU enters low-power consumption mode when the main clock stops in low-speed mode. The sub clock is used as the source for the CPU clock. The on-chip oscillator clock can be selected as the source for fPFC by setting the CM21 bit after entering low-power consumption mode. fC32 can be used as the count source for timer A and timer B. When low-power consumption mode is entered, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). Therefore, when next time the CPU clock source is switched to the main clock, the CPU clock is the main clock divided by eight. However, bits MCD4 to MCD0 do not become 01000b if the main clock is stopped by setting the CM05 bit to 1 while the on-ship oscillator clock is selected as the source for fPFC in low-speed mode. In this case, set bits MCD4 to MCD0 to 01000b by a program and then switch the CPU clock source to the main clock.
9.5.1.5
On-Chip Oscillator Mode
The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.6
On-Chip Oscillator Low-Power Consumption Mode
The MCU enters on-chip oscillator low-power consumption mode when the main clock stops in on-chip oscillator mode. The on-chip oscillator clock divided by 1 (no division), 2, 3, 4, 6, 8, 10, 12, 14, or 16 is used as the source for the CPU clock. The on-chip oscillator clock is also used as the source for fPFC. When the sub clock is running, fC32 can be used as the count source for timer A and timer B.
9.5.1.7
Main Clock Direct Mode
The main clock is used as the source for the CPU clock in main clock direct mode. The PLL clock is used for fPFC. When fCAN is used to operate the CAN modules, enter main clock direct mode before accessing the CANassociated registers.
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Table 9.6
CPU Clock Source
9. Clock Generation Circuits
Operation Mode Setting
Oscillation Control Operating Mode CM0 Register CM05 Main clock mode 0 0 0 0 1 0 1 CM04 0 or 1 0 or 1 0 or 1 1 1 0 or 1 0 or 1 PLC0 Register PLC07 0 or 1 0 or 1 1 0 or 1 0 0 or 1 0 CM2 Register CM21(1) 0 0 0 0 0 1 1 CM1 Register CM17 0 0 1 0 0 0 0 Selector CM0 Register CM07 0 0 0 1 1 0 0 PM2 Register PM24 0 1 0 0 0 0 0
Main clock PLL clock Sub clock
Main clock direct mode(2) PLL mode Low-speed mode Low power consumption mode On-chip oscillator mode On-chip oscillator lowpower consumption mode
On-chip oscillator clock
NOTES: 1. The CM21 bit in the CM2 register has both the oscillation control and selector functions. 2. Refer to 23.2 CAN Clock and CPU Clock for details.
9.5.2
Wait Mode
In wait mode, the CPU and watchdog timer stop operating. If the PM22 bit in the PM2 register is set to 1 (onchip oscillator clock as watchdog timer count source), the watchdog timer continues operating. Since the main clock, sub clock, and on-chip oscillator clock continue running, peripheral functions using these clocks as their clock source also continue to operate.
9.5.2.1
Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is set to 1 (peripheral clocks stop in wait mode), fAD, f1, f8, and f32 stop in wait mode. f2n, which uses the clock selected by the CM21 bit in the CM2 register as its clock source, also stops in wait mode. Power consumption can be reduced by stopping these peripheral clocks. f2n, which uses the XIN clock (fXIND) or on-chip oscillator clock as its clock source, and fC32 do not stop even in wait mode.
9.5.2.2
Entering Wait Mode
To enter wait mode with the CM02 bit in the CM0 register set to 1, set bits MCD4 to MCD0 in the MCD register for the CPU clock frequency to be 10 MHz or lower after dividing the main clock. Figure 9.14 shows a procedure to enter wait mode.
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9. Clock Generation Circuits
Start (1) Initial setting RLVL register: bits RLVL2 to RLVL0 = 7 Set an interrupt priority level of each interrupt Initial setting for the wait/stop mode exit interrupt priority level
(2) Before entering wait mode I flag = 0 Set the interrupt priority level (ILVL2 to ILVL0) of the interrupt used to exit wait mode Set the interrupt priority level of the interrupts, which are not used to exit wait mode, to 0 FLG register: set IPL Bits RLVL2 to RLVL0 = the same level as IPL Select the operating mode from the following: -main clock mode -low-speed mode -on-chip oscillator mode -on-chip oscillator low-power consumption mode I flag = 1 Execute the WAIT instruction Wait mode (Note 2) Set the processor interrupt priority level (IPL) Set the exit interrupt priority level (RLVL2 to RLVL0) Interrupt disabled
(NOTE 1)
When the CM02 bit in the CM0 register is 1, set bits MCD4 to MCD0 in the MCD register for the CPU frequency to be 10 MHz or lower.
Interrupt enabled
(3) After exiting wait mode RLVL register: bits RLVL2 to RLVL0 = 7 End NOTES: 1. Set each level to meet the formula shown as below. (ILVL2 to ILVL0) > IPL = (RLVL2 to RLVL0) 2. Insert at least 4 NOP's after WAIT instruction. Set the exit priority level as soon as exiting wait mode
Figure 9.14
Procedure to Enter Wait Mode
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9. Clock Generation Circuits
9.5.2.3
Pin States in Wait Mode
Table 9.7 lists pin states in wait mode. Table 9.7 Pin States in Wait Mode
Pin Address bus, data bus, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK ALE Ports CLKOUT When fC is selected Memory Expansion Mode Microprocessor Mode Maintain the state immediately before entering wait mode "H" "H" "L" Maintain the state immediately before entering wait mode Continue to output the clock When f8, f32 are selected * When the CM02 bit in the CM0 register is 0 (peripheral clocks do not stop in wait mode): Continue to output the clock * When the CM02 bit is 1 (peripheral clock stops in wait mode): The clock is stopped and holds the level immediately before entering wait mode Single-Chip Mode
9.5.2.4
Exiting Wait Mode
Wait mode is exited by the hardware reset 1, hardware reset 2, NMI interrupt, Vdet4 detection interrupt, or peripheral function interrupts. As for a peripheral function interrupt that is not used to exit wait mode, set bits ILVL2 to ILVL0 in the corresponding Interrupt Control Register to 000b (interrupt disabled) before executing the WAIT instruction. The CM02 bit setting in the CM0 register affects the use of the peripheral function interrupts to exit wait mode. When the CM02 bit is set to 0 (peripheral clocks do not stop in wait mode), any peripheral function interrupts can be used to exit wait mode. When the CM02 bit is set to 1 (peripheral clocks stop in wait mode), the peripheral functions clocked by the peripheral function clocks stop, and therefore, the peripheral function interrupts cannot be used to exit wait mode. However, the peripheral functions clocked by the external clock and fC32 do not stop regardless of the CM02 bit setting. Also, f2n, which uses the XIN clock (fXIND) or onchip oscillator clock as its clock source does not stop. The interrupts generated by the peripheral functions which operate using these clocks can be used to exit wait mode. When the MCU exits wait mode by the peripheral function interrupts or NMI interrupt, the CPU clock does not change before and after the WAIT instruction is executed. Table 9.8 lists interrupts to be used to exit wait mode and usage conditions.
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Table 9.8
NMI interrupt Vdet4 detection interrupt Serial interface interrupt
9. Clock Generation Circuits
Interrupts to Exit Wait Mode and Usage Conditions
Interrupt Available Available Available when the source clock is the internal clock or external clock. Available Available in one-shot mode or singlesweep mode Available in all modes When CM02 = 0 Available Available Available when the source clock is the external clock or f2n (when fXIND or onchip oscillator clock is selected). Available Not available Available in event counter mode or when the count source is fC32 or f2n (when fXIND or on-chip oscillator clock is selected) Available Available when fCAN is used Not available When CM02 = 1
Key input interrupt A/D conversion interrupt Timer A interrupt Timer B interrupt
INT interrupt CAN interrupt Intelligent I/O Interrupt
Available Available Available
9.5.3
Stop Mode
In stop mode, all clocks are stopped. Since the CPU clock and peripheral function clocks are stopped, the CPU and the peripheral functions which are operated by these clocks stop their operation. The least power is required to operate the MCU in stop mode. Enter stop mode from main clock mode.
9.5.3.1
Entering Stop Mode
Stop mode is entered by setting the CM10 bit in the CM1 register to 1 (all clocks stop) while the NMI pin is held "H". Also, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode) by setting the CM10 bit to 1. Figure 9.15 shows a procedure to enter stop mode. When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction queue, and the program stops. When stop mode is exited, the instruction lined in the queue is executed before the exit interrupt routine is handled. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1. fset I bset 0, cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0, prcr . . . ; I flag is set to 1 ; all clocks stopped (stop mode) ; jmp.b instruction executed (no instruction between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; protection set
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
Start (1) Initial setting RLVL register: bits RLVL2 to RLVL0 = 7 Set an interrupt priority level of each interrupt (2) Before entering stop mode I flag = 0 Set the interrupt priority level (ILVL2 to ILVL0) of the interrupt used to exit stop mode Set the interrupt priority level of the interrupts, which is not used to exit stop mode, to 0 FLG register: set IPL Bits RLVL2 to RLVL0 = the same level as IPL PRCR register: PRC0 bit = 1 PRC1 bit = 1 CM1 register: CM2 register: CM0 register: PM2 register: CM17 bit = 0 CM21 bit = 0 CM07 bit = 0 PM24 bit = 0 Set the processor interrupt priority level (IPL)* Set the exit interrupt priority level (RLVL2 to RLVL0)* Enable writing to registers associated with clocks Interrupt disabled (ILVL2 to ILVL0) > IPL* = (RLVL2 to RLVL0)* Set the wait/stop mode exit interrupt priority level to 7.
Select the main clock as the CPU clock source (Set after a main clock oscillation stabilizes)
When the oscillation stop detect function is used CM2 register: CM20 bit = 0 Disable oscillation stop detect function
I flag = 1 CM1 register: CM10 bit = 1 Stop mode (3) After exiting wait mode RLVL register: bits RLVL2 to RLVL0 = 7 End (Note 1)
Interrupt enabled All clocks stop
Set the exit priority level as soon as exiting wait mode
NOTE: 1. Insert the jmp.b instruction as follows after the instruction to set the CM10 bit to 1. bset 0, cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0, prcr . . . ; all clocks stopped (stop mode) ; jmp.b instruction executed (no instruction ; between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; protection set
Figure 9.15
Procedure to Enter Stop Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
9. Clock Generation Circuits
9.5.3.2
Pin States in Stop Mode
Table 9.9 lists pin states in stop mode. Table 9.9 Pin States in Stop Mode
Pin Address Bus, Data Bus, CS0 to CS3, BHE RD, WR, WRL, WRH HLDA, BCLK ALE Ports CLKOUT When fC is selected When f8, f32 are selected XIN XOUT XCIN, XCOUT Memory Expansion Mode Microprocessor Mode Maintain the state immediately before entering stop mode "H" "H" "H" Maintain the state immediately before entering stop mode "H" The clock is stopped and holds the level immediately before entering stop mode Placed in a high-impedance state "H" Placed in a high-impedance state Single-Chip Mode
9.5.3.3
Exiting Stop Mode
Stop mode is exited by the hardware reset 1, NMI interrupt, Vdet4 detection interrupt, or peripheral function interrupts. The following are the peripheral function interrupts that can be used to exit stop mode.
* Key input interrupt * INT interrupt * Timer A and timer B interrupts
(Available when the timer counts external pulse having 100-Hz frequency or lower in event counter mode) When only the hardware reset 1, NMI interrupt, or Vdet4 detection interrupt is used to exit stop mode, set bits ILVL2 to ILVL0 in the Interrupt Control Registers for all the peripheral function interrupts to 000b (interrupt disabled) before setting the CM10 bit in the CM1 register to 1 (all clocks stop). If the voltage applied to pins VCC1 and VCC2 drops below 3.0 V in stop mode, exit stop mode by the hardware reset 1 after the voltage has satisfied the recommended operating conditions.
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9. Clock Generation Circuits
9.6
System Clock Protect Function
The system clock protect function prohibits the clock setting from being rewritten in order to prevent the CPU clock source from being changed when a program goes out of control. When the PM21 bit in the PM2 register is set to 1 (disables a clock change), the following bits cannot be written: * Bits CM02, CM05, and CM07 in the CM0 register * Bits CM10 and CM17 in the CM1 register * The CM20 bit in the CM2 register * All bits in registers PLC0 and PLC1 The CPU clock continues running when the WAIT instruction is executed. Figure 9.16 shows a procedure to use the system clock protect function. Follow the procedure while the CM05 bit in the CM0 register is set to 0 (main clock oscillates) and the CM07 bit to 0 (main clock as CPU clock source).
Start
PRCR register: PRC1 bit = 1 PM2 register: PM21 bit = 1 PRCR register: PRC1 bit = 0 (Note 1)
Enable writing to registers associated with clocks Disable a clock change Disable writing to registers associated with clocks
End
NOTE: 1. When entering wait mode, execute the WAIT instruction while the PM21 bit in the PM2 register is set to 0.
Figure 9.16
Procedure to Use System Clock Protect Function
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10. Protection
10. Protection
The function protects important registers from being inadvertently overwritten in case of a program crash. Figure 10.1 shows the PRCR register. The PRC2 bit in the PRCR register becomes 0 (write disable) by a write to the SFR area after the PRC2 bit is set to 1 (write enable). Set the PD9 or PS3 register immediately after the PRC2 bit is set to 1. Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. Bits PRC0, PRC1, and PRC3 do not become 0 automatically even after a write to the SFR area. Set bits PRC0, PRC1, and PRC3 to 0 by a program.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR
Bit Symbol Bit Name
Address 000Ah
Function
After Reset XXXX 0000b
RW
PRC0
Protect bit 0(1)
Writing to registers CM0, CM1, CM2, MCD, PLC0, and PLC1 is enabled 0: Write disable 1: Write enable Writing to registers PM0, PM1, PM2, INVC0, and INVC1 is enabled 0: Write disable 1: Write enable Writing to registers PD9 and PS3 is enabled 0: Write disable 1: Write enable Writing to registers VCR2 and D4INT is enabled 0: Write disable 1: Write enable
RW
PRC1
Protect bit 1(1)
RW
PRC2
Protect bit 2(2)
RW
PRC3
Protect bit 3(1)
RW
- (b7-b4)
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. Bits PRC0, PRC1, and PRC3 do not become 0 automatically even after a write to the SFR area. Set bits PRC0, PRC1, and PRC3 to 0 by a program. 2. The PRC2 bit becomes 0 by a write to the SFR area after the PRC2 bit is set to 1.
Figure 10.1
PRCR Register
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11. Interrupts
11. Interrupts
11.1 Types of Interrupts
Figure 11.1 shows the types of interrupts.
Software (Non-maskable interrupts)
Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction BRK2 instruction(2) INT instruction NMI Watchdog timer Oscillation stop detection Vdet4 detection Single step(2) Address match DMACII transfer complete
Interrupts
Special (Non-maskable interrupts) Hardware Peripheral function(1) (Maskable interrupts)
NOTES: 1. Peripheral function interrupts are generated by the on-chip peripheral functions in the MCU. 2. Do not use these interrupts. They are for use with development tool only.
Figure 11.1
Interrupts
* Maskable interrupts
The I flag and IPL can enable and disable these interrupts. The interrupt priority order can be changed by using interrupt priority level settings. * Non-maskable interrupt These interrupts cannot be disabled regardless of the I flag and IPL settings.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.2
Software Interrupts
Software interrupts occur when particular instructions are executed. Software interrupts are non-maskable.
11.2.1
Undefined Instruction Interrupt
The undefined instruction interrupt occurs when the UND instruction is executed.
11.2.2
Overflow Interrupt
The overflow interrupt occurs when the INTO instruction is executed while the O flag in the FLG register is 1 (arithmetic operation overflow). Instructions that can set the O flag are: ABS, ADC, ADCF, ADD, ADDX, CMP, CMPX, DIV, DIVU, DIVX, NEG, RMPA, SBB, SCMPU, SHA, SUB, SUBX
11.2.3
BRK Interrupt
The BRK interrupt occurs when the BRK instruction is executed.
11.2.4
BRK2 Interrupt
The BRK2 interrupt occurs when the BRK2 instruction is executed. Do not use this interrupt. This is for use with development support tool only.
11.2.5
INT Instruction Interrupt
The INT instruction interrupt occurs when the INT instruction is executed. The INT instruction can specify software interrupt numbers 0 to 63. Software interrupt numbers 8 to 54 and 57 are assigned to the vector table used for the peripheral function interrupt. This means that the MCU is able to execute the peripheral function interrupt routine by executing the INT instruction. When the INT instruction is executed, values in the FLG register and PC are saved to the stack. The relocatable vector of the specified software interrupt number is stored in PC. The stack, where the data is saved, varies depending on a software interrupt number. ISP is selected for software interrupt numbers 0 to 31. (The U flag in the FLG register becomes 0.) For software interrupt numbers 32 to 63, SP which is selected immediately before executing the INT instruction is used. (The U flag does not change.) For the peripheral function interrupt, the FLG register value is saved and the U flag becomes 0 (ISP selected) when an interrupt request is acknowledged. Therefore, for software interrupt numbers 32 to 54 and 57, SP to be used can differ depending on whether an interrupt is generated by a peripheral function or by the INT instruction.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.3
Hardware Interrupts
Special interrupts and peripheral function interrupts are available as hardware interrupts.
11.3.1
Special Interrupts
Special interrupts are non-maskable.
11.3.1.1
NMI Interrupt
The NMI interrupt occurs when a signal applied to the NMI pin changes from high level ("H") to low level ("L"). Refer to 11.8 NMI Interrupt for details.
11.3.1.2
Watchdog Timer Interrupt
The watchdog timer interrupt occurs when the watchdog timer counter underflows. Refer to 12. Watchdog Timer for details.
11.3.1.3
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt occurs when the MCU detects a loss of the main clock. Refer to 9. Clock Generation Circuits for details.
11.3.1.4
Vdet4 Detection Interrupt
The Vdet4 detection interrupt occurs when the voltage applied to VCC1 rises above or drops below Vdet4. Refer to 6.2 Vdet4 Detection Function for details.
11.3.1.5
Single-Step Interrupt
Do not use the single-step interrupt. This is for use with development support tool only.
11.3.1.6
Address Match Interrupt
When the AIERi bit in the AIER register is set to 1 (address match interrupt enabled), the address match interrupt occurs immediately before executing the instruction stored in the address indicated by the RMADi register (i = 0 to 7). Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if a table data or any address other than the starting address of the instruction is set. Refer to 11.10 Address Match Interrupt for details.
11.3.2
DMACII End-of-Transfer Complete Interrupt
The DMACII transfer complete interrupt is generated by the DMACII function. Refer to 14. DMACII for details.
11.3.3
Peripheral Function Interrupt
The peripheral function interrupt is generated by the on-chip peripheral functions. The peripheral function interrupts and software interrupt numbers 8 to 54 and 57 for the INT instruction use the same interrupt vector table. The peripheral function interrupt is maskable. See Tables 11.2 and 11.3 for the peripheral function interrupt sources. Refer to the descriptions of individual peripheral functions for details.
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11. Interrupts
11.4
High-Speed Interrupt
The high-speed interrupt executes an interrupt sequence in five cycles and returns from the interrupt routine in three cycles. When the FSIT bit in the RLVL register is set to 1 (interrupt priority level 7 is used for the highspeed interrupt), the interrupt that bits ILVL2 to ILVL0 in the Interrupt Control Register are set to 111b (level 7) becomes the high-speed interrupt. Only one interrupt can be set as the high-speed interrupt. To use the high-speed interrupt, do not set multiple interrupts to interrupt priority level 7. Set the DMAII bit in the RLVL register to 0 (interrupt priority level 7 is used for interrupt) to use the high-speed interrupt. Set the starting address of a high-speed interrupt routine in the VCT register. When the high-speed interrupt is acknowledged, the FLG register value is saved into the SVF register and the PC value is saved into the SVP register. A program is executed from an address indicated by the VCT register. Use the FREIT instruction to return from a high-speed interrupt routine. Values saved into registers SVF and SVP are restored to the FLG register and PC by executing the FREIT instruction. The high-speed interrupt, and DMA2 and DMA3 share some of the registers. When using the high-speed interrupt, neither DMA2 nor DMA3 is available. DMA0 and DMA1 can still be used. Figure 11.2 shows a procedure to use high-speed interrupt.
Start
I flag = 0 RLVL register: FSIT bit = 1 DMAII bit = 0 VCT regsiter: Set the starting address of the high-speed interrupt routine Set the peripheral function used for the high-speed interrupt source Interrupt Control Register: Bits ILVL2 to ILVL0 = 111b (level 7) I flag = 1 Operate peripheral functions
Interrupt disabled Interrupt priority level 7 is used for the high-speed interrupt Interrupt priority level 7 is used for interrupt
Set the interrupt priority level in the Interrupt Control Register for the peripheral function used for the high-speed interrupt source. Interrupt enabled
End
Figure 11.2
Procedure to Use High-Speed Interrupt
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11. Interrupts
11.5
Interrupts and Interrupt Vectors
There are four bytes in each interrupt vector. Set the starting address of an interrupt routine in each interrupt vector. When an interrupt request is acknowledged, an interrupt routine is executed from the address set in its interrupt vector. Figure 11.3 shows an interrupt vector.
MSB Vector address+0 Vector address+1 Vector address+2 Vector address+3 8 Low-order bits of address 8 Middle-order bits of address 8 High-order bits of address 00h
LSB
Figure 11.3
Interrupt Vector
11.5.1
Fixed Vector Table
The fixed vector table is allocated in addresses FFFFDCh to FFFFFFh. Table 11.1 lists the fixed vector table. The ID code which is used for the ID code check function of the flash memory is stored to the part of the fixed vector table. Refer to 26.2.2 ID Code Check Function for details. Table 11.1
Interrupt Source Undefined instruction Overflow BRK instruction
Fixed Vector Table
Vector Addresses Address (L) to Address (H) FFFFDCh to FFFFDFh FFFFE0h to FFFFE3h FFFFE4h to FFFFE7h If the content of the address FFFFE7h is FFh, the CPU executes from the address stored in the software interrupt number 0 in the relocatable vector table. Reserved space These addresses are used for Voltage detection function, Clock generation circuit, the watchdog timer interrupt, Watchdog timer oscillation stop detection interrupt, and Vdet4 detection interrupt. Reserved space Reset Remarks Reference M32C/80 series software manual
Address match - Watchdog timer
FFFFE8h to FFFFEBh FFFFECh to FFFFEFh FFFFF0h to FFFFF3h
- NMI Reset
FFFFF4h to FFFFF7h FFFFF8h to FFFFFBh FFFFFCh to FFFFFFh
11.5.2
Relocatable Vector Table
The relocatable vector table occupies 256 bytes beginning from the address set in the INTB register. Tables 11.2 and 11.3 list the relocatable vector table. Set an even address to the starting address of the vector set in the INTB register to increase the interrupt sequence execution rate.
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Table 11.2 Relocatable Vector Tables (1/2)
Vector Table Address Address (L) to Address (H)(1) +0 to +3 (0000h to 0003h) +4 to +31 (0004h to 001Fh) +32 to +35 (0020h to 0023h) +36 to +39 (0024h to 0027h) +40 to +43 (0028h to 002Bh) +44 to +47 (002Ch to 002Fh) +48 to +51 (0030h to 0033h) +52 to +55 (0034h to 0037h) +56 to +59 (0038h to 003Bh) +60 to +63 (003Ch to 003Fh) +64 to +67 (0040h to 0043h) +68 to +71 (0044h to 0047h) +72 to +75 (0048h to 004Bh) +76 to +79 (004Ch to 004Fh) +80 to +83 (0050h to 0053h) +84 to +87 (0054h to 0057h) +88 to +91 (0058h to 005Bh) +92 to +95 (005Ch to 005Fh) +96 to +99 (0060h to 0063h) +100 to +103 (0064h to 0067h) +104 to +107 (0068h to 006Bh) +108 to +111 (006Ch to 006Fh) +112 to +115 (0070h to 0073h) +116 to +119 (0074h to 0077h) +120 to +123 (0078h to 007Bh) +124 to +127 (007Ch to 007Fh) +128 to +131 (0080h to 0083h) +132 to +135 (0084h to 0087h) +136 to +139 (0088h to 008Bh) +140 to +143 (008Ch to 008Fh) +144 to +147 (0090h to 0093h) +148 to +151 (0094h to 0097h) +152 to +155 (0098h to 009Bh) ACK(3) NACK(3) ACK(3) ACK(3) ACK(3) NACK(3) ACK(3) Software Interrupt Number 0 1 to 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Timer B Interrupts Timer B Timer A
11. Interrupts
Interrupt Source BRK instruction(2) Reserved space DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission, NACK(3) UART0 reception, UART1 reception, Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 INT2 INT1 INT0 Timer B5 UART2 transmission, NACK(3) UART2 reception, UART3 reception, UART4 reception, UART3 transmission, UART1 transmission,
Reference M32C/80 Series Software Manual DMAC
Serial interfaces
Serial interfaces
UART4 transmission, NACK(3)
NOTES: 1. These are the addresses offset from the base address set in the INTB register. 2. The I flag can not disable this interrupt. 3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources.
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Table 11.3 Relocatable Vector Tables (2/2)
Vector Table Address Address (L) to Address (H)(1) +156 to +159 (009Ch to 009Fh) Software Interrupt Number 39
11. Interrupts
Interrupt Source Bus conflict detection, Start condition detection/ Stop condition detection (UART2)(3) Bus conflict detection, Start condition detection/ Stop condition detection (UART3 or UART0)(4) Bus conflict detection, Start condition detection/ Stop condition detection (UART4 or UART1)(4) A/D0 Key input Intelligent I/O interrupt 0, CAN10(5), UART5 reception Intelligent I/O interrupt 1, CAN11(5), UART5 transmission Intelligent I/O interrupt 2 Intelligent I/O interrupt 3 Intelligent I/O interrupt 4 Intelligent I/O interrupt 5, CAN12(5), CAN1 wake-up Intelligent I/O interrupt 6 Intelligent I/O interrupt 7 Intelligent I/O interrupt 8
Reference Serial interfaces
+160 to +163 (00A0h to 00A3h)
40
+164 to +167 (00A4h to 00A7h)
41
+168 to +171 (00A8h to 00ABh) +172 to +175 (00ACh to 00AFh) +176 to +179 (00B0h to 00B3h) +180 to +183 (00B4h to 00B7h) +184 to +187 (00B8h to 00BBh) +188 to +191 (00BCh to 00BFh) +192 to +195 (00C0h to 00C3h) +196 to +199 (00C4h to 00C7h) +200 to +203 (00C8h to 00CBh) +204 to +207 (00CCh to 00CFh) +208 to +211 (00D0h to 00D3h)
42 43 44 45 46 47 48 49 50 51 52 53 54
A/D converter Interrupts Intelligent I/O, CAN, UART5, UART6, INT
+212 to +215 (00D4h to 00D7h) Intelligent I/O interrupt 9, CAN00(5), UART6 reception, INT6 Intelligent I/O interrupt 10, CAN01(5), UART6 transmission, INT7 Reserved space Intelligent I/O interrupt 11, CAN02(5), INT8 Reserved space INT instruction(2) +216 to +219 (00D8h to 00DBh)
+220 to +227 (00DCh to 00E3h) +228 to +231 (00E4h to 00E7h) +232 to +255 (00E8h to 00FFh) +0 to +3 (0000h to 0003h) to +252 to +255 (00FCh to 00FFh)
55, 56 57 58 to 63 0 to 63
- Intelligent I/O, CAN, INT - Interrupts
NOTES: 1. These are the addresses offset from the base address set in the INTB register. 2. The I flag can not disable this interrupt. 3. In I2C mode, NACK, ACK, or start/stop condition detection can be the interrupt sources. 4. The IFSR6 bit in the IFSR register selects either UART0 or UART3. The IFSR7 bit selects either UART1 or UART4. 5. Any CAN interrupt source cannot be used in M32C/87B. Only CAN00, CAN01, and CAN02 interrupt sources can be used in M32C/87A.
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11. Interrupts
11.6
Interrupt Request Acknowledgement
Software interrupts occur when their corresponding instructions are executed. The INTO instruction, however, requires the O flag in the FLG register to be 1. Special interrupts occur when their corresponding interrupt requests are generated. For the peripheral function interrupts to be acknowledged, the following conditions must be met: * I flag = 1 * IR bit = 1 * Bits ILVL2 to ILVL0 > IPL The I flag, IPL, IR bit, and bits ILVL2 to ILVL0 are independent of each other. The I flag and IPL are in the FLG register. The IR bit and bits ILVL2 to ILVL0 are in the Interrupt Control Register.
11.6.1
I Flag and IPL
The I flag enables and disables maskable interrupts. When the I flag is set to 1 (enable), all maskable interrupts are enabled; when the I flag is set to 0 (disable), they are disabled. The I flag automatically becomes 0 after reset. IPL is 3 bits wide and indicates the Interrupt Priority Level (IPL) from level 0 to level 7. If a requested interrupt has higher priority level than IPL, the interrupt is acknowledged. Table 11.4 lists interrupt priority levels associated with IPL. Table 11.4
IPL2 to IPL0 0 1 2 3 4 5 6 7
Interrupt Priority Levels
Required Interrupt Priority Levels to Be Acknowledged for Maskable Interrupts Level 1 and above Level 2 and above Level 3 and above Level 4 and above Level 5 and above Level 6 and above Level 7 and above All maskable interrupts are disabled
11.6.2
Interrupt Control Registers and RLVL Register
The Interrupt Control Registers are used to control the peripheral function interrupts. Figures 11.4 and 11.5 show the Interrupt Control Registers. Figure 11.6 shows the RLVL register.
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11. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TA0IC to TA4IC TB0IC to TB5IC S0TIC to S4TIC S0RIC to S4RIC BCN0IC to BCN4IC DM0IC to DM3IC AD0IC KUPIC IIO0IC to IIO5IC IIO6IC to IIO11IC CAN0IC to CAN2IC CAN3IC to CAN5IC
Bit Symbol ILVL0
Address 006Ch, 008Ch, 006Eh, 008Eh, 0070h 0094h, 0076h, 0096h, 0078h, 0098h, 0069h 0090h, 0092h, 0089h, 008Bh, 008Dh 0072h, 0074h, 006Bh, 006Dh, 006Fh 0071h, 0091h, 008Fh, 0071h(1), 0091h(2) 0068h, 0088h, 006Ah, 008Ah 0073h 0093h 0075h, 0095h, 0077h, 0097h, 0079h, 0099h 007Bh, 009Bh, 007Dh, 009Dh, 007Fh, 0081h 009Dh, 007Fh, 0081h(3) 0075h, 0095h, 0099h(3)
Bit Name
b2 b1 b0
After Reset XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX X000b X000b X000b X000b X000b X000b X000b X000b X000b X000b X000b X000b
RW RW
Function
ILVL1
Interrupt priority level select bits
ILVL2
0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt not requested 1: Interrupt requested
RW
RW
IR
Interrupt request bit(4) Unimplemented. Write 0. Read as undefined value.
RW
- (b7-b4)
-
NOTES: 1. The BCN0IC register shares the address with the BCN3IC register. 2. The BCN1IC register shares the address with the BCN4IC register. 3. The CAN-associated registers cannot be used in M32C/87B. Only registers CAN0IC to CAN2IC can be used in M32C/87A for the CAN-associated registers. The CAN0IC register controls the CAN00 interrupt. The CAN1IC register controls the CAN01 interrupt. The CAN2IC register controls the CAN02 interrupt. The CAN3IC register controls the CAN10 interrupt. The CAN4IC register controls the CAN11 interrupt. The CAN5IC register controls the CAN12 interrupt and CAN1 wake-up interrupt. The IIO09IC register shares the address with the CAN0IC register. The IIO10IC register shares the address with the CAN1IC register. The IIO11IC register shares the address with the CAN2IC register. The IIO0IC register shares the address with the CAN3IC register. The IIO1IC register shares the address with the CAN4IC register. The IIO5IC register shares the address with the CAN5IC register. 4. The IR bit can be set to 0 only. (Do not set to 1.)
Figure 11.4
Interrupt Control Register (1/2)
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11. Interrupts
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol INT0IC to INT2IC INT3IC to INT5IC(1)
Bit Symbol ILVL0 Interrupt priority level select bits Bit Name
Address 009Eh, 007Eh, 009Ch 007Ch, 009Ah, 007Ah
Function
b2 b1 b0
After Reset XX00 X000b XX00 X000b
RW RW
ILVL1
ILVL2
0 0 0: Level 0 (interrupt disabled) 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt not requested 1: Interrupt requested 0: Falling edge / "L" level selected 1: Rising edge / "H" level selected 0 : Edge sensitive 1 : Level sensitive
RW
RW
IR
Interrupt request bit(2)
RW
POL
Polarity switch bit (3) Level sensitive/ edge sensitive switch bit (4) Unimplemented. Write 0. Read as undefined value.
RW
LVS - (b7-b6)
RW
-
NOTES: 1. When a 16-bit data bus is used in microprocessor mode and memory expansion mode, pins INT3 to INT5 are used as data bus. In this case, set bits ILVL2 to ILVL0 in registers INT3IC to INT5IC to 000b. 2. The IR bit can be set to 0 only. (Do not set to 1.) 3. Set the POL bit to 0 when its corresponding bit in the IFSR register is set to 1 (both edges). 4. When the LVS bit is set to 1, set its corresponding bit in the IFSR register to 0 (one edge).
Figure 11.5
Interrupt Control Register (2/2)
11.6.2.1
Bits ILVL2 to ILVL0
Bits ILVL2 to ILVL0 determine an interrupt priority level. The higher the interrupt priority level is, the higher priority the interrupt has. When an interrupt request is generated, its interrupt priority level is compared to IPL. This interrupt is enabled only when its interrupt priority level is higher than IPL. When bits ILVL2 to ILVL0 are set to 000b (level 0), the interrupt is disabled.
11.6.2.2
IR Bit
The IR bit is automatically set to 1 (interrupt requested) by hardware when an interrupt request is generated. After an interrupt request is acknowledged and an interrupt sequence in the corresponding interrupt vector is executed, the IR bit is automatically set to 0 (interrupt not requested) by hardware. The IR bit can be set to 0 by a program. Do not set it to 1.
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11. Interrupts
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RLVL
Bit Symbol RLVL0 Exit wait mode/stop mode interrupt priority level control bits(1) Bit Name
Address 009Fh
Function
b2 b1 b0
After Reset XXXX 0000b
RW RW
RLVL1
RLVL2
0 0 0: Level 0 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt(2)(3)
RW
RW
FSIT
High-speed interrupt select bit
RW
- (b4) DMAII - (b7-b6)
Unimplemented. Write 0. Read as undefined value. DMACII select bit (4) Unimplemented. Write 0. Read as undefined value. 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMACII transfer (2)
-
RW
-
NOTES: 1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register. 2. Do not set both the FSIT and DMAII bits to 1. Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b. 3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt. 4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt Control Register.
Figure 11.6
RLVL Register
11.6.2.3
Bits RLVL2 to RLVL0
When using an interrupt to exit wait mode or stop mode, refer to 9.5.2 Wait Mode and 9.5.3 Stop Mode for details.
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11. Interrupts
11.6.3
Interrupt Sequence
The interrupt sequence is performed between an interrupt request acknowledgment and interrupt routine execution. When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt priority after the instruction in progress is completed. Then, the CPU starts the interrupt sequence from the following cycle. However, for the SCMPU, SIN, SMOVB, SMOVF, SMOVU, SSTR, SOUT, and RMPA instructions, if an interrupt request is generated while one of these instructions is being executed, the MCU suspends the instruction execution to start the interrupt sequence. The interrupt sequence is performed as indicated below: (1) The CPU obtains the interrupt number by reading the address 000000h (address 000002h for the highspeed interrupt). Then, the corresponding IR bit to the interrupt becomes 0 (interrupt not requested). (2) The FLG register value, immediately before the interrupt sequence, is saved to a temporary register(1) in the CPU. (3) Each bit in the FLG register becomes as follows: The I flag becomes 0 (interrupt disabled) The D flag becomes 0 (single-step interrupt disabled) The U flag becomes 0 (ISP selected) (4) The internal register value (the FLG register value saved in (2)) in the CPU is saved to the stack; or to the SVF register for the high-speed interrupt. (5) The PC value is saved to the stack; or to the SVP register for the high-speed interrupt. (6) The interrupt priority level of the acknowledged interrupt becomes the IPL level. (7) An interrupt vector corresponding to the acknowledged interrupt is stored into PC. After the interrupt sequence is completed, the CPU executes the instruction from the starting address of the interrupt routine. NOTE: 1. Temporary register cannot be accessed by users.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.6.4
Interrupt Response Time
Figure 11.7 shows the interrupt response time. Interrupt response time is the period between an interrupt request generation and the end of an interrupt sequence. Interrupt response time is divided into two phases: the period between an interrupt request generation and the end of the ongoing instruction execution ((a) in Figure 11.7), and the period required to perform the interrupt sequence ((b) in Figure 11.7).
Interrupt request is generated
Interrupt request is acknowledged Time
Instruction (a)
Interrupt sequence (b)
Instruction in interrupt routine
Interrupt response time
(a) Period between an interrupt request generation and the end of instruction execution. (b) Period required to perform an interrupt sequence.
Figure 11.7
Interrupt Response Time
Time (a) varies depending on an instruction being executed. The DIV, DIVX, and DIVU instructions require the longest time (a), which is at the maximum of 42 cycles. Table 11.5 lists time (b). Table 11.5 Interrupt Sequence Execution Time(1)
Interrupts Peripheral function INT instruction NMI Watchdog timer Undefined instruction Address match Overflow BRK instruction (relocatable vector table) BRK instruction (fixed vector table) High-speed interrupt Execution Time (in terms of CPU clock) 14 cycles 12 cycles 13 cycles
14 cycles 17 cycles 19 cycles 5 cycles
NOTE: 1. The values when interrupt vectors are allocated in even addresses in the internal ROM, except for the highspeed interrupt.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.6.5
IPL Change when Interrupt Request is Acknowledged
When a peripheral function interrupt request is acknowledged, the priority level for the acknowledged interrupt becomes the IPL level in the flag register. Software interrupts and special interrupts have no interrupt priority level. If an interrupt that has no interrupt priority level occurs, the value shown in Table 11.6 becomes the IPL level. Table 11.6 Interrupts without Interrupt Priority Levels and IPL
Interrupt Source Watchdog timer, NMI, oscillation stop detection, Vdet4 detection, DMACII end-of-transfer interrupt Software, address match IPL level 7 Not changed
11.6.6
Saving a Register
In the interrupt sequence, values of the FLG register and PC are saved to the stack. Figure 11.8 shows the stack states before and after an interrupt request is acknowledged. The other necessary registers are saved by a program at the beginning of the interrupt routine. The PUSHM instruction can save multiple registers(1) in the register bank currently used. Refer to 11.4 High-Speed Interrupt for the high-speed interrupt. NOTE: 1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.
Address
Address
MSB
Stack
LSB
MSB
Stack
LSB
[SP] New SP value
m-6 m-5 m-4 m-3 m-2 m-1 m m+1 Previous stack contents Previous stack contents
m-6 m-5 m-4 m-3 m-2 m-1 m m+1
PCL PCM PCH 00h FLGL FLGH Previous stack contents Previous stack contents
[SP] SP value before an interrupt is generated
PCL: 8 low-order bits of PC PCM: 8 middle-order bits of PC PCH: 8 high-order bits of PC FLGL: 8 low-order bits of FLG FLGH: 8 high-order bits of FLG
Stack state before an interrupt request is acknowledged
Stack state before an interrupt request is acknowledged
Figure 11.8
Stack States Before and After Acknowledgement of Interrupt Request
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.6.7
Returning from Interrupt Routine
When the REIT instruction is executed at the end of an interrupt routine, the values of the FLG register and PC, which have been saved to the stack before the interrupt sequence is performed, are automatically restored. And then, the program that was running before an interrupt request was acknowledged, resumes its process. The high-speed interrupt uses the FREIT instruction instead. Refer to 11.4 High-Speed Interrupt for details. Before executing the REIT or FREIT instruction, use the POPM instruction or the like to restore registers saved by a program in the interrupt routine. By executing the REIT or FREIT instruction, register bank is switched back to the bank used immediately before the interrupt sequence.
11.6.8
Interrupt Priority
If two or more interrupt requests are detected at the same sampling points (a timing to check whether any interrupt request is generated or not), the interrupt with the highest priority is acknowledged. Set bits ILVL2 to ILVL0 in the Interrupt Control Register to select the given priority level for maskable interrupts (peripheral function interrupts). Priority levels of special interrupts, such as NMI and watchdog timer interrupt are fixed by hardware. Figure 11.9 shows the priority of hardware interrupts. The interrupt priority does not affect software interrupts. Executing an instruction for a software interrupt causes the MCU to execute an interrupt routine.
NMI Watchdog timer Oscillation stop detection Vdet4 detection Peripheral function Address match
H
L
Figure 11.9
Interrupt Priority of Hardware Interrupts
11.6.9
Interrupt Priority Level Decision Circuit
The interrupt priority level decision circuit selects the highest priority interrupt when two or more interrupt requests are generated at the same sampling point. Figure 11.10 shows the interrupt priority level decision circuit.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
High
Interrupt priority level
Level 0 (initial value)
DMA0 DMA1 DMA2 DMA3 Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 UART0 transmission/NACK UART0 reception/ACK UART1 transmission/NACK UART1 reception/ACK Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 INT5 INT4 INT3 INT2 INT1 INT0 Timer B5 UART2 transmission/NACK UART2 reception/ACK UART3 transmission/NACK UART3 reception/ACK UART4 transmission/NACK UART4 reception/ACK Bus conflict/ start or stop condition detection (UART2) I flag Address match Watchdog timer, oscillation stop detection, Vdet4 detection NMI DMACII
Interrupt request acknowledged (to CPU)
Interrupt priority level
Bus conflict/ start or stop condition detection (UART0, UART3) Bus conflict/ start or stop condition detection (UART1, UART4) A/D0 Key input interrupt Intelligent I/O interrupt 0/ CAN10/UART5 reception Intelligent I/O interrupt 1/ CAN11/UART5 transmission Intelligent I/O interrupt 2 Intelligent I/O interrupt 3 Intelligent I/O interrupt 4 Intelligent I/O interrupt 5/ CAN12/CAN1 wake-up Intelligent I/O interrupt 6 Intelligent I/O interrupt 7 Intelligent I/O interrupt 8 Intelligent I/O interrupt 9/ CAN00/UART6 reception/INT6 Intelligent I/O interrupt 10/ CAN01/UART6 transmission/ INT7 Intelligent I/O interrupt 11/ CAN02/INT8
Bits RLVL2 to RLVL0
Interrupt priority level decision output (to the clock generation circuit)
IPL
Low
Peripheral function interrupt priority (if priority levels are the same)
Figure 11.10
Interrupt Priority Level Decision Circuit
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.7
INT Interrupt
External input to pins INT0 to INT8 generates the INT0 to INT8 interrupt. INT0 to INT5 interrupts can select either edge sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input signal level to the INTi pin (i = 0 to 5) triggers an interrupt request. The INT6 to INT8 interrupts are available only in the 144-pin package with edge-sensitive triggering. To use INT0 to INT5 interrupts with edge sensitive, set the LVS bit in the INTiIC register to 0 (edge sensitive), and select a rising edge, falling edge, or both edges using the POL bit in the INTiIC register and the IFSRi bit in the IFSR register. When the IFSRi bit is set to 1 (both edges), set the corresponding POL bit to 0 (falling edge). When the selected edge is detected at the INTi pin, the corresponding IR bit becomes 1. To use INT0 to INT5 interrupts with level sensitive, set the LVS bit to 1 (level sensitive) and select either "L" level or "H" level using the POL bit. Also, set the IFSRi bit to 0 (one edge). While the selected level is detected at the INTi pin, the IR bit becomes 1 and remains 1. Therefore, the interrupt requests are generated repeatedly as long as the selected level is detected at the INTi pin. When the input signal is changed to the inactive level, the IR bit becomes 0 by the interrupt request acknowledgement or writing a 0 by a program. Interrupts can be enabled or disabled using bits ILVL2 to ILVL0 in the INTiIC register. To use INT6 to INT8 interrupts with edge sensitive, select a rising edge or falling edge by the IFSRj bit (j = 10 to 12) in the IFSRA register. Interrupts can be enabled or disabled using the INTiE bit in the IIOkIE register (k = 9 to 11) and bits ILVL2 to ILVL0 in the IIOkIC register. Refer to 11.11 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/Receive Interrupts, and INT6 to INT8 Interrupts for details. Figure 11.11 shows INTi interrupt setting procedures (i = 0 to 5). Figure 11.12 shows INTi interrupt setting procedures (i = 6 to 8). Figure 11.13 shows the IFSR register and Figure 11.14 shows IFSRA register.
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11. Interrupts
< Procedure for Edge Sensitive >
Start INTiIC register: bits ILVL2 to ILVL0 = 000b IFSR register: IFSRi bit INTiIC register: POL bit LVS bit = 0 INTiIC register: IR bit = 0 INTiIC register: bits ILVL2 to ILVL0 End Interrupt disabled Select either one edge or both edges Select polarity (Set to 0 when both edges are selected) Select edge sensitive Clear the interrupt request bit Interrupt enabled
< Procedure for Level Sensitive >
Start INTiIC register: bits ILVL2 to ILVL0 = 000b IFSR register: IFSRi bit = 0 INTiIC register: POL bit LVS bit = 1 INTiIC register: IR bit = 0 INTiIC register: bits ILVL2 to ILVL0 End Interrupt disabled Select one edge Select polarity Select level sensitive Clear the interrupt request bit Interrupt enabled i = 0 to 5
Figure 11.11
INTi Interrupt Setting Procedures (i = 0 to 5)
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11. Interrupts
Start IIOjIE register: INTiE bit = 0 IFSRA register: IFSRk bit IIOjIR register: INTiR bit = 0 IIOjIE register: INTiE bit = 1 End Interrupt disabled Select polarity Clear the IR bit Interrupt enabled j = 9, k = 10, when i = 6 j = 10, k = 11, when i = 7 j = 11, k = 12, when i = 8
Figure 11.12
INTi Interrupt Setting Procedures (i = 6 to 8)
External Interrupt Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR
Bit Symbol IFSR0 Bit Name INT0 interrupt polarity select bit(1) INT1 interrupt polarity select bit(1) INT2 interrupt polarity select bit(1) INT3 interrupt polarity select bit(1) INT4 interrupt polarity select bit(1) INT5 interrupt polarity select bit(1) UART0, UART3 interrupt source select bit
Address 031Fh
Function 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges
After Reset 00h
RW RW
IFSR1
RW
IFSR2
RW
IFSR3
RW
IFSR4
RW
IFSR5
RW
IFSR6
0: UART3 bus conflict, start condition detection, stop condition detection 1: UART0 bus conflict, start condition detection, stop condition detection 0: UART4 bus conflict, start condition detection, stop condition detection 1: UART1 bus conflict, start condition detection, stop condition detection
RW
IFSR7
UART1, UART4 interrupt source select bit
RW
NOTE: 1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the corresponding INTilC register to 0 (falling edge).
Figure 11.13
IFSR Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
External Interrupt Source Select Register1(1)
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol IFSRA
Bit Symbol IFSR10 Bit Name INT6 interrupt polarity select bit INT7 interrupt polarity select bit INT8 interrupt polarity select bit Reserved bits
Address 031Eh
Function 0: One edge (falling edge) 1: One edge (rising edge) 0: One edge (falling edge) 1: One edge (rising edge) 0: One edge (falling edge) 1: One edge (rising edge) Set to 0
After Reset 00h
RW RW
IFSR11
RW
IFSR12 - (b7-b3)
RW
RW
NOTE: 1. The IFSRA register is available in the 144-pin package only.
Figure 11.14
IFSRA Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.8
NMI Interrupt
The NMI interrupt is non-maskable. The NMI interrupt occurs when a signal applied to the P8_5/NMI pin changes from "H" level to "L" level. A read from the P8_5 bit in the P8 register returns the input level of the NMI pin. When the NMI interrupt is not used, connect the NMI pin to VCC1 via a resistor (pull-up). Each "H" or "L" width of the signal applied to the NMI pin must be 2 CPU clock cycles + 300 ns or more.
11.9
Key Input Interrupt
The IR bit in the KUPIC register becomes 1 when an falling edge is detected at any of the pins P10_4 to P10_7 set to input mode. The key input interrupt can also be used as key-on wake-up function to exit wait mode or stop mode. To use the key input interrupt, do not use pins P10_4 to P10_7 as A/D input. Figure 11.15 shows a block diagram of the key input interrupt. When an "L" signal is applied to one of the pins P10_4 to P10_7 in input mode, a falling edge detected at the other pins is not recognized as an interrupt request signal. When the PSC_7 bit in the PSC register is set to 1 (AN_4 to AN_7), the input buffer for the port and the key input interrupt is disconnected. Therefore, the pin level cannot be obtained by reading the Port P10 register in input mode. Also, the IR bit in the KUPIC register does not become 1 even if a falling edge is detected at pins KI0 to KI3.
PU31 bit Pull-up transistor PSC_7 bit P10_7/KI3 Pull-up transistor P10_6/KI2 Pull-up transistor P10_5/KI1 Pull-up transistor P10_4/KI0 PD10_4 bit PD10_4 to PD10_7: Bits in the PD10 register PSC_7: Bit in the PSC register PU31: Bit in the PUR3 register PD10_6 bit PD10_7 bit PD10_7 bit
Key input interrupt request
PD10_5 bit
Figure 11.15
Key Input Interrupt Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.10 Address Match Interrupt
The address match interrupt is non-maskable. This interrupt occurs immediately before executing the instruction stored in the address specified by the RMADi register (i=0 to 7). Eight addresses can be set for the address match interrupt. The AIERi bit in the AIER register determines whether the interrupt is enabled or disabled. Figure 11.16 shows registers associated with the address match interrupt. Set the starting address of the instruction in the RMADi register. The address match interrupt does not occur if a table data or any address other than the starting address of the instruction is set.
Address Match Interrupt Register i (i = 0 to 7)
b23 b16 b15 b8 b7 b0
Symbol RMAD0 RMAD1 RMAD2 RMAD3 RMAD4 RMAD5 RMAD6 RMAD7
Function
Address 0012h to 0010h 0016h to 0014h 001Ah to 0018h 001Eh to 001Ch 002Ah to 0028h 002Eh to 002Ch 003Ah to 0038h 003Eh to 003Ch
After Reset 000000h 000000h 000000h 000000h 000000h 000000h 000000h 000000h
Setting Range 000000h to FFFFFFh RW RW
Address register for the address match interrupt
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER
Bit Symbol AIER0 Bit Name
Address 0009h
Function 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled 0: interrupt disabled 1: interrupt enabled
After Reset 00h
RW RW
Address match interrupt 0 enable bit Address match interrupt 1 enable bit Address match interrupt 2 enable bit Address match interrupt 3 enable bit Address match interrupt 4 enable bit Address match interrupt 5 enable bit Address match interrupt 6 enable bit Address match interrupt 7 enable bit
AIER1
RW
AIER2
RW
AIER3
RW
AIER4
RW
AIER5
RW
AIER6
RW
AIER7
RW
Figure 11.16
RMAD0 to RMAD7 Registers, AIER Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
11.11 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/ Receive Interrupts, and INT6 to INT8 Interrupts
The intelligent I/O interrupts are shared by CAN interrupt, INT6 to INT8 interrupts, UART5 and UART6 transmit/ receive interrupt. A logical sum of interrupt request signals from individual peripheral functions is used to generate an interrupt. Figure 11.17 shows a block diagram of the intelligent I/O interrupts. Figure 11.18 shows the IIOiIR (i = 0 to 11) register. Figure 11.19 shows the IIOiIE register.
IIOiIR register(1) Interrupt request signal "0" write signal to bit 1 Interrupt request signal "0" write signal to bit2
0 SQ R 1
IR bit in the IIOiIC (CANjIC) register
DQ R
bit 1
0 SQ R 1
To the interrupt priority level decision circuit IR bit is cleared to 0 by an interrupt request acknowledgement or by writing a 0 to the IR bit.
bit 2
When this signal changes from 0 to 1, the IR bit in the IIOiIC (CANjIC) register becomes 1. Interrupt request signal "0" write signal to bit7
0 SQ R 1
bit 7
IIOiIE register(2) IRLT bit 1 bit 2
bit 7
i = 0 to 11, j = 0 to 5 NOTES: 1. Bits 1 to 7 in the IIOiIR register do not automatically become 0 when the interrupt request is acknowledged. Set to 0 by a program. 2. Do not change the interrupt enable bit (bits 1 to 7 in the IIOiIE register) and IRLT bit in the IIOiIE register simultaneously.
Figure 11.17
Intelligent I/O Interrupt Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
Interrupt Request Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IIO0IR to IIO11IR
Bit Symbol - (b0) (Note 1)
Address See below
Function Unimplemented. Write 0. Read as undefined value. Interrupt request flag 1 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2)
After Reset 0000 000Xb
RW -
RW
(Note 1)
Interrupt request flag 2
RW
(Note 1)
Interrupt request flag 3
RW
(Note 1)
Interrupt request flag 4
RW
(Note 1)
Interrupt request flag 5
RW
(Note 1)
Interrupt request flag 6
RW
(Note 1)
Interrupt request flag 7
RW
NOTES: 1. See table below for bit symbols. 2. These bits can be set to only 0. Do not write a 1 to these bits.
Bit Symbols for the Interrupt Request Register
Symbol IIO0IR IIO1IR IIO2IR IIO3IR IIO4IR IIO5IR IIO6IR IIO7IR IIO8IR IIO9IR IIO10IR IIO11IR Address 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh Bit 7 CAN10R CAN11R - - SRT0R CAN12R - IE0R IE1R CAN00R CAN01R CAN02R Bit 6 U5RR U5TR - - SRT1R CAN1WUR - - IE2R INT6R INT7R INT8R Bit 5 SIO0RR SIO0TR SIO1RR SIO1TR - - - - - U6RR U6TR - Bit 4 G0RIR G0TOR G1RIR G1TOR BT1R SIO2RR SIO2TR - BT2R - - - Bit 3 - - - PO27R - - - - - - - - Bit 2 TM13R/PO13R TM14R/PO14R TM12R/PO12R TM10R/PO10R TM17R/PO17R PO21R PO20R PO22R PO23R PO24R PO25R PO26R Bit 1 - - - - - - - - TM11R/PO11R TM15R/PO15R TM16R/PO16R - Bit 0 - - - - - - - - - - - -
BTqR: Intelligent I/O group q base timer interrupt request TM1jR: Intelligent I/O group 1 time measurement function j interrupt request POqjR: Intelligent I/O group q waveform generation function j interrupt request SIOkRR: Intelligent I/O group k receive interrupt request SIOkTR: Intelligent I/O group k transmit interrupt request GmTOR: Intelligent I/O group m HDLC data processing function interrupt request (TO: Transmit Output) GmRIR: Intelligent I/O group m HDLC data processing function interrupt request (RI: Receive Input) SRTmR: Intelligent I/O group m special communication function interrupt request IEkR: Intelligent I/O group 2 IEBus communication function interrupt request CAN0kR: CAN0 communication function interrupt request CAN1kR: CAN1 communication function interrupt request CAN1WUR: CAN1 wake-up interrupt request INTnR: INTn interrupt request UpTR: UARTp transmit interrupt request UpRR: UARTp receive interrupt request -: Reserved bit. Set to 0
j = 0 to 7 k = 0 to 2 m = 0, 1 n = 6 to 8 p = 5, 6 q = 1, 2
Figure 11.18
IIO0IR to IIO11IR Registers
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11. Interrupts
Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IIO0IE to IIO11E
Bit Symbol IRLT Bit Name
Address See below
Function
After Reset 00h
RW RW
Interrupt request select bit (2)
0: Uses an interrupt request for DMA, DMA II 1: Uses an interrupt request for interrupt 0: Disables an interrupt set by bit 1 in the IIOiIR register 1: Enables an interrupt set by bit 1 in the IIOiIR register 0: Disables an interrupt set by bit 2 in the IIOiIR register 1: Enables an interrupt set by bit 2 in the IIOiIR register 0: Disables an interrupt set by bit 3 in the IIOiIR register 1: Enables an interrupt set by bit 3 in the IIOiIR register 0: Disables an interrupt set by bit 4 in the IIOiIR register 1: Enables an interrupt set by bit 4 in the IIOiIR register 0: Disables an interrupt set by bit 5 in the IIOiIR register 1: Enables an interrupt set by bit 5 in the IIOiIR register 0: Disables an interrupt set by bit 6 in the IIOiIR register 1: Enables an interrupt set by bit 6 in the IIOiIR register 0: Disables an interrupt set by bit 7 in the IIOiIR register 1: Enables an interrupt set by bit 7 in the IIOiIR register
(Note 1)
Interrupt enabled bit 1
RW
(Note 1)
Interrupt enabled bit 2
RW
(Note 1)
Interrupt enabled bit 3
RW
(Note 1)
Interrupt enabled bit 4
RW
(Note 1)
Interrupt enabled bit 5
RW
(Note 1)
Interrupt enabled bit 6
RW
(Note 1)
Interrupt enabled bit 7
RW
NOTES: 1. See table below for bit symbols. 2. To use an interrupt request for interrupt, set the interrupt enabled bit r (r = 1 to 7) to 1 after setting the IRLT bit to 1.
Bit Symbols for the Interrupt Enable Register
Symbol IIO0IE IIO1IE IIO2IE IIO3IE IIO4IE IIO5IE IIO6IE IIO7IE IIO8IE IIO9IE IIO10IE IIO11IE Address 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh Bit 7 CAN10E CAN11E - - SRT0E CAN12E - IE0E IE1E CAN00E CAN01E CAN02E Bit 6 U5RE U5TE - - SRT1E CAN1WUE - - IE2E INT6E INT7E INT8E Bit 5 SIO0RE SIO0TE SIO1RE SIO1TE - - - - - U6RE U6TE - Bit 4 G0RIE G0TOE G1RIE G1TOE BT1E SIO2RE SIO2TE - BT2E - - - Bit 3 - - - PO27E - - - - - - - - Bit 2 TM13E/PO13E TM14E/PO14E TM12E/PO12E TM10E/PO10E TM17E/PO17E PO21E PO20E PO22E PO23E PO24E PO25E PO26E Bit 1 - - - - - - - - TM11E/PO11E TM15E/PO15E TM16E/PO16E - Bit 0 IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT IRLT
BTqE: Intelligent I/O group q base timer interrupt enabled TM1jE: Intelligent I/O group 1 time measurement function j interrupt enabled POqjE: Intelligent I/O group q waveform generation function j interrupt enabled SIOkRE: Intelligent I/O group k receive interrupt enabled SIOkTE: Intelligent I/O group k transmit interrupt enabled GmTOE: Intelligent I/O group m HDLC data processing function interrupt enabled (TO: Transmit Output) GmRIE: Intelligent I/O group m HDLC data processing function interrupt enabled (RI: Receive Input) SRTmE: Intelligent I/O group m special communication function interrupt enabled IEkE: Intelligent I/O group 2 IEBus communication function interrupt enabled CAN0kE: CAN0 communication function interrupt enabled CAN1kE: CAN1 communication function interrupt enabled CAN1WUE: CAN1 wake-up interrupt enabled INTnE: INTn interrupt enabled UpTE: UARTp transmit interrupt enabled UpRE: UARTp receive interrupt enabled -: Reserved bit. Set to 0
i = 1 to 11 j = 0 to 7 k = 0 to 2 m = 0, 1 n = 6 to 8 p = 5, 6 q = 1, 2
Figure 11.19
IO0IE to IIO11IE Registers
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11. Interrupts
To configure for intelligent I/O interrupts, use IIOiIE register (i = 0 to 11), IIOiIR register, and IIOiIC (CANjIC (j = 0 to 5)) register.
11.11.1 IIOiIE Register
* IRLT bit
Set to 1 to use interrupt requests from individual peripheral functions for interrupts. Set to 0 to use them for DMA or DMACII trigger sources. * Interrupt enable bit Set the interrupt enable bit corresponding to the interrupt to be used, to 1 (interrupt enabled) after setting the IRLT bit.
11.11.2 IIOiIR Register
* Interrupt request flag
The interrupt request flag becomes 1 (interrupt requested) when an interrupt request is generated. This flag does not automatically become 0 when the interrupt request is acknowledged. Use AND or BCLR instruction to set it to 0 (interrupt not requested) in the interrupt routine. If any of these flags remains 1, the IR bit in the IIOiIC (CANjIC) register does not become 1 when an interrupt request is generated in the same register. (Interrupt does not occur.) If an interrupt request is generated while writing a 0 to the corresponding interrupt flag, the flag may not be cleared to 0. In this case, keep writing a 0 until 0 is read.
11.11.3 IIOiIC (CANjIC) Register
* IR bit
The IR bit in the IIOiIC register becomes 1 (interrupt requested), if all the enabled request flags in the corresponding IIOiIR register are set to 0, and an interrupt request corresponding to one of these flags is generated. The IR bit automatically becomes 0 when the interrupt is acknowledged. Table 11.7 lists registers used for CAN interrupts, UART5 and UART6 transmit/receive interrupts, and INT6 to INT8 interrupts. Figure 11.20 shows an interrupt request bit timing with multiple interrupt sources. Figure 11.21 shows an interrupt routine example. Table 11.7 Registers Used for CAN interrupts, UART5 and UART6 transmit/receive interrupts, and INT6 to INT8 interrupts
UART Transmit/receive UART6 receive UART6 transmit - UART5 receive UART5 transmit - Registers to be Used(2) IIO9IE IIO10IE IIO11IE IIO0IE IIO1IE IIO5IE IIO9IR IIO10IR IIO11IR IIO0IR IIO1IR IIO5IR IIO9IC (CAN0IC) IIO10IC (CAN1IC) IIO11IC (CAN2IC) IIO0IC (CAN3IC) IIO1IC (CAN4IC) IIO5IC (CAN5IC)
Interrupts shared with Intelligent I/O Interrupt CAN Interrupt(1) CAN00 CAN01 CAN02 CAN10 CAN11 CAN12 CAN1 Wake-up INT Interrupt INT6 INT7 INT8 - - -
NOTES: 1. Only CAN00 to CAN02 interrupts can be used in M32C/87A. No CAN interrupt is provided in M32C/87B. 2. The IIO9IC register and the CAN0IC register share the same address. So do the IIO10IC register and CAN1IC register, the IIO11IC register and the CAN2IC register, the IIO0IC register and the CAN3IC register, the IIO1IC register and the CAN4IC register, and the IIO5IC register and the CAN5IC register.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
Interrupt request A from peripheral function A Interrupt request B from peripheral function B Interrupt request flag (1) corresponding to interrupt request A Interrupt request corresponding to interrupt request B Intelligent I/O i interrupt request IR bit in the IIOiIC (CANkIC) register flag (1)
"H" "L" "H" "L" 1 0 1 0 "H" "L" 1 0 When all the enabled interrupt request flags are set to 0, the intelligent I/O i interrupt request becomes "L". The IR bit automatically becomes 0 when the interrupt request is acknowledged. Set to 0 by a program
i = 0 to 11, k = 0 to 5
NOTE: 1. These interrupt request flags are assigned to the same IIOiIR register and both flags are enabled in the IIOiIE register.
Figure 11.20
Interrupt Request Bit Timing with Multiple Interrupt Sources
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
11. Interrupts
Example: Intelligent I/O Group 1 Waveform Generation Function 1 Interrupt, Group 2 Waveform Generation Function 3 Interrupt are used.
IIO8IR register = 00h IIO8IE register: IRLT bit = 1 IIO8IE register: PO11E bit = 1 PO23E bit = 1 bits 7 to 3 = 00000b IIO8IC register: bits ILVL2 to ILVL0 IR bit = 0 I flag = 1 Initialize the Interrupt Request Register Uses an interrupt request for interrupts Enable intelligent I/O group 1 waveform generation function 1 interrupt Enable intelligent I/O group 2 waveform generation function 3 interrupt Disable unused interrupts Interrupt priority level select bits Interrupt not requested Interrupt enabled (note 1)
Interrupt routine
NO
IIO8IR register: PO11R bit = 1 ? YES IIO8IR register: PO11R bit = 0 Interrupt processing of PO11 Set to 0 (interrupt not requested) using AND or BCLR instruction (2)
NO
IIO8IR register: PO23R bit = 1 ? YES IIO8IR register: PO23R bit = 0 Interrupt processing of PO23 Set to 0 (interrupt not requested) using AND or BCLR instruction (2)
NO
IIO8IR register & 06h = 0 ? YES
(note 3)
End
NOTES: 1. Do not change the interrupt enable bit (bits 1 to 7 in the IIOiIE register (i = 0 to 11)) and the IRLT bit in the IIOiIE register simultaneously. Set the IRLT bit to 1 first, and then set the interrupt enable bit to 1. 2. If an interrupt request is generated while writing a 0 to the corresponding interrupt request flag, the flag may not be cleared to 0. In this case, keep writing a 0 until 0 is read. 3. Ensure that all the enabled interrupt request flags are set to 0. If any of these flags remains 1, the IR bit in the IIOiIC (CANkIC (k = 0 to 5)) register does not become 1 when an interrupt request is generated in the same register. (Interrupt does not occur.)
Figure 11.21
Interrupt Routine Example
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
12. Watchdog Timer
12. Watchdog Timer
The watchdog timer is used to detect the program running improperly. The watchdog timer contains a 15-bit freerunning counter. If a write to the WDTS register is not performed due to a program running out of control, the freerunning counter underflows, which results in the watchdog timer interrupt generation or the MCU reset. When operating the watchdog timer, write to the WDTS register in a shorter cycle than the watchdog timer cycle in such as the main routine. Tables 12.1 and 12.2 list specifications of the watchdog timer. Figure 12.1 shows a block diagram of the watchdog timer. Figures 12.2 and 12.3 show registers associated with the watchdog timer. Table 12.1 Watchdog Timer Specifications (1/2)
Item Count operation Count start condition Specification The free-running counter decrements Writing to the WDTS register: A write to the WDTS register initializes a free-running counter and the counter decrements from 7FFFh One of the following occurs (selectable using the CM06 bit in the CM0 register): * Watchdog timer interrupt generation(1) * MCU reset The counter continues decrementing (when the watchdog timer interrupt is selected) A read from bit 4 to bit 0 in the WDC register returns bit 14 to bit 10 of the free-running counter
When underflows
After underflows Read from watchdog timer
NOTE: 1. The watchdog timer shares the same vector with the oscillation stop detection interrupt and Vdet4 detection interrupt. When using the watchdog timer interrupt simultaneously with these interrupts, determine whether the watchdog timer interrupt is generated by reading the D43 bit in the D4INT register in the interrupt routine.
Table 12.2
Watchdog Timer Specifications (2/2)
Item Bit Setting and Specification 0 0 0 0 0 1 CPU clock Clock divided by MCD register Sub clock Divide-by-2 1 x2 fCPU 1 x 65536 fCPU Approx. 2 s fCPU = 32 kHz Divide-by-16 1 x 16 fCPU 1 x 524288 fCPU Approx. 16.4 ms fCPU = 32 MHz Divide-by-128 1 fCPU x 128 1 fCPU x 4194304 Approx. 131.1 ms fCPU = 32 MHz Stops 0 1 0 or 1 1 0 or 1 0 or 1 On-chip oscillator not available 1 fROC 1 fROC x 32768 Approx. 32.8 ms fROC = 1 MHz Operates(3)
PM22 bit in PM2 register(1) CM07 bit in CM0 register WDC7 bit in WDC register Clock source Prescaler Count source for counter Time-out period (formula)(2) Time-out period (reference) Operation in wait mode, stop mode, and hold state
fCPU: CPU clock frequency fROC: On-chip oscillator clock frequency NOTES: 1. Once the PM22 bit is set to 1, it cannot be set to 0 by a program. 2. Difference between the calculation result and actual period can be one count source cycle of the counter. 3. A write to the CM10 bit in the CM1 register is disabled. Writing a 1 has no effect and the MCU does not enter stop mode. The watchdog timer interrupt cannot be used to exit wait mode.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
12. Watchdog Timer
Prescaler 1/16
CPU clock Wait mode signal HOLD
1/128 1/2
CM07=0 WDC7=0 CM07=0 WDC7=1 CM07=1
PM22 0 1 Watchdog timer
CM06
0
Watchdog timer interrupt signal
1 Set to 7FFFh
Reset
On-chip oscillator clock Write signal to the WDTS register Internal reset signal
Vdet4 detection interrupt signal Oscillation stop detection interrupt signal Watchdog timer interrupt request (non-maskable)
D43 CM06, CM07: bits in the CM0 register WDC7: bit in the WDC register PM22: bit in the PM2 register D43: bit in the D4INT register
Figure 12.1
Watchdog Timer Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
12. Watchdog Timer
System Clock Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0
Bit Symbol CM00 Bit Name
Address 0006h
Function
b1 b0
After Reset 0000 1000b
RW RW
Clock output function select bits (2) CM01 Peripheral function clock stop in wait mode bit(9) XCIN-XCOUT drive capability select bit(10) Port XC switch bit Main clock (XIN-XOUT) stop bit(5, 9) Watchdog timer function select bit
0 0: I/O port P5_3(2) 0 1: Outputs fC 1 0: Outputs f8 1 1: Outputs f32 0: Peripheral clocks do not stop in wait mode 1: Peripheral clocks stop in wait mode (3) 0: Low 1: High 0: I/O port function 1: XCIN-XCOUT oscillation function (4) 0: Main clock oscillates 1: Main clock stops (6) 0: Watchdog timer interrupt 1: Reset(7) 0: Clock selected by the CM21 bit divided by the MCD register 1: Sub clock
RW
CM02
RW
CM03
RW
CM04
RW
CM05
RW
CM06
RW
CM07
CPU clock select bit 0 (8, 9)
RW
NOTES: 1. Set the CM0 register after the PRC0 bit in the PRCR register is set to 1 (write enable). 2. The BCLK, ALE, or "L" signal is output from the P5_3 in memory expansion mode or microprocessor mode. Port P5_3 does not function as an I/O port. 3. fC32 does not stop running. 4. To set the CM04 bit to 1, set bits PD8_7 and PD8_6 in the PD8 register to 00b (ports P8_6 and P8_7 in input mode) and the PU25 bit in the PUR2 register to 0 (not pulled up). 5. The CM05 bit stops the main clock oscillation when entering low-power consumption mode or on-chip oscillator low-power consumption mode. The CM05 bit cannot be used to determine whether the main clock stops or not. To stop the main clock oscillation, set the PLC07 bit in the PLC0 register to 0 and the CM05 bit to 1 after setting the CM07 bit to 1 or setting the CM21 bit in the CM2 register to 1 (on-chip oscillator clock). When the CM05 bit is set to 1, the XOUT pin outputs "H". Since an on-chip feedback resistor remains ON, the XIN pin is pulled up to the XOUT pin via the feedback resistor. 6. When the CM05 bit is set to 1, bits MCD4 to MCD0 in the MCD register become 01000b (divide-by-8 mode). In on-chip oscillator mode, bits MCD4 to MCD0 do not become 01000b even if the CM05 bit is set to 1. 7. Once the CM06 bit is set to 1, it cannot be set to 0 by a program. 8. Change the CM07 bit setting from 0 to 1, after the CM04 bit is set to 1 and the sub clock oscillation stabilizes. Change the CM07 bit setting from 1 to 0, after the CM05 bit is set to 0 and the main clock oscillation stabilizes. Do not change the CM07 bit simultaneously with the CM04 or CM05 bit. 9. If the PM21 bit in the PM2 register is set to 1 (disables a clock change), a write to bits CM02, CM05, and CM07 has no effect. 10. When stop mode is entered, the CM03 bit becomes 1.
Figure 12.2
CM0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
12. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol WDC
Bit Symbol - (b4-b0) WDC5 - (b6) WDC7 Bit Name
Address 000Fh
Function
After Reset 00XX XXXXb
RW RO 0: Cold start 1: Warm start Set to 0 0: Divide-by-16 1: Divide-by-128
High-order bits of watchdog timer Cold start/warm start determine flag(1) Reserved bit
RW
RW
Prescaler select bit
RW
NOTES: 1. The WDC5 bit is 0 after power-on. It can be set to 1 only by a program. The bit becomes 1 by writing either a 0 or 1. The bit maintains a value set before reset, even after reset has been performed.
Watchdog Timer Start Register
b7 b0
Symbol WDTS
Address 000Eh
Function
Address Undefined
RW WO
The counter is initialized and starts decrementing by a write instruction to the WDTS register. 7FFFh is the default value after initialization no matter what value is written.
Figure 12.3
WDC Register, WDTS Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
13. DMAC
DMAC allows data to be sent to and from memory without involving the CPU. The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has four DMAC channels. DMAC transfers an 8- or 16-bit data from a source address to a destination address for each transfer request. DMA0 and DMA1 must be prioritized when using DMAC. DMA2 and DMA3 share the registers with the high-speed interrupts. The high-speed interrupts cannot be used when three or more DMAC channels are used. The CPU and DMAC use the same data bus, but DMAC has a higher bus access privilege than the CPU. DMAC employing the cycle-steal method enables a high-speed operation from a transfer request to a completion of 16-bit (word) or 8-bit (byte) data transfer. Figure 13.1 shows a mapping of DMAC-associated registers. Table 13.1 lists specifications of DMAC. Figures 13.2 to 13.6 show DMAC-associated registers. Figures 13.7 and 13.8 show register settings. Because the registers shown in Figure 13.1 are allocated in the CPU, use the LDC instruction to set the registers. To set registers DCT2, DCT3, DRC2, DRC3, DMA2, and DMA3, set the B flag to 1 (register bank 1) and write to registers R0 to R3, A0, and A1 with the MOV instruction. To set registers DSA2 and DSA3, set the B flag to 1 and write to registers SB and FB with the LDC instruction. To set registers DRA2 and DRA3, write to registers SVP and VCT with the LDC instruction.
DMAC-Associated Registers
DMD0 DMD1 DCT0 DCT1 DRC0 DRC1 DMA0 DMA1 DSA0 DSA1 DRA0 DRA1 DMA mode register 0 DMA mode register 1 DMA0 transfer count register DMA1 transfer count register DMA0 transfer count reload register (1) DMA1 transfer count reload register (1) DMA0 memory address register DMA1 memory address register DMA0 SFR Address register DMA1 SFR Address register DMA0 memory address reload register (1) DMA1 memory address reload register (1)
When three or more DMAC channels are used, the register bank 1 is employed as DMAC registers.
When three or more DMAC channels are used, the high-speed interrupt registers are employed as DMAC registers.
SVF DRA2(SVP) DRA3(VCT) Flag save register DMA2 memory address reload register (1) DMA3 memory address reload register (1)
DCT2(R0) DCT3(R1) DRC2(R2) DRC3(R3) DMA2(A0) DMA3(A1) DSA2(SB) DSA3(FB)
DMA2 transfer count register DMA3 transfer count register DMA2 transfer count reload register (1) DMA3 transfer count reload register DMA2 memory address register DMA3 memory address register DMA2 SFR Address register DMA3 SFR Address register
(1)
When using DMA2 and DMA3, use the CPU registers shown in parentheses ( ).
NOTE: 1. These registers are used for repeat transfer, not for single transfer.
Figure 13.1
Register Mapping for DMAC
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
A software trigger or an interrupt request generated by individual peripheral functions can be the DMA transfer request source. Bits DSEL 4 to DSEL0 in the DMiSL register determine which source is selected. When a software trigger is selected, a DMA transfer is started by setting the DSR bit in the DMiSL register to 1. When a peripheral function interrupt request is selected, a DMA transfer is started by an interrupt request generation. The DMA transfer is performed even if interrupts are disabled by the I flag, IPL, or Interrupt Control Register, since DMAC is free from these affects. When an interrupt request (DMA request) is generated, the IR bit in the Interrupt Control Register becomes 1. The IR bit, however, does not become 0 even if the DMA transfer is performed. Table 13.1 DMAC Specifications
Item Number of Channels Transfer memory space Maximum bytes transferred DMA request source 4 channels (cycle-steal method) * From a given address in a 16-Mbyte space to a fixed address in a 16-Mbyte space * From a fixed address in a 16-Mbyte space to a given address in a 16-Mbyte space 128 Kbytes (when a 16-bit data is transferred) 64 Kbytes (when an 8-bit data is transferred) * Falling edge or both edges of signals applied to pins INT0 to INT3 * INT6 to INT8 interrupt requests * Timer A0 to A4 interrupt requests * Timer B0 to B5 interrupt requests * UART0 to UART6 transmit/receive interrupt requests * A/D0 interrupt request * Intelligent I/O interrupt request * CAN interrupt request(1) * Software trigger DMA0 > DMA1 > DMA2 > DMA3 (DMA0 has the highest priority) 8 bits, 16 bits Fixed address: one specified address Incremented address: address which is incremented by a transfer unit on each successive access. (Source address and destination address cannot be both fixed nor both incremented.) Transfer is completed when the DCTi register (i = 0 to 3) becomes 0000h When the DCTi register becomes 0000h, values of the DRCi register are reloaded into the DCTi register and the DMA transfer continues. When the DCTi register becomes from 0001h to 0000h, a DMA interrupt request is generated. DMAC starts a data transfer when a DMA request is generated after bits MDi1 and MDi0 in the DMDj register (j = 0 to 1) are set to 01b (single transfer), while the DCTi register is set to 0001h or higher value. DMAC starts a data transfer when a DMA request is generated after bits MDi1 and MDi0 are set to 11b (repeat transfer), while the DCTi register is set to 0001h or higher value. * When bits MDi1 and MDi0 are set to 00b (DMA disabled) * When the DCTi register becomes 0000h (no DMA transfer) at completion of DMA transfer, or is set to 0000h by a program. * When bits MDi1 and MDi0 are set to 00b (DMA disabled) * When the DCTi register becomes 0000h (no DMA transfer) at completion of DMA transfer, or is set to 0000h by a program while the DRCi register is 0000h. Specification
Channel priority Transfer unit Transfer address
Transfer mode
Single transfer Repeat transfer
DMA interrupt request generation timing DMA start Single transfer
Repeat transfer
DMA stop
Single transfer
Repeat transfer
Reload timing to registers DCTi Values are reloaded when the DCTi register becomes from 0001h to 0000h in repeat and DMAi transfer mode. DMA transfer time Between SFR area and internal RAM transfer: minimum 3 bus clock cycles NOTE: 1. Only CAN00, CAN01, and CAN02 interrupt requests can be used for M32C/87A. Any CAN interrupt request cannot be used for M32C/87B.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
DMAi Request Source Select Register (i=0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL to DM3SL
Bit Symbol DSEL0 Bit Name
Address 0378h, 0379h, 037Ah, 037Bh
Function
After Reset 0X00 0000b
RW RW
DSEL1 DMA request source select bits(1)
See Table "DMiSL register function (i = 0 to 3)"
RW
DSEL2
RW
DSEL3
RW
DSEL4 When a software trigger is selected, a DMA request is generated by setting this bit to 1 (Read as 0) Read as undefined value 0: Not requested 1: Requested
RW
DSR - (b6) DRQ
Software DMA request bit (2)
RW
Reserved bit
-
DMA request bit(2, 3)
RW
NOTES: 1. Change settings of bits DSEL4 to DSEL0 while bits MDi1 and MDi0 in the DMD0 or DMD1 register are set to 00b (DMA disabled). Also, when bits DSEL4 to DSEL0 are changed, set the DRQ bit to 1 at the same time. e.g., MOV.B #083h, DMiSL ; Select timer A0 2. When the DSR bit is set to 1, set the DRQ bit to 1 at the same time. e.g., OR.B #0A0h, DMiSL 3. Do not write a 0 to the DRQ bit.
Figure 13.2
DM0SL to DM3SL Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 13.2
Setting Value b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DMA0 Software trigger Falling edge of INT0 Both edges of INT0 Timer A0 interrupt request Timer A1 interrupt request Timer A2 interrupt request Timer A3 interrupt request Timer A4 interrupt request Timer B0 interrupt request Timer B1 interrupt request Timer B2 interrupt request Timer B3 interrupt request Timer B4 interrupt request Timer B5 interrupt request UART0 transmit interrupt request UART0 receive interrupt or ACK interrupt request(3) UART1 transmit interrupt request UART1 receive interrupt or ACK interrupt request(3) UART2 transmit interrupt request UART2 receive interrupt or ACK interrupt request(3) UART3 transmit interrupt request UART3 receive interrupt or ACK interrupt request(3) UART4 transmit interrupt request UART4 receive interrupt or ACK interrupt request(3) A/D0 interrupt request Intelligent I/O interrupt 0 request(4) Intelligent I/O interrupt 1 request(5) Intelligent I/O interrupt 2 request Intelligent I/O interrupt 3 request Intelligent I/O interrupt 4 request Intelligent I/O interrupt 5 request(6) Intelligent I/O interrupt 6 request Intelligent I/O interrupt 7 request Intelligent I/O interrupt 8 request Intelligent I/O interrupt 9 request(7) Intelligent I/O interrupt 10 request(8) Intelligent I/O interrupt 11 request(9) Intelligent I/O interrupt 0 request(4) Intelligent I/O interrupt 1 request(5) Intelligent I/O interrupt 2 request Intelligent I/O interrupt 3 request Intelligent I/O interrupt 4 request Intelligent I/O interrupt 5 request(6) Intelligent I/O interrupt 6 request Intelligent I/O interrupt 7 request Intelligent I/O interrupt 8 request Falling edge of INT1 Both edges of INT1 Falling edge of INT2 Both edges of INT2 DMA1
13. DMAC
DMiSL Register (i = 0 to 3) Function
DMA Request Source DMA2 DMA3 Falling edge of INT3(1) Both edges of INT3(1)
(Note 2) (Note 2)
Intelligent I/O interrupt 9 request(7) Intelligent I/O interrupt 10 request(8) Intelligent I/O interrupt 11 request(9) Intelligent I/O interrupt 0 request(4) Intelligent I/O interrupt 1 request(5) Intelligent I/O interrupt 2 request Intelligent I/O interrupt 3 request
NOTES: 1. When the INT3 pin is used for data bus in memory expansion mode or microprocessor mode, a DMA3 interrupt request cannot be generated by an input signal to the INT3 pin. 2. The falling edge or both edges of input signal to the INTi pin can be a DMA request source. It is not affected by the INT interrupts (bits POL and LVS in the INTiIC register, the IFSR register) and vice versa. 3. To switch between the UARTj receive interrupt and ACK interrupt (j = 0 to 4), use the IICM bit in the UiSMR register and IICM2 bit on the UiSMR2 register. To use the ACK interrupt, set the IICM bit to 1 (I2C mode) and the IICM2 bit to 0 (NACK/ACK interrupt). 4. The same setting is used for a CAN10 interrupt request and a UART5 receive interrupt request. 5. The same setting is used for a CAN11 interrupt request and a UART5 transmit interrupt request. 6. The same setting is used for a CAN12 interrupt request. 7. The same setting is used for a CAN00 interrupt request, an INT6 interrupt request, and a UART6 receive interrupt request. 8. The same setting is used for a CAN01 interrupt request, an INT7 interrupt request, and a UART6 transmit interrupt request. 9. The same setting is used for a CAN02 interrupt request and INT8 interrupt request.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
DMAi Memory Address Register (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol DMA0 DMA1(2) DMA2 (bank1:A0)(3) DMA3 (bank1:A1)(4)
(2)
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
Function
After Reset XXXXXXh XXXXXXh 000000h 000000h
Setting Range 000000h to FFFFFFh (16 Mbytes) RW RW
Set an incremented source address or incremented destination address(1)
NOTES: 1. When the RWk bit (k = 0 to 3) in the DMDj register (j = 0, 1) is set to 0 (fixed address to incremented address), a destination address is selected. When the RWk bit is set to 1 (incremented address to fixed address), a source address is selected. 2. Use the LDC instruction to set registers DMA0 and DMA1. 3. To set the DMA2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the A0 register. 4. To set the DMA3 register, set the B flag to 1 and write to the A1 register.
DMAi SFR Address Register (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol DSA0(2) DSA1(2) DSA2 (bank1:SB)(3) DSA3 (bank1:FB)(4)
Function
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXXXh XXXXXXh 000000h 000000h
Setting Range 000000h to FFFFFFh (16 Mbytes) RW RW
Set a fixed source address or fixed destination address (1)
NOTES: 1. When the RWk bit (k = 0 to 3) in the DMDj register (j = 0, 1) is set to 0 (fixed address to incremented address), a source address is selected. When the RWk bit is set to 1 (incremented address to fixed address), a destination address is selected. 2. Use the LDC instruction to set registers DSA0 and DSA1. 3. To set the DSA2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the SB register using the LDC instruction. 4. To set the DSA3 register, set the B flag to 1 and write to the FB register using the LDC instruction.
Figure 13.3
DMA0 to DMA3 Registers, DSA0 to DSA3 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
DMAi Memory Address Reload Register(1) (i = 0 to 3)
b23 b16 b15 b8 b7 b0
Symbol DRA0 DRA1 DRA2 (SVP)(2) DRA3 (VCT)(3)
Function
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXXXh XXXXXXh XXXXXXh XXXXXXh
Setting Range 000000h to FFFFFFh (16 Mbytes) RW RW
Set an incremented source address or incremented destination address NOTES: 1. Use the LDC instruction to set registers DRA0 to DRA3. 2. To set the DRA2 register, write to the SVP register. 3. To set the DRA3 register, write to the VCT register.
DMAi Transfer Count Register (i = 0 to 3)
b15 b8 b7 b0
Symbol DCT0(2) DCT1(2) DCT2 (bank1:R0)(3) DCT3 (bank1:R1)(4)
Function Set the number of transfers
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXh XXXXh 0000h 0000h
Setting Range 0000h to FFFFh(1) RW RW
NOTES: 1. When the DCTi register is set to 0000h, no data transfer occurs regardless of a DMA request generation. 2. Use the LDC instruction to set registers DCT0 and DCT1. 3. To set the DCT2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R0 register. 4. To set the DCT3 register, set the B flag to 1 and write to the R1 register.
DMAi Transfer Count Reload Register (i = 0 to 3)
b15 b8 b7 b0
Symbol DRC0(1) DRC1(1) DRC2 (bank1:R2)(2) DRC3 (bank1:R3)(3)
Function Set the number of transfers
Address (CPU internal register) (CPU internal register) (CPU internal register) (CPU internal register)
After Reset XXXXh XXXXh 0000h 0000h
Setting Range 0000h to FFFFh RW RW
NOTES: 1. Use the LDC instruction to set registers DRC0 and DRC1. 2. To set the DRC2 register, set the B flag in the FLG register to 1 (register bank 1) and write to the R2 register. 3. To set the DRC3 register, set the B flag to 1 and write to the R3 register.
Figure 13.4
DRA0 to DRA3 Registers, DCT0 to DCT3 Registers, DRC0 to DRC3 Registers
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13. DMAC
DMA Mode Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMD0
Bit Symbol MD00 Channel 0 transfer mode select bits MD01 Channel 0 transfer unit select bit Bit Name
Address (CPU internal register)
Function
b1 b0
After Reset 00h
RW RW
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
b5 b4
RW
BW0
RW
RW0
Channel 0 transfer direction select bit
RW
MD10 Channel 1 transfer mode select bits MD11 Channel 1 transfer unit select bit Channel 1 transfer direction select bit
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
RW
RW
BW1
RW
RW1
RW
NOTE: 1. Use the LDC instruction to set the DMD0 register.
Figure 13.5
DMD0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
DMA Mode Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMD1
Bit Symbol MD20 Channel 2 transfer mode select bits MD21 Channel 2 transfer unit select bit Bit Name
Address (CPU internal register)
Function
b1 b0
After Reset 00h
RW RW
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
b5 b4
RW
BW2
RW
RW2
Channel 2 transfer direction select bit
RW
MD30 Channel 3 transfer mode select bits MD31 Channel 3 transfer unit select bit Channel 3 transfer direction select bit
0 0: DMA disabled 0 1: Single transfer 1 0: Do not set to this value 1 1: Repeat transfer 0: 8 bits 1: 16 bits 0: Fixed address to incremented address 1: Incremented address to fixed address
RW
RW
BW3
RW
RW3
RW
NOTE: 1. Use the LDC instruction to set the DMD1 register.
Figure 13.6
DMD1 Register
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13. DMAC
Start
Set the peripheral function used as DMAi request source DMD0 register: bits MD01 and MD00 = 00b bits MD11 and MD10 = 00b
Set the control registers of the peripheral function, but do not yet start. DMA disabled for channel 0 DMA disabled for channel 1
Write with LDC instruction
DMiSL register: bits DSEL4 to DSEL0 DSR bit = 0 DRQ bit = 1
DMA request source select bits DMA requested Set an incremented source address or incremented destination address
(note 1)
DMAi register
Write with LDC instruction DSAi register DRAi register Set an incremented source address or incremented destination address Write with LDC instruction Set a fixed source address or fixed destination address
DCTi register DRCi register
Set the number of transfers (2)
Write with LDC instruction
Set the number of transfers, which is to be reloaded
Write with LDC instruction
DMD0 register: bits MD01 and MD00 BW0 bit RW0 bit bits MD11 and MD10 BW1 bit RW1 bit Start the peripheral function used as DMAi request source
Transfer mode select bits for channel 0 Transfer unit select bit for channel 0 Transfer direction select bit for channel 0 Transfer mode select bits for channel 1 Transfer unit select bit for channel 1 Transfer direction select bit for channel 1
Write with LDC instruction (note 3)
(note 4)
End
i = 0, 1 NOTES: 1. When setting the DMiSL register, write a 1 to the DRQ bit. 2. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is 1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0. 3. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register. 4. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the same time.
Figure 13.7
Register Settings When Using DMA0 or DMA1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
Start
Set the peripheral function used as DMAi request source DMD1 register: bits MD21 and MD20 = 00b bits MD31 and MD30 = 00b
Set the control registers of the peripheral function, but do not yet start. DMA disabled for channel 2 DMA disabled for channel 3
Write with LDC instruction
DMiSL register: bits DSEL4 to DSEL0 DSR bit = 0 DRQ bit = 1
DMA request source select bits DMA requested
(note 1)
B flag = 1
Select register bank 1 (2) Set an incremented source address or incremented destination address Set a fixed source address or fixed destination address
DMA2 (A0) register or DMA3 (A1) register
Write with MOV instruction
DSA2 (SB) register or DSA3 (FB) register DRA2 (SVP) register or DRA3 (VCT) register
Write with LDC instruction
Set an incremented source address or incremented destination address
Write with LDC instruction
DCT2 (R0) register or DCT3 (R1) register DRC2 (R2) register or DRC3 (R3) register
Set the number of transfer (3)
Write with MOV instruction
Set the number of transfer, which is to be reloaded
Write with MOV instruction
B flag = 0
Select register bank 0 (2)
DMD1 register: bits MD21 and MD20 BW2 bit RW2 bit bits MD31 and MD30 BW3 bit RW3 bit Start the peripheral function used as DMAi request source
Transfer mode select bits for channel 2 Transfer unit select bit for channel 2 Transfer direction select bit for channel 2 Transfer mode select bits for channel 3 Transfer unit select bit for channel 3 Transfer direction select bit for channel 3
Write with LDC instruction (note 4)
(note 5)
End i = 2, 3 NOTES: 1. When setting the DMiSL register, write a 1 to the DRQ bit. 2. The register bank 1 and high-speed interrupt cannot be used when using DMA2 and DMA3. 3. When the INT interrupts are selected as a DMA request source, do not write a 1 to the DCTi register. If the DCTi register is 1, do not generate a DMA request when writing 01b or 11b to bits MDi1 and MDi0. 4. Wait six CPU clock cycles or more by a program to set bits MDi1 and MDi0 to 01b or 11b after setting the DMiSL register. 5. When a DMA transfer is started by the software trigger, set both the DSR and DRQ bit in the DMiSL register to 1 at the same time.
Figure 13.8
Register Settings When Using DMA2 or DMA3
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
13. DMAC
13.1
Transfer Cycles
The transfer cycle is composed of bus cycles to read data from source address (source read) and bus cycles to write data to destination address (destination write). The number of read and write bus cycles depends on the locations of source and destination addresses. In memory expansion mode and microprocessor mode, the number of read and write bus cycles also depends on DS register setting. Software wait state insertion and the RDY signal can extend the number of the bus cycles.
13.1.1
Effect of Source and Destination Addresses
When a 16-bit data is transferred with a 16-bit data bus and a source address starts with an odd address, the source-read cycle is added by one bus cycle, compared to a source address starting with an even address. When a 16-bit data is transferred with a 16-bit data bus and a destination address starts with an odd address, the destination-write cycle is added by one bus cycle, compared to a destination address starting with an even address.
13.1.2
Effect of the DS Register
In an external space in memory expansion mode and microprocessor mode, the transfer cycle varies depending on the data bus width of the source and destination addresses. See Figure 8.1 for details about the DS register. * When a 16-bit data is transferred accessing both source address and destination address with an 8-bit data bus (the DSi bit in the DS register is set to 0 (i = 0 to 3)), an 8-bit data will be transferred twice. Therefore, two bus cycles are required for reading and another two bus cycles for writing. * When a 16-bit data is transferred accessing a source address with an 8-bit data bus (the DSi bit is set to 0) and a destination address with a 16-bit data bus, an 8-bit data will be read twice but be written once as 16bit data. Therefore, two bus cycles are required for reading and one bus cycle for writing. * When a 16-bit data is transferred accessing a source address with a 16-bit data bus (the DSi bit is set to 1) and a destination address with an 8-bit data bus, a 16-bit data will be read once and an 8-bit data will be written twice. Therefore, one bus cycle is required for reading and two bus cycles for writing.
13.1.3
Effect of Software Wait State
When accessing the SFR area or memory space that requires wait states, the number of bus clocks (BCLK) is increased by software wait states.
13.1.4
Effect of the RDY Signal
In memory expansion mode and microprocessor mode, the RDY signal affects the number of the bus cycles if a source address or destination address is in an external space. Refer to 8.2.6 RDY Signal for details.
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13. DMAC
13.2
DMA Transfer Time
The DMA transfer time can be calculated as follows. (in terms of bus clock) Table 13.3 lists the number of the source read cycle and destination write cycle. Table 13.4 lists coefficient j, k (the number of bus clock). Transfer time = source read bus cycle x j + destination write bus cycle x k Table 13.3 Source Read Cycle and Destination Write Cycle
Bus Width 16 bits 8 bits 16 bits 8 bits i=0 to 3, p=0 and 1 Access Address Even Odd Even Odd 16-bit transfer (BWi bit = 1) Even Odd Even Odd Accessing Internal Space Read Cycle 1 1 - - 1 2 - - Write Cycle 1 1 - - 1 2 - - Accessing External Space Read Cycle 1 1 1 1 1 2 2 2 Write Cycle 1 1 1 1 1 2 2 2
Transfer Unit 8-bit transfer (BWi bit in the DMDp register = 0)
Table 13.4
Coefficient j, k
Internal Space External Space SFR area j=2 k=2 j and k BCLK cycles shown in Table 8.6 (j, k = 2 to 9). Add one cycle to j or k cycles when inserting a recovery cycle Internal ROM or internal RAM with wait state j=2 k=2
Internal ROM or internal RAM with no wait state j=1 k=1
13.3
Channel Priority and DMA Transfer Timing
When multiple DMA requests are generated in the same sampling period (between a falling edge of the BCLK and the next falling edge), the corresponding DRQ bits in the DMiSL register (i = 0 to 3) are set to 1 (requested) simultaneously. Channel priority in this case is: DMA0 > DMA1 > DMA2 > DMA3. Leave the following period between each DMA transfer request generation on the same channel. DMA request interval (number of channels set for DMA transfer - 1) x 5 BCLK cycles Described in the following is the operation when DMA0 and DMA1 requests are generated in the same sampling period. Figure 13.9 shows an example of DMA transfers triggered by the INT interrupts. In Figure 13.9, DMA0 and DMA1 requests are generated simultaneously. A DMA0 request having higher priority is acknowledged first to start a transfer. After one DMA0 transfer is completed, the DMAC returns ownership of the bus to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is completed, bus ownership is again returned to the CPU. DMA requests cannot be counted up since each channel has one DRQ bit. Even if multiple DMA1 requests are generated before receiving bus ownership as shown in Figure 13.9, the DRQ bit is set to 0 as soon as bus ownership is acquired. Bus ownership is returned to the CPU after one transfer is completed.
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13. DMAC
Example when DMA transfer requests for DMA0 and DMA1 are generated simultaneously and DMA transfers (SFR to RAM) are performed in minimum time.
BCLK
DMA0 Bus privilege acquired
DMA1
CPU
INT0 DRQ bit in DMA0 INT1 DRQ bit in DMA1
Figure 13.9
DMA Transfers Triggered by INT Interrupt Requests
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14. DMACII
14. DMACII
DMACII performs memory-to-memory transfer, immediate data transfer, and calculation transfer which transfers a result of the addition of two data. DMACII transfer occurs in response to interrupt requests from the peripheral functions. Table 14.1 lists specifications of DMACII. Table 14.1 DMACII Specifications
Item DMACII request source Transfer data Specification Interrupt requests generated by any peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7) - Data in a memory location is transferred to another memory location (memory-to-memory transfer) - Immediate data is transferred to a memory location (immediate data transfer) - Data in a memory location (or immediate data) + data in another memory location is transferred to the other memory location (calculation transfer) 8 bits or 16 bits 64-Kbyte space in addresses 00000h to 0FFFFh(1)(2) Fixed address: one specified address Incremented address: address which is incremented by the transfer unit on each successive access. (Selectable for source address and destination address individually) Single transfer, burst transfer, multiple transfer Address indicated by an interrupt vector for DMACII index is replaced when a transfer counter reaches zero Interrupt occurs when a transfer counter reaches zero
Transfer unit Transfer space Transfer address
Transfer mode Chain transfer function End-of-transfer interrupt
NOTES: 1. When a destination address is 0FFFFh and a 16-bit data is transferred, it is transferred to addresses 0FFFFh and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred to a given destination address. 2. The actual transferable space varies depending on internal RAM capacity.
14.1
DMACII Settings
Set up the following registers and tables to activate DMACII. * RLVL register * DMACII Index * Interrupt Control Register of the peripheral functions triggering DMACII requests * The relocatable vector table of the peripheral functions triggering DMACII requests * IRLT bit in the IIOiIE register (i = 0 to 11) if using the intelligent I/O interrupt, CAN interrupt, INTj interrupt (j = 6 to 8), UARTk (k = 5, 6) transmit, or UARTk receive interrupt. Refer to 11. Interrupts for details on the IIOiIE register.
14.1.1
RLVL Register
When the DMAII bit is set to 1 (interrupt priority level 7 is used for DMACII transfer) and the FSIT bit to 0 (interrupt priority level 7 is used for normal interrupt), DMACII is activated by an interrupt request from any peripheral functions with bits ILVL2 to ILVL0 in the Interrupt Control Register set to 111b (level 7). Figure 14.1 shows the RLVL register.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
14. DMACII
Exit Priority Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RLVL
Bit Symbol RLVL0 Exit wait mode/stop mode interrupt priority level control bits(1) Bit Name
Address 009Fh
Function
b2 b1 b0
After Reset XXXX 0000b
RW RW
RLVL1
RLVL2
0 0 0: Level 0 0 0 1: Level 1 0 1 0: Level 2 0 1 1: Level 3 1 0 0: Level 4 1 0 1: Level 5 1 1 0: Level 6 1 1 1: Level 7 0: Interrupt priority level 7 is used for normal interrupt 1: Interrupt priority level 7 is used for high-speed interrupt(2)(3)
RW
RW
FSIT
High-speed interrupt select bit
RW
- (b4) DMAII - (b7-b6)
Unimplemented. Write 0. Read as undefined value. DMACII select bit (4) Unimplemented. Write 0. Read as undefined value. 0: Interrupt priority level 7 is used for interrupt 1: Interrupt priority level 7 is used for DMACII transfer (2)
-
RW
-
NOTES: 1. The MCU exits stop or wait mode when an interrupt priority level of a requested interrupt is higher than a level set using bits RLVL2 to RLVL0. Set bits RLVL2 to RLVL0 to the same value as IPL in the FLG register. 2. Do not set both the FSIT and DMAII bits to 1. Set either the FSIT bit or the DMAII bit to 1 before setting bits ILVL2 to ILVL0 in the Interrupt Control Register to 111b. 3. Only one interrupt can have the interrupt priority level 7 when selecting the high-speed interrupt. 4. The DMAII bit is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt Control Register.
Figure 14.1
RLVL Register
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14. DMACII
14.1.2
DMACII Index
The DMACII index is an 8- to 32-byte data table, which stores parameters for transfer mode, transfer counter, source address (or immediate data), operation address as an address to be calculated, destination address, chain transfer address, and end-of-transfer interrupt address. The DMACII index must be located on the RAM area. Figure 14.2 shows a configuration of the DMACII index. Table 14.2 lists an example configuration of the DMACII index.
Memory-to-Memory Transfer, Immediate Transfer, Calculation Transfer
DMACII Index Starting Address (BASE) BASE+2 BASE+4 BASE+6 BASE+8 16 bits Transfer mode (MOD) Transfer counter (COUNT) Transfer source address (or immediate data) (SADR) Operation address(1) (OADR) Transfer destination address (DADR)
Multiple Transfer
16 bits BASE BASE+2 BASE+4 BASE+6 BASE+8 Transfer mode (MOD) Transfer counter (COUNT) Transfer source address (SADR1) Transfer destination address (DADR1) Transfer source address (SADR2)
BASE+10 Chain Transfer Address (lower byte) (2) (CADR0) BASE+12 Chain Transfer Address (higher byte) (2) (CADR1)
(3) BASE+14 End-of-Transfer Interrupt Address (lower byte) (IADR0) End-of-Transfer Interrupt Address (higher byte) (3) BASE+16 (IADR1)
BASE+10 Transfer destination address (DADR2) to BASE+28 Transfer source address (SADR7) BASE+30 Transfer destination address (DADR7)
NOTES: 1. This data is not needed unless using the calculation transfer function. 2. This data is not needed unless using the chain transfer function. 3. This data is not needed unless using the end-of-transfer interrupt. Place the DMACII index in the RAM. Necessary data must be set top-aligned without any space. For example, if not using the calculation transfer function, assign a transfer destination address to BASE+6. The starting address of the DMACII index must be assigned to the interrupt vector of the peripheral function interrupt triggering a DMACII request.
Figure 14.2
DMACII Index
Details of the DMACII index are described below. Set these parameters in the specified order listed in Table 14.2, depending on DMACII transfer mode. * Transfer mode (MOD) MOD is two-byte data and required to set transfer mode. Figure 14.3 shows a configuration for transfer mode. * Transfer counter (COUNT) COUNT is two-byte data and required to set the number of transfer. * Transfer source address (SADR) SADR is two-byte data and required to set a source memory address or immediate data. * Operation address (OADR) OADR is two-byte data and required to set a memory address to be calculated. Set this data only when using the calculation transfer function. * Transfer destination address (DADR) DADR is two-byte data and required to set a destination memory address. * Chain transfer address (CADR) CADR is four-byte data and required to set the starting address of the DMACII index for the next transfer. Set this data only when using the chain transfer function. * End-of-transfer interrupt address (IADR) IADR is four-byte data and required to set a jump address for end-of-transfer interrupt processing. Set this data only when using the end-of-transfer interrupt. The abbreviations shown in parentheses( ) for each parameter are used in this section.
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Table 14.2
Transfer data Chain transfer End-ofTransfer Interrupt DMAC II index Not used Not used MOD COUNT SADR DADR 8 bytes
14. DMACII
DMACII Index Configuration in Transfer Mode
Memory-to-Memory Transfer/ Immediate Data Transfer Used Not used MOD COUNT SADR DADR CADR0 CADR1 12 bytes Not used Used MOD COUNT SADR DADR IADR0 IADR1 12 bytes Used Used MOD COUNT SADR DADR CADR0 CADR1 IADR0 IADR1 16 bytes Not used Not used MOD COUNT SADR OADR DADR 10 bytes Calculation Transfer Used Not used MOD COUNT SADR OADR DADR CADR0 CADR1 14 bytes Not used Used MOD COUNT SADR OADR DADR IADR0 IADR1 14 bytes Used Used MOD COUNT SADR OADR DADR CADR0 CADR1 IADR0 IADR1 18 bytes SADRi DADRi
i = 1 to 7 max. 32 bytes (when i = 7)
Multiple Transfer Cannot used Cannot used MOD COUNT SADR1 DADR1
Transfer Mode (MOD)(1)
b15 b8 b7 b0
Bit Symbol SIZE
Bit Name Transfer unit select bit
Function (MULT = 0) 0: 8 bits 1: 16 bits 0: Immediate data 1: Memory 0: Fixed address 1: Incremented address 0: Fixed address 1: Incremented address 0: Not used 1: Used 0: Single transfer 1: Burst transfer 0: Interrupt not used 1: Interrupt used 0: Chain transfer not used 1: Chain transfer used
b6 b5 b4
Function (MULT = 1)
RW RW
IMM
Transfer data select bit Transfer source direction select bit Transfer destination direction select bit Calculation transfer function select bit Burst transfer select bit End-of-transfer interrupt select bit Chain transfer select bit
Set to 1
RW
UPDS
RW
UPDD OPER/ CNT0(2) BRST/ CNT1(2) INTE/ CNT2(2) CHAIN
RW
0 0 0: Do not set to this value 0 0 1: Once 0 1 0: Twice : : 1 1 0: 6 times 1 1 1: 7 times Set to 0
RW
RW
RW
RW
- (b14-b8)
MULT
Unimplemented. Write 0. Read as undefined value. Multiple transfer select bit 0: Multiple transfer not used 1: Multiple transfer used
-
RW
NOTES: 1. MOD must be located in the RAM. 2. When the MULT bit is set to 0, bits 6 to 4 function as bits OPER, BRST, and INTE. When the MULT bit is set to 1, bits 6 to 4 function as bits CNT2 to CNT0.
Figure 14.3
MOD
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14. DMACII
14.1.3
Interrupt Control Register for the Peripheral Function
To use the peripheral function interrupt as a DMACII request source, set bits ILVL2 to ILVL0 to 111b (level 7).
14.1.4
Relocatable Vector Table for the Peripheral Function
Set the starting address of the DMACII index in an interrupt vector for the peripheral function interrupt used as a DMACII request source. When using the chain transfer, the relocatable vector table must be located in the RAM.
14.1.5
IRLT Bit in the IIOiIE Register (i = 0 to 11)
When the intelligent I/O interrupt, CAN interrupt, INTj interrupt (j = 6 to 8), UARTk (k = 5, 6) transmit interrupt, or UARTk receive interrupt is used to activate DMACII, set the IRLT bit in the corresponding IIOiIE register (i = 0 to 11) to 0 (interrupt request is used for DMAC, DMACII).
14.2
DMACII Performance
The DMACII function is selected by setting the DMAII bit to 1 (interrupt priority level 7 is used for DMACII transfer). DMACII transfer request is generated by interrupt requests from any peripheral function with bits ILVL2 to ILVL0 set to 111b (level 7). These peripheral function interrupt requests are used as DMACII transfer requests and the peripheral function interrupts cannot be used. When an interrupt request with bits ILVL2 to ILVL0 set to 111b (level 7) is generated, DMACII is activated regardless of the I flag and IPL settings.
14.3
Transfer Data
DMACII transfers data in 8-bit units or 16-bit units. * Memory-to-memory transfer: data is transferred from a given memory location in the 64-Kbyte space (addresses 00000h to 0FFFFh) to another given memory location in the same space. * Immediate data transfer: immediate data is transferred to a given memory location in the 64-Kbyte space. * Calculation transfer: two 8-bit or two 16-bit data are added together and the result is transferred to a given memory location in the 64-Kbyte space. When a 16-bit data is transferred to a destination address 0FFFFh, it is transferred to addresses 0FFFFh and 10000h. Likewise, when a source address is 0FFFFh, a 16-bit data in addresses 0FFFFh and 10000h is transferred to a given destination address. The actual transferable space varies depending on internal RAM capacity. Refer to Figure 3.1 for the internal memory.
14.3.1
Memory-to-memory Transfer
Data transfer between any two memory locations in the 64-Kbyte space can be: * a transfer from a fixed address to another fixed address; * a transfer from a fixed address to an incremented address; * a transfer from an incremented address to a fixed address; * a transfer from an incremented address to another incremented address. When an incremented address is selected, DMACII increments an address after every transfer for the following transfer. In a 8-bit data transfer, a transfer address is incremented by one. In a 16-bit data transfer, a transfer address is incremented by two. When a source or destination address exceeds 0FFFFh as a result of address incrementation, the source or destination address returns to 00000h and continues incrementation. Maintain source and destination address at 0FFFFh or below.
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14. DMACII
14.3.2
Immediate Data Transfer
DMACII transfers immediate data to a given memory location. A fixed or incremented address can be selected as a destination address. Store immediate data into SADR. To transfer an 8-bit immediate data, write data in the low-order byte of SADR. (The high-order byte is ignored.)
14.3.3
Calculation Transfer
After two memory data, or an immediate data and a memory data, are added together, DMACII transfers the calculated result to a given memory location. Set a memory address or immediate data to be calculated in SADR. Set another memory address to be calculated in OADR. To use a "memory + memory" calculation transfer, a fixed or incremented address can be selected as a source or destination address. If a source address is incremented, an operation address also becomes incremented. To use an "immediate data + memory" calculation transfer, a fixed or incremented address can be selected as a destination address.
14.4
Transfer Modes
In DMACII, a single transfer, burst transfer, and multiple transfer are available. The BRST bit in MOD selects either a single transfer or burst transfer, and the MULT bit in MOD selects a multiple transfer. COUNT determines how many transfers occur. No transfer occurs when COUNT is set to 0000h.
14.4.1
Single Transfer
For one transfer request, DMACII transfers an 8-bit or 16-bit data once. When an incremented address is selected for a source or destination address, DMACII increments the address after every transfer for the following transfer. COUNT is decremented every time a transfer occurs. If using the end-of-transfer interrupt, an interrupt occurs when COUNT reaches zero.
14.4.2
Burst Transfer
For one transfer request, DMACII continuously transfers data the number of times determined by COUNT. COUNT is decremented every time DMACII transfers one transfer unit, and when it reaches zero, a burst transfer is completed. If using the end-of-transfer interrupt, an interrupt occurs at the end of the burst transfer. While the burst transfer is taking place, no interrupt can be acknowledged.
14.4.3
Multiple Transfer
When using the multiple transfer, select the memory-to-memory transfer. For one transfer request, DMACII transfers data multiple times. Bits CNT2 to CNT0 in MOD selects the number of transfers from 001b (once) to 111b (7 times). Do not set bits CNT2 to CNT0 to 000b. Source and destination addresses enough for all transfers must be allocated alternately in addresses following MOD and COUNT in DMACII index. While the transfers are taking place the number of times set using bits CNT2 to CNT0, no interrupt can be acknowledged. When the multiple transfer is selected, a calculation transfer, burst transfer, chain transfer, and end-of-transfer interrupt cannot be used.
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14. DMACII
14.5
Chain Transfer
The chain transfer can be selected with the CHAIN bit in MOD. The chain transfer is performed as follows. (1) Transfer occurs in response to an interrupt request from a peripheral function and is performed according to the contents of the DMACII index at the address specified by the interrupt vector. For one transfer request, either a single transfer or burst transfer selected by the BRST bit in MOD occurs. (2) When COUNT reaches zero, the interrupt vector in (1) is replaced with the address written in CADR1 and CADR0. The end-of-transfer interrupt occurs after the replacement, if the INTE bit in MOD is set to 1. (3) When the next DMACII transfer request is generated, the transfer is performed according to the contents of the DMACII index specified by the interrupt vector which has been replaced in (2). Figure 14.4 shows the relocatable vector and DMACII index when using the chain transfer. For the chain transfer, the relocatable vector table must be located in the RAM.
RAM INTB Relocatable Vector
Interrupt vector of the peripheral function triggering DMACII request. Default value is BASE (a).
BASE (a) DMACII index (a) (CADR1, CADR0) BASE (b) When COUNT reaches zero, the above interrupt vector is replaced with BASE (b), which is the address written in CADR1 and CADR0. When the next request occurs, a transfer starts according to the contents of the DMACII index at BASE (b). BASE (b) DMACII index (b) (CADR1, CADR0) BASE (c) When COUNT reaches zero, the interrupt vector is replaced wtih BASE (c).
Figure 14.4
Relocatable Vector and DMACII Index When using the Chain Transfer
14.6
End-of-Transfer Interrupt
The end-of-transfer interrupt can be selected with the INTE bit in MOD. Set the starting address of the end-oftransfer interrupt routine in IADR1 and IADR0. The end-of-transfer interrupt occurs when COUNT reaches zero.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
14. DMACII
14.7
Execution Time
DMACII execution time is calculated by the following equations (single-speed mode): Multiple transfers: t [bus clock] = 21+ (11 + b + c) x k Other than multiple transfers: t [bus clock] = 6 + (26 + a + b + c + d) x m + (4 + e) x n a: If IMM = 0 (source is immediate data), a = 0; if IMM = 1 (source is data in memory location), a = -1. b: If UPDS = 1 (source address is incremented), b = 0; if UPDS = 0 (source address is fixed), b = 1. c: If UPDD = 1 (destination address is incremented), c = 0; if UPDD = 0 (destination address is fixed), c = 1. d: If OPER = 0 (calculation function is not selected), d = 0; if OPER = 1 (calculation function is selected) and UPDS = 0 (source is immediate data or fixed address in memory location), d = 7; if OPER = 1 (calculation function is selected) and UPDS = 1 (source is incremented address in memory location), d = 8. e: If CHAIN = 0 (chain transfer is not selected), e = 0; if CHAIN = 1 (chain transfer is selected), e = 4. m: If BRST = 0 (single transfer), m = 1; if BRST = 1 (burst transfer), m = a value set in COUNT. n: If COUNT = 1, n = 0; if COUNT = 2 or more, n = 1. k: The number of transfers set in bits CNT2 to CNT0 in MOD. The above equations are approximations. The execution time varies depending on CPU state, bus wait states, and DMACII index allocation. The first instruction of the end-of-transfer interrupt routine is executed in the eighth bus clock after the DMACII transfer is completed.
Conditions of the example below: -memory-to-memory transfer (a = -1) -incremented source address (b = 0) -fixed destination address (c = 1) -no calculation function (d = 0) -no chain transfer (e = 0) -single transfer (m = 1) -the end-of-transfer interrupt (transfer counter = 2) occurs First DMACII transfer t = 6 + 26 x 1 + 4 x 1 = 36 bus clocks Second DMACII transfer t = 6 + 26 x 1 + 4 x 0 = 32 bus clocks
DMACII transfer requested DMACII transfer requested
Program
First DMACII transfer
Program
Second DMACII transfer
End-of-transfer interrupt routine executed
36 clocks
32 clocks
7 clocks
Transfer counter = 2
Transfer counter = 1 Transfer counter is decremented. Transfer counter = 0
Transfer counter is decremented. Transfer counter = 1
Figure 14.5
Transfer Time
When a DMACII transfer request is generated simultaneously with another request having a higher priority (e.g., NMI or watchdog timer), the interrupt with higher priority is acknowledged first, and the pending DMACII transfer starts after the interrupt sequence of the higher priority interrupt has been completed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timers
15. Timers
The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has eleven 16-bit timers, and they are separated into five timer A and six timer B based on their functions. Individual timers function independently. The count source for each timer is used to operate the timer for counting and reloading, etc. Figures 15.1 and 15.2 show block diagrams of timer A and timer B configurations.
Clock Prescaler XCIN Set the CPSR bit in the CPSRF register to 1 f1 f8 f2n fC32
1/32
Reset
fC32
00 01 10 11
TCK1 and TCK0
10
TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
TA0IN
Noise filter
TCK1 and TCK0
01 00
Timer A0
01: Event counter mode 11 TA0TGH and TA0TGL
Timer A0 interrupt
00 01 10 11
10
TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
TA1IN
Noise filter
TCK1 and TCK0
01 00
Timer A1
01: Event counter mode 11 TA1TGH and TA1TGL
Timer A1 interrupt
00 01 10 11
10
TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
TA2IN
Noise filter
TCK1 and TCK0
01 00
Timer A2
01: Event counter mode 11 TA2TGH and TA2TGL
Timer A2 interrupt
00 01 10 11
10
TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
TA3IN
Noise filter
TCK1 and TCK0
01 00
Timer A3
01: Event counter mode 11 TA3TGH and TA3TGL
Timer A3 interrupt
00 01 10 11
10
TMOD1 and TMOD0 00: Timer mode 10: One-shot timer mode 11: PWM mode
TA4IN
Noise filter
01 00
Timer A4
01: Event counter mode 11 TA4TGH and TA4TGL
Timer A4 interrupt
Timer B2 overflow or underflow signal TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TAiMR register TAiGH, TAiGL: Bits in the ONSF register or the TRGSR register (i = 0 to 4)
Figure 15.1
Timer A Configuration
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timers
Clock prescaler XCIN Set the CPSR bit in the CPSRF register to 1
1/32
Reset
fC32
f1 f8 f2n fC32
Timer B2 overflow or underflow signal (to the count source of timer A)
TCK1 and TCK0 TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 TCK1 01: Event counter mode TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 TCK1 01: Event counter mode TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 TCK1 01: Event counter mode TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 TCK1 01: Event counter mode TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 TCK1 01: Event counter mode TMOD1 and TMOD0 00: Timer mode 10: Pulse width measurement mode, Pulse cycle measurement mode 1 0 TCK1 01: Event counter mode
00 01 10 11
TB0IN
Noise filter
00 01 10 11 TCK1 and TCK0
Timer B0
Timer B0 interrupt
TB1IN
00 01 10 11
Noise filter
TCK1 and TCK0
Timer B1
Timer B1 interrupt
TB2IN
00 01 10 11
Noise filter
TCK1 and TCK0
Timer B2
Timer B2 interrupt
TB3IN
Noise filter
00 01 10 11 TCK1 and TCK0
Timer B3
Timer B3 interrupt
TB4IN
00 01 10 11
Noise filter
TCK1 and TCK0
Timer B4
Timer B4 interrupt
TB5IN
Noise filter
Timer B5
Timer B5 interrupt
TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register (i = 0 to 5)
Figure 15.2
Timer B Configuration
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
15.1
Timer A
Timer A contains the following four modes. Except in event counter mode, all timers A0 to A4 have the same functionality. Bits TMOD1 and TMOD0 in the TAiMR register (i = 0 to 4) determine which mode is used. * Timer mode: The timer counts the internal count source. * Event counter mode: The timer counts overflow/underflow signal of another timer or the external pulses. * One-shot timer mode: The timer operates only once for one trigger. * Pulse width modulation mode: The timer continuously outputs given pulse widths. Figure 15.3 shows a block diagram of timer A. Figures 15.4 to 15.13 show the registers associated with timer A. Table 15.1 lists TAiOUT pin settings to use in output mode. Table 15.2 lists TAiIN and TAiOUT pin settings to use in input mode.
Clock select Clock source select TCK1 and TCK0 f1 00 f8 01 f2n(1) 10 11 fC32 Polarity Selector High-order bits of data bus * Timer mode * One-shot timer mode TMOD1 and TMOD0, MR2 * Pulse width modulation mode * Timer Mode (Gate Function) * Event counter mode TAiS Counter Increment/decrement Always decrement except in event counter mode 00 10 11 01 TAiUD 0 1 Function select register TAiOUT Toggle flip flop MR2 TMOD1 and TMOD0 Low-order bits of data bus 8 low-order bits Reload register 8 high-order bits
TAiIN
TB2 Overflow(2) TAj Overflow(2) TAk Overflow(2)
00 01 10 11 11 TAiTGH to TAiTGL
Decrement
i = 0 to 4 j = i - 1, except j = 4 if i = 0 k = i + 1, except k = 0 if i = 4 NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Overflow signal or underflow signal.
TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4
Addresses 0347h 0346h 0349h 0348h 034Bh 034Ah 034Dh 034Ch 034Fh 034Eh
TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3
TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0
TCK1 and TCK0, TMOD1 and TMOC0, MR2 and MR1: Bits in the TAiMR register TAiTGH to TAiTGL: Bits in the ONSF register if i = 0 or bits in the TRGSR register if i = 1 to 4 TAiS: Bit in the TABSR register TAiUD: Bit in the UDF register
Figure 15.3
Timer A Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Count Source Prescaler Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TCSPR
Bit Symbol CNT0 Bit Name
Address 035Fh
Function
After Reset(2) 0XXX 0000b
RW RW
CNT1 Divide ratio select bits (1) CNT2
If the setting value is n, f2n is the main clock, on-chip oscillator, or PLL clock divided by 2n. No division if n = 0
RW
RW
CNT3
RW
- (b6-b4)
CST
Reserved bits
Read as undefined value 0: Divider stops 1: Divider operates
-
Operation enable bit
RW
NOTES: 1. Set the CST bit to 0 before bits CNT3 to CNT0 are rewritten. 2. The TCSPR register maintains values set before reset, even after software reset or watchdog timer reset has been performed.
Figure 15.4
TCSPR Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
000
Symbol TA0MR to TA4MR
Bit Symbol TMOD0 Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
RW RW
Operating mode select bits TMOD1
b1 b0
0 0: Timer mode RW
- (b2)
MR1
Reserved bit
Set to 0
b4 b3
RW
Gate function select bits MR2
0 0: Gate function disabled 0 1: (TAiIN pin is a programmable I/O port) 1 0: Timer counts only while an "L" signal is input to the TAiIN pin 1 1: Timer counts only while an "H" signal is input to the TAiIN pin
RW
RW
MR3
Set to 0 in timer mode
RW
TCK0 Count source select bits TCK1
b7 b6
0 0: f1 0 1: f8 1 0: f2n(1) 1 1: fC32
RW
RW
NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divided-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.5
TA0MR to TA4MR Registers in Timer Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol TA0MR to TA4MR
Bit Symbol Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
Function RW
(When not processing two-phase pulse signals)
(When processing two-phase pulse signals)
TMOD0 Operating mode select bits TMOD1
b1 b0
RW 0 1: Event counter mode(1) RW
- (b2)
Reserved bit
Set to 0 0: Falling edges of an external signal counted 1: Rising edges of an external signal counted 0: UDF registser setting 1: Signal applied to the TAiOUT pin (3)
RW
MR1
Count polarity select bit (2)
Set to 0
RW
MR2
Increment/decrement switching source select bit Set to 0 in event counter mode Count operation type select bit Two-phase pulse signal processing operation select bit(4,5)
Set to 1
RW
MR3
RW 0: Reload 1: Free running 0: Normal processing operation 1: Multiply-by-4 processing operation
TCK0
RW
TCK1
Set to 0
RW
NOTES: 1. Bits TAiTGH and TAiTGL in the ONSF or TRGSR register determine a count source in event counter mode. 2. The MR1 bit is enabled only when counting external signals. 3. The counter decrements when an "L" signal is applied to the TAiOUT pin. The counter increments when an "H" signal is applied to the TAiOUT pin. 4. The TCK1 bit is enabled only in the TA3MR register. The TCK1 bit in registers TA0MR to TA2MR and TA4MR are disabled. 5. For two-phase pulse signal processing, set the TAjP bit in the UDF register (j = 2 to 4) to 1 (two-phase pulse signal processing function enabled). Also, set bits TAjTGH and TAjTGL in the TRGSR register to 00b (input to the TAjIN pin).
Figure 15.6
TA0MR to TA4MR Registers in Event Counter Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(One-Shot Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
010
Symbol TA0MR to TA4MR
Bit Symbol TMOD0 Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
RW RW
Operating mode select bits TMOD1
b1 b0
1 0: One-shot timer mode RW
- (b2)
MR1
Reserved bit
Set to 0 0: Falling edge of signal applied to the TAiIN pin 1: Rising edge of signal applied to the TAiIN pin 0: The TAiOS bit enabled 1: Selected by bits TAiTGH and TAiTGL
RW
External trigger select bit(1)
RW
MR2
Trigger select bit
RW
MR3
Set to 0 in one-shot timer mode
RW
TCK0 Count source select bits TCK1
b7 b6
0 0: f1 0 1: f8 1 0: f2n(2) 1 1: fC32
RW
RW
NOTES: 1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN pin). The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj (j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow). 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.7
TA0MR to TA4MR Registers in One-Shot Timer Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Timer Ai Mode Register (i = 0 to 4)(Pulse Width Modulation Mode)
b7 b6 b5 b4 b3 b2 b1 b0
011
Symbol TA0MR to TA4MR
Bit Symbol TMOD0 Bit Name
Address 0356h, 0357h, 0358h, 0359h, 035Ah
Function
After Reset 00h
RW RW
Operating mode select bits TMOD1
b1 b0
1 1: Pulse width modulation (PWM) mode RW
- (b2)
MR1
Reserved bit
Set to 0 0: Falling edge of signal applied to the TAiIN pin 1: Rising edge of signal applied to the TAiIN pin 0: The TAiS bit is enabled 1: Selected by bits TAiTGH and TAiTGL 0: Functions as 16-bit pulse width modulator 1: Functions as 8-bit pulse width modulator
b7 b6
RW
External trigger select bit(1)
RW
MR2
Trigger select bit
RW
MR3
16/8-bit PWM mode select bit
RW
TCK0 Count source select bits TCK1
0 0: f1 0 1: f8 1 0: f2n (2) 1 1: fC32
RW
RW
NOTES: 1. The MR1 bit is enabled only when bits TAiTGH and TAiTGL in the ONSF or TRGSR register are set to 00b (input to the TAiIN pin). The MR1 bit can be set to either 0 or 1 when bits TAiTGH and TAiTGL are set to 01b (TB2 overflow or underflow), 10b (TAj (j = i - 1, except j = 4 if i = 0) overflow or underflow), or 11b (TAk (k = i + 1, except i = 4 if k = 0) overflow or underflow). 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.8
TA0MR to TA4MR Registers in Pulse Width Modulation Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Timer Ai Register(1) (i = 0 to 4)
b15 b8 b7 b0
Symbol TA0 to TA2 TA3, TA4
Mode Timer mode
Address 0347h - 0346h, 0349h - 0348h, 034Bh - 034Ah 034Dh - 034Ch, 034Fh - 034Eh
Function If a count source frequency is fj and the setting value of TAi register is n, the counter cycle is (n + 1) / fj If the setting value is n, the count times are (FFFFh - n+1) when the counter increments, and (n+1) when the counter decrements (2) If the setting value is n, the counter counts n times and stops. If a count source frequency is fj and the setting value of the TAi register is n, PWM cycle: (216 - 1) / fj "H" width of PWM pulse: n / fj If a count source frequency is fj, the setting value of high-order bits in the TAi register is n, and the setting value of low-order bits in the TAi register is m, PWM cycle: (28 -1) x (m+1) / fj "H" width of PWM pulse: (m+1) n / fj
After Reset Undefined Undefined
RW RW
Setting Range 0000h to FFFFh
Event counter mode
0000h to FFFFh
RW
One-shot timer mode Pulse width modulation mode (16-bit PWM)
0000h to FFFFh(3, 4)
WO
0000h to FFFEh (3, 5)
WO
Pulse width modulation mode (8-bit PWM)
(High-order address bits) (Low-order address bits)
00h to FEh(3, 6) 00h to FFh(3, 6)
WO
fj: f1, f8, f2n, fC32 NOTES: 1. Read and write this register in 16-bit units. 2. The TAi register counts external pulses or another timer overflows or underflows. 3. Read-modify-write instructions cannot be used to set the TAi register. Refer to Usage Notes for details. 4. When the TAi register is set to 0000h, the counter does not start and a timer Ai interrupt request is not generated. 5. When the TAi register is set to 0000h, the pulse width modulator does not operate and the TAiOUT pin output is held "L". A timer Ai interrupt request is not generated. When the TAi register is set to FFFFh, the pulse width modulator does not operate and the TAiOUT pin output is held "H". A timer Ai interrupt request is not generated. 6. When 8 high-order bits are set to 00h, the pulse width modulator does not operate and the TAiOUT pin output is held "L". A timer Ai interrupt request is not generated. When 8 high-order bits are set to FFh, the pulse width modulator does not operate and the TAiOUT pin output is held "H". A timer Ai interrupt request is not generated.
Figure 15.9
TA0 to TA4 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Up/Down Select Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF
Bit Symbol TA0UD Bit Name
Address 0344h
Function 0: Decrement 1: Increment 0: Decrement 1: Increment 0: Decrement 1: Increment 0: Decrement 1: Increment 0: Decrement 1: Increment
After Reset 00h
RW RW
Timer A0 up/down select bit (2)
TA1UD
Timer A1 up/down select bit (2)
RW
TA2UD
Timer A2 up/down select bit (2)
RW
TA3UD
Timer A3 up/down select bit (2)
RW
TA4UD
Timer A4 up/down select bit (2) Timer A2 two-phase pulse signal processing function select bit (3) Timer A3 two-phase pulse signal processing function select bit (3) Timer A4 two-phase pulse signal processing function select bit (3)
RW
TA2P
0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled 0: Two-phase pulse signal processing function disabled 1: Two-phase pulse signal processing function enabled
WO
TA3P
WO
TA4P
WO
NOTES: 1. Read-modify-write instructions cannot be used to set the UDF register. Refer to Usage Notes for details. 2. This bit is enabled when the MR2 bit in the TAiMR register (i = 0 to 4) is set to 0 (the UDF register causes increment/decrement switching) in event counter mode. 3. Set these bits to 0 when not using the two-phase pulse signal processing function.
Figure 15.10
UDF Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Bit Symbol TA1TGL Bit Name
Address 0343h
Function
b1 b0
After Reset 00h
RW RW
Timer A1 trigger select bits TA1TGH
0 0: Input to the TA1IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA0 overflows selected (1) 1 1: TA2 overflows selected (1)
b3 b2
RW
TA2TGL Timer A2 trigger select bits TA2TGH
0 0: Input to the TA2IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA1 overflows selected (1) 1 1: TA3 overflows selected (1)
b5 b4
RW
RW
TA3TGL Timer A3 trigger select bits TA3TGH
0 0: Input to the TA3IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA2 overflows selected (1) 1 1: TA4 overflows selected (1)
b7 b6
RW
RW
TA4TGL Timer A4 trigger select bits TA4TGH
0 0: Input to the TA4IN pin selected 0 1: TB2 overflows selected (1) 1 0: TA3 overflows selected (1) 1 1: TA0 overflows selected (1)
RW
RW
NOTE: 1. Overflow or underflow.
Figure 15.11
TRGSR Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Bit Symbol TA0S Bit Name
Address 0340h
Function 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
After Reset 00h
RW RW
Timer A0 count start bit
TA1S
Timer A1 count start bit
RW
TA2S
Timer A2 count start bit
RW
TA3S
Timer A3 count start bit
RW
TA4S
Timer A4 count start bit
RW
TB0S
Timer B0 count start bit
RW
TB1S
Timer B1 count start bit
RW
TB2S
Timer B2 count start bit
RW
Figure 15.12
TABSR Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 170 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
One-Shot Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF
Bit Symbol TA0OS Bit Name
Address 0342h
Function 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: In an idle state 1: Timer starts 0: Z-phase input disabled 1: Z-phase input enabled
b7 b6
After Reset 00h
RW RW
Timer A0 one-shot start bit (1)
TA1OS
Timer A1 one-shot start bit (1)
RW
TA2OS
Timer A2 one-shot start bit (1)
RW
TA3OS
Timer A3 one-shot start bit (1)
RW
TA4OS
Timer A4 one-shot start bit (1)
RW
TAZIE
Z-phase input enable bit
RW
TA0TGL Timer A0 trigger select bits TA0TGH
0 0: Input to the TA0IN pin selected 0 1: TB2 overflows selected (2) 1 0: TA4 overflows selected (2) 1 1: TA1 overflows selected (2)
RW
RW
NOTES: 1. Read as 0. 2. Overflow or underflow.
Figure 15.13
ONSF Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 15.1
Port P7_0(2) P7_2 P7_4 P7_6 P8_0
15. Timer A
TAiOUT Pin Settings in Output Mode (i = 0 to 4)
Bit Setting Function TA0OUT TA1OUT TA2OUT TA3OUT TA4OUT - - PSC_4 = 0 - - PSC Register PSL1, PSL2 Registers PSL1_0 = 1 PSL1_2 = 1 PSL1_4 = 0 PSL1_6 = 1 PSL2_0 = 0 PS1, PS2 Registers(1) PS1_0 = 1 PS1_2 = 1 PS1_4 = 1 PS1_6 = 1 PS2_0 = 1
NOTES: 1. Set registers PS1and PS2 after setting registers PSC, PSL1, and PSL2. 2. P7_0 is an N-channel open drain output port.
Table 15.2
Port P7_0 P7_1 P7_2 P7_3 P7_4 P7_5 P7_6 P7_7 P8_0 P8_1
TAiIN and TAiOUT Pin Settings in Input Mode (i = 0 to 4)
Bit Setting Function TA0OUT TA0IN TA1OUT TA1IN TA2OUT TA2IN TA3OUT TA3IN TA4OUT TA4IN PD7, PD8 Registers PD7_0 = 0 PD7_1 = 0 PD7_2 = 0 PD7_3 = 0 PD7_4 = 0 PD7_5 = 0 PD7_6 = 0 PD7_7 = 0 PD8_0 = 0 PD8_1 = 0 PS1, PS2 Registers PS1_0 = 0 PS1_1 = 0 PS1_2 = 0 PS1_3 = 0 PS1_4 = 0 PS1_5 = 0 PS1_6 = 0 PS1_7 = 0 PS2_0 = 0 PS2_1 = 0
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 172 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
15.1.1
Timer Mode
In timer mode, the timer counts an internally generated count source. Table 15.3 lists specifications of timer mode. Figure 15.14 shows a timer mode operation (Timer A). Table 15.3
Count source Count operation
Specifications of Timer Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. n+1 fj fj: count source frequency n: setting value of the TAi register (i = 0 to 4), 0000h to FFFFh
Counter cycle Count start condition Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
The TAiS bit in the TABSR register is set to 1 (count starts) The TAiS bit is set to 0 (count stops) Input for gate function Pulse output A read from the TAi register returns a counter value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2) * Gate function A signal applied to the TAiIN pin determines whether the count starts or stops. * Pulse output function The polarity of the TAiOUT pin is inverted whenever the timer underflows. The TAiOUT pin outputs an "L" signal while the TAiS bit is 0 (count stops).
Interrupt request generation timing When the timer underflows
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
FFFFh n Contents of the counter n = contents of the reload register
Count starts
Underflow
Underflow
Reload
Count stops
Reload
0000h TAiS bit in the TABSR register IR bit in the TAiIC register TAiOUT pin (output) 1 0 1 0 "H" "L" (Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode). Bits MR2 and MR1 are set to 00b (gate function disabled). Set to 0 by an interrupt request acknowledgement or by a program
i = 0 to 4
Figure 15.14
Operation in Timer Mode (Timer A)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
15.1.2
Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulse input. Timers A2, A3, and A4 can count externally generated two-phase signals. Table 15.4 lists specifications of event counter mode when not handling two-phase pulse signals. Table 15.5 lists specifications of event counter mode when handling two-phase pulse signals with timers A2, A3, and A4. Figure 15.15 shows a event counter mode operation when not handling two-phase pulse signals. Figure 15.16 shows a event counter mode operation when handling two-phase pulse signals with timers A2, A3, and A4. Table 15.4
Count source
Specifications of Event Counter Mode When Not Handling Two-Phase Pulse Signals
Item Specification * External signal applied to the TAiIN pin (i = 0 to 4) (valid edge is selectable by a program) * Timer B2 overflows or underflows * Timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0) * Timer Ak overflows or underflows (k = i + 1 except k = 0 if i = 4) * Count direction (increment or decrement) can be selected by external signal or by a program. * Reload/Free-run type can be selected. Reload function: The contents of the reload register are reloaded into the counter and the count continues when the timer underflows or overflows. Free-running function: The counter continues running without reloading when the timer underflows or overflows. (FFFFh - n + 1): when incrementing n + 1: when decrementing n: setting value of the TAi register, 0000h to FFFFh The TAiS bit in the TABSR register is set to 1 (count starts) The TAiS bit is set to 0 (count stops) Count source input Pulse output, or input to select the count direction A read from the TAi register returns a counter value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(1) Pulse output function The polarity of the TAiOUT pin is inverted whenever the timer overflows or underflows. The TAiOUT pin outputs "L" signal while the TAiS bit is 0 (count stops).
Count operation
Number of counting
Count start condition Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
Interrupt request generation timing When the timer overflows or underflows
Selectable function
NOTE: 1. Wait for one or more count source cycles to write after the count starts.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Overflow FFFFh Decrement to increment Count starts Underflow Count stops Count resumes Reload
n Contents of the counter n = contents of the reload register
Reload
0000h Input to TAiIN pin TAiS bit in the TABSR register TAiUD bit in the UDF register IR bit in the TAiIC register i = 0 to 4 "H" "L" 1 0 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program Set to 1 by a program
(Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode) The MR1 bit is set to 1 (rising edges of an external signal counted) The MR2 bit is set to 0 (UDF register setting) Bits TCK1 to TCK0 bit are set to 00b (reload)
Figure 15.15
Operation in Event Counter Mode When Not Handling Two-Phase Pulse Signals
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 15.5
15. Timer A
Specifications of Event Counter Mode When Handling Two-Phase Pulse Signals on Timers A2, A3, and A4
Item Specification Two-phase pulse signals applied to pins TAiIN and TAiOUT (i = 2 to 4) * Count direction (increment or decrement) is set by a two-phase pulse signal. * Reload/Free-run type can be selected. Reload function: The contents of the reload register are reloaded into the counter and the count continues when the timer underflows or overflows. Free-running function: The counter continues running without reloading when the timer underflows or overflows. (FFFFh - n + 1): when incrementing n + 1: for decrementing n: setting value of the TAi register, 0000h to FFFFh The TAiS bit in the TABSR Register is set to 1 (count starts) The TAiS bit is set to 0 (count stops) Two-phase pulse input Two-phase pulse input A read from the TAi register returns a counter value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(1) * Normal processing operation (Timers A2 and A3) While a high-level ("H") signal is applied to the TAjOUT pin (j = 2, 3), the timer increments a counter value at the rising edge of the TAjIN pin or decrements a counter value at the falling edge. * Multiply-by-4 processing operation (Timers A3 and A4) The timer increments the counter value in the following timings: -at the rising edge of TAkIN while TAkOUT is "H" (k = 3, 4) -at the falling edge of TAkIN while TAkOUT is "L" -at the rising edge of TAkOUT while TAkIN is "L" -at the falling edge of TAkOUT while TAkIN is "H" The timer decrements the counter in the following timings: -at the rising edge of TAkIN while TAkOUT is "L" -at the falling edge of TAkIN while TAkOUT is "H" -at the rising edge of TAkOUT while TAkIN is "H" -at the falling edge of TAkOUT while TAkIN is "L" * Counter reset by a Z-phase pulse signal input (Timer A3) The counter value is cleared to 0 by a Z-phase pulse signal input
Count source Count operation
Number of counting
Count start condition Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
Interrupt request generation timing When the timer overflows or underflows
Selectable function(2)
NOTES: 1. Wait for one or more count source cycles to write after the count starts. 2. Any operation can be selected for timer A3. Timer A2 is used only for the normal processing operation. Timer A4 is used only for the multiply-by-4 operation.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Normal processing operation (Timer A2 and timer A3) While an "H" is applied to the TAjOUT pin (j = 2, 3), the counter increments at the rising edge of the TAjIN pin and decrements at the falling edge. TAjOUT
TAjIN

Counter value IR bit in the TAjIC register Counter value IR bit in the TAjIC register Set to 0 by an interrupt request acknowledgement or by a program. Multiply-by-4 processing operation (Timer A3 and timer A4) The counter increments at the following timings: -at the rising edge of TAkIN while TAkOUT is "H" -at the falling edge of TAkIN while TAkOUT is "L" -at the rising edge of TAkOUT while TAkIN is "L" -at the falling edge of TAkOUT while TAkIN is "H" The counter decrements at the following timings: -at the rising edge of TAkIN while TAkOUT is "L" -at the falling edge of TAkIN while TAkOUT is "H" -at the rising edge of TAkOUT while TAkIN is "H" -at the falling edge of TAkOUT while TAkIN is "L" m m+1 m+2 m+1 m m-1 Set to 0 by an interrupt request acknowledgement or by a program. 1 0 FFFF m-1 m m+1 m m+1 m+2 m+1 m m-1 1 0 FFFF FFFE FFFF 0
TAkOUT
TAkIN

Counter value IR bit in the TAkIC register Counter value IR bit in the TAkIC register Set to 0 by an interrupt request acknowledgement or by a program. : increment :decrement m m+1 m+2 m+1 m m-1 Set to 0 by an interrupt request acknowledgement or by a program. 1 0 FFFF m-1 m m+1 m m+1 m+2 m+1 m m-1 1 0 FFFF FFFE FFFF 0
Figure 15.16
Operation in Event Counter Mode When Handling Two-Phase Pulse Signals on Timers A2, A3, and A4
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
15.1.2.1
Counter Reset by Two-Phase Pulse Signal Processing
The counter value of timer can be set to 0 by a Z-phase pulse signal input (counter reset) when processing two-phase pulse signals. This function can be used when all the following conditions are met; timer A3 event counter mode, two-phase pulse signal processing, free-running count operation type, and multiply-by-4 processing. The Z-phase pulse signal is applied to the INT2 pin. When the TAZIE bit in the ONSF register is set to 1 (Z-phase input enabled), Z-phase pulse input is enabled to reset the counter. To reset the counter by a Z-phase pulse input, set the TA3 register to 0000h beforehand. A Z-phase pulse input is enabled when the edge of a signal applied to the INT2 pin is detected. The POL bit in the INT2IC register can determine the edge polarity. The Z-phase pulse must have a pulse width of one or more timer A3 count source cycles. Figure 15.17 shows relations between two-phase pulses (A-phase and B-phase) and the Z-phase pulse. Z-phase pulse input resets the counter in the next count source timing followed a Z-phase pulse input. A timer A3 interrupt request is generated twice in a row if a timer A3 overflow or underflow, and the counter reset by an INT2 input occur at the same time. Do not generate a timer A3 interrupt request when this function is used.
TA3OUT (A phase) TA3IN (B phase) Count source INT2(1) (Z phase) Pulse width of one or more count source cycles is required Counter value m m+1 1 2 3 4 5 6
NOTE: 1. Example when the rising edge of INT2 is selected.
Figure 15.17
Relations between Two-Phase Pulses (A-Phase and B-Phase) and Z-Phase Pulse
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
15.1.3
One-Shot Timer Mode
When a trigger occurs, the counter decrements until underflows. Then, the counter is reloaded and stops until the next trigger occurs. Table 15.6 lists specifications of one-shot timer mode. Figure 15.18 shows a one-shot timer mode operation. Table 15.6
Count source Count operation
Specifications of One-Shot Timer Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements When the counter reaches 0000h, the counter is reloaded and stops until the next trigger occurs. If a trigger occurs while counting, the contents of the reload register are reloaded into the counter and the count continues. n times n: setting value of the TAi register (i = 0 to 4), 0000h to FFFFh (but the counter does not run if n = 0000h)
Number of counting Count start condition
A trigger, selectable from the following, occurs while the TAiS bit in the TABSR register is set to 1 (count starts): * the TAiOS bit in the ONSF register is set to 1 (timer starts) * an external trigger is applied to TAiIN pin * timer B2 overflows or underflows, * timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0), * timer Ak overflows or underflows (k = i + 1, except k = 0 if i = 4) * After the counter reaches 0000h and the counter value is reloaded * When the TAiS bit is set to 0 (count stops) Trigger input Pulse output A read from the TAi register returns undefined value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2) Pulse output function "L" is output while the count stops. "H" is output while counting.
Count stop condition
Interrupt request generation timing When the counter reaches 0000h TAiIN pin function TAiOUT pin function Read from timer Write to timer
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Count stops FFFFh m Reload Count starts Count starts Re-trigger input
Count stops
Count stops
Count starts
Contents of the counter m = contents of the reload register
Reload
Reload
0000h 1 0
TAiS bit in the TABSR register Write signal to TAiOS bit in the ONSF register
1 / fj x m One-shot pulse output from the TAiOUT pin "H" "L"
1 / fj x (m + 1)
Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TAiIC register 1 0
fj: Frequency of the count source (f1, f8, f2n (1), fC32) i = 0 to 4 NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). (Conditions) TAiMR register: Bits TMOD1 and TMOD0 are set to 10b (one-shot timer mode). The MR2 bit is set to 0 (The TAiOS bit is enabled).
Figure 15.18
Operation in One-Shot Timer Mode (Timer A)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
15.1.4
Pulse Width Modulation Mode
In pulse width modulation mode, the timer outputs pulse signals of a given width repeatedly. The counter functions as an 8-bit pulse width modulator or 16-bit pulse width modulator. Table 15.7 lists specifications of pulse width modulation mode. Figures 15.19 and 15.20 show examples of a 16-bit pulse width modulator and 8-bit pulse width modulator operations. Table 15.7
Count source Count operation
Specifications of Pulse Width Modulation Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements (The counter functions as the 8-bit or 16-bit pulse width modulator.) The contents of the reload register are reloaded at the rising edge of the PWM pulse and the count continues. The count continues without reloading even if the re-trigger occurs while counting. * "H" width = n / fj n: setting value of the TAi register (i = 0 to 4), 0000h to FFFEh fj: count source frequency * Cycle = (216 - 1) / fj The cycle is fixed to this value * "H" width = n x (m + 1) / fj * Cycle = (28 - 1) x (m + 1) / fj m: setting value of low-order bit address of the TAi register, 00h to FFh n: setting value of high-order bit address of the TAi register, 00h to FEh When a trigger is not used (the MR2 bit in the TAiMR register is 0): Set the TAiS bit in the TABSR register to 1 When a trigger is used (the MR2 bit in the TAiMR register is 1): A trigger, selectable from the following occurs while the TAiS bit in the TABSR register is set to 1(count starts): * an external trigger is applied to TAiIN pin * timer B2 overflows or underflows * timer Aj overflows or underflows (j = i - 1, except j = 4 if i = 0) * timer Ak overflows or underflows (k = i + 1, except k = 0 if i = 4) The TAiS bit is set to 0 (count stops) Trigger input Pulse output A read from the TAi register returns undefined value * A write to the TAi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TAi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2)
16-bit PWM
8-bit PWM
Count start condition
Count stop condition TAiIN pin function TAiOUT pin function Read from timer Write to timer
Interrupt request generation timing At the falling edge of the PWM pulse
NOTES:
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 181 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Count starts 1 / fj x (216 - 1) Count source Input to the TAiIN pin "H" "L" 1 0 1 / fj x m "H" "L" 1 0 No trigger is generated by this signal Set to 1 by a program
Count stops End of 1 cycle
Set to 0 by a program
TAiS bit in the TABSR register PWM pulse output from the TAiOUT pin
Set to 0 by an interrupt request acknowledgement or by a program
IR bit in the TAiIC register
i = 0 to 4 fj: Count source frequency (f1, f8, f2n (1), fC32) m: Setting value of the TAi register (0000h to FFFEh)
When the TAiS bit is set to 0 (count stops) while the TAiOUT output is "H", the TAiOUT output becomes "L" and the IR bit is set to 1 (interrupt requested).
(Conditions) TAi register is set to 0005h. TAiMR register: MR1 bit is set to 1 (rising edge of signal applied to the TAiIN pin) NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 15.19
16-Bit Pulse Width Modulator Operation (Timer A)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 182 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer A
Count starts
End of 1 cycle
Count stops
Count source 1 / fj x (m+1) x (28-1)
Signal applied to TAiIN pin TAiS bit in the TABSR register
"H" "L" 1 0 Set to 1 by a program
Set to 0 by a program
Underflow signal of 8-bit prescaler 1 / fj x (m+1) x n PWM pulse output from TAiOUT pin "H" "L" Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TAiIC register 1 0 When the TAiS bit is set to 0 (count stops) while the TAiOUT output is "H", the TAiOUT output becomes "L" and the IR bit becomes 1 (interrupt requested).
i = 0 to 4 fj: Count source frequency (f1, f8, f2n(1), fC32) n: high-order bits in the TAi register (00h to FEh) m: low-order bits in the TAi register (00h to FFh)
(Conditions) High-order bits in the TAi register are set to 02h. Low-order bits in the TAi register are set to 02h. TAiMR register: The MR1 bit is set to 0 (falling edge of signal applied to the TAiIN pin.) NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. The 8-bit pulse width modulator counts underflow signals of the 8-bit prescaler.
Figure 15.20
8-bit Pulse Width Modulator Operation (Timer A)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 183 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
15.2
Timer B
Timer B contains the following three modes. Bits TMOD1 and TMOD0 in the TBiMR register (i = 0 to 5) determine which mode is used.
* Timer mode: The timer counts the internal count source. * Event counter mode: The timer counts overflows/underflows of another timer, or the external pulses. * Pulse period measurement mode, pulse width measurement mode: The timer measures the pulse period or
pulse width of the external signal. Figure 15.21 shows a block diagram of timer B. Figures 15.22 to 15.26 show the registers associated with timer B. Table 15.8 shows TBiIN pin settings (i = 0 to 5).
High-order bits of data bus
Clock source select TCK1 and TCK0 00 f1 f8 01 f2n(1) 10 fC32 11 TBj overflow(2) Polarity switching TBiIN and edge pulse 1 0 TMOD1 and TMOD0 00: Timer mode 10: Pulse period and pulse width measurement mode TCK1 01: Event counter mode TBiS
Low-order bits of data bus
8 low-order bits Reload register 8 high-order bits
Counter
Counter reset circuit
i= 0 to 5 j = i - 1, except j = 2 if i = 0, j = 5 if i = 3. NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Overflow signal or underflow signal. TCK1 and TCK0, TMOD1 and TMOD0: Bits in the TBiMR register TBiS: Bit in the TABSR register or the TBSR register
TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5
Addresses 0351h 0350h 0353h 0352h 0355h 0354h 0311h 0310h 0313h 0312h 0315h 0314h
TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4
Figure 15.21
Timer B Block Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 184 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
Timer Bi Mode Register (i = 0 to 5)(Timer Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TB0MR to TB5MR
Bit Symbol TMOD0
Address 035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Name Function
After Reset 00XX 0000b
RW RW
Operating mode select bits TMOD1
b1 b0
0 0: Timer mode RW
MR0 Disabled in timer mode. Can be set to either 0 or 1 MR1 Registers TB0MR and TB3MR: Set to 0 in timer mode. MR2 Registers TB1MR, TB2MR, TB4MR, and TB5MR: Unimplemented. Write 0. Read as undefined value. Disabled in timer mode. Write 0. Read as undefined value.
b7 b6
RW
RW
RW
-
MR3
-
TCK0 Count source select bits TCK1
0 0: f1 0 1: f8 1 0: f2n(1) 1 1: fC32
RW
RW
NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.22
TB0MR to TB5MR Registers in Timer Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
Timer Bi Mode Register (i = 0 to 5)(Event Counter Mode)
b7 b6 b5 b4 b3 b2 b1 b0
0
01
Symbol TB0MR to TB5MR
Bit Symbol TMOD0
Address 035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Name Function
After Reset 00XX 0000b
RW RW
Operating mode select bits TMOD1
b1 b0
0 1: Event counter mode RW
b3 b2
MR0 Count polarity select bits (1) MR1 Registers TB0MR and TB3MR: Set to 0 in event counter mode. MR2
0 0: Falling edges of an external signal counted 0 1: Rising edges of an external signal counted 1 0: Falling and rising edges of an external signal counted 1 1: Do not set to this value
RW
RW
RW
Registers TB1MR, TB2MR, TB4MR, and TB5MR: Unimplemented. Write 0. Read as undefined value. Disabled in event counter mode. Write 0. Read as undefined value. Disabled in event counter mode. Can be set to either 0 or 1 Event clock select bit 0: Signal applied to the TBiIN pin 1: TBj overflows or underflows (2)
-
MR3
-
TCK0
RW
TCK1
RW
NOTES: 1. Bits MR1 and MR0 are enabled when the TCK1 bit is set to 0. Bits MR1 and MR0 can be set to either 0 or 1 when the TCK1 bit is set to 1. 2. j = i - 1, except j = 2 if i = 0 and j = 5 if i = 3.
Figure 15.23
TB0MR to TB5MR Registers in Event Counter Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
Timer Bi Mode Register (i = 0 to 5) (Pulse Period Measurement Mode, Pulse Width Measurement Mode)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol TB0MR to TB5MR
Bit Symbol TMOD0
Address 035Bh, 035Ch, 035Dh, 031Bh, 031Ch, 031Dh
Bit Name Function
After Reset 00XX 0000b
RW RW
Operating mode select bits TMOD1
b1 b0
1 0: Pulse period measurement mode Pulse width measurement mode
RW
MR0 Measurement mode select bits(1) MR1
b3 b2
0 0: Pulse period measurement 1 0 1: Pulse period measurement 2 1 0: Pulse width measurement 1 1: Do not set to this value
RW
RW
Registers TB0MR and TB3MR: Set to 0 in pulse period measurement mode, pulse width measurement mode. MR2 Registers TB1MR, TB2MR, TB4MR, and TB5MR: Unimplemented. Write 0. Read as undefined value. Timer Bi overflow flag(2) 0: No overflow has occurred 1: Overflow has occurred (3)
b7 b6
RW
-
MR3
RO
TCK0 Count source select bits TCK1
0 0: f1 0 1: f8 1 0: f2n(4) 1 1: fC32
RW
RW
NOTES: 1. Bits MR1 and MR0 determine the following measurement modes: Pulse period measurement 1 (bits MR1 and MR0 are set to 00b): Measures the width between the falling edges of a pulse Pulse period measurement 2 (bits MR1 and MR0 bits are set to 01b): Measures the width between the rising edges of a pulse Pulse width measurement (bits MR1 and MR0 bits are set to 10b): Measures the width between a falling edge and a rising edge of a pulse, and between a rising edge and a falling edge of a pulse 2. The MR3 bit is undefined when reset. 3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts). 4. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits TCK1 and TCK0 to 10b.
Figure 15.24
TB0MR to TB5MR Registers in Pulse Period Measurement Mode, Pulse Width Measurement Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
Timer Bi Register(1) (i = 0 to 5)
b15 b8 b7 b0
Symbol TB0 to TB2 TB3 to TB5
Mode Timer Mode
Address 0351h - 0350h, 0353h - 0352h, 0355h - 0354h 0311h - 0310h, 0313h - 0312h, 0315h - 0314h
Function If a count source frequency is fj, and the setting value of the TBi register is n, the counter cycle is (n+1) / fj. If the setting value of the TBi register is n, the count times are (n+1)(2) Increment the counter between one valid edge and another valid edge of a pulse applied to the TBiIN pin
After Reset Undefined Undefined
RW RW
Setting Range 0000h to FFFFh
Event Counter Mode Pulse Period Measurement Mode, Pulse Width Measurement Mode
0000h to FFFFh
RW
-
RO
NOTES: 1. Read and write this register in 16-bit units. 2. Timer Bi counts overflows/underflows of another timer, or the external pulses.
Figure 15.25
TB0 to TB5 Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 188 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Bit Symbol TA0S Bit Name
Address 0340h
Function 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
After Reset 00h
RW RW
Timer A0 count start bit
TA1S
Timer A1 count start bit
RW
TA2S
Timer A2 count start bit
RW
TA3S
Timer A3 count start bit
RW
TA4S
Timer A4 count start bit
RW
TB0S
Timer B0 count start bit
RW
TB1S
Timer B1 count start bit
RW
TB2S
Timer B2 count start bit
RW
Timer B3, B4, B5 Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TBSR
Bit Symbol - (b4-b0) TB3S Bit Name
Address 0300h
Function
After Reset 000X XXXXb
RW - 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
Unimplemented. Write 0. Read as undefined value. Timer B3 count start bit
RW
TB4S
Timer B4 count start bit
RW
TB5S
Timer B5 count start bit
RW
Figure 15.26
TABSR Register, TBSR Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 189 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 15.8
Port P7_1 P9_0 P9_1 P9_2 P9_3 P9_4
15. Timer B
TBiIN Pin Settings (i = 0 to 5)
Bit Setting Function TB5IN TB0IN TB1IN TB2IN TB3IN TB4IN PD7, PD9(1) Registers PD7_1 = 0 PD9_0 = 0 PD9_1 = 0 PD9_2 = 0 PD9_3 = 0 PD9_4 = 0 PS1, PS3(1) Registers PS1_1 = 0 PS3_0 = 0 PS3_1 = 0 PS3_2 = 0 PS3_3 = 0 PS3_4 = 0
NOTE: 1. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 190 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
15.2.1
Timer Mode
In timer mode, the timer counts an internally generated count source. Table 15.9 lists specifications of timer mode. Figure 15.27 shows a timer mode operation (Timer B). Table 15.9
Count source Count operation
Specifications of Timer Mode
Item f1, f8, f2n(1), fC32 Specification * Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. n+1 fj fj: count source frequency n: setting value of the TBi register (i=0 to 5), 0000h to FFFFh
Counter cycle Count start condition Count stop condition TBiIN pin function Read from timer Write to timer
The TBiS bit in the TABSR or TBSR register is set to 1 (count starts) The TBiS bit is set to 0 (count stops) Programmable I/O port A read from the TBi register returns a counter value. * A write to the TBi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TBi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(2)
Interrupt request generation timing When the timer underflows
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Wait for one or more count source cycles to write after the count starts.
FFFFh n Contents of the counter n = contents of the reload register
Count starts Underflow Count stops
Count resumes Underflow
Reload
Reload
TBiS bit in the TABSR or TBSR register IR bit in the TBiIC register i = 0 to 5
0000h 1 0 1 0 Set to 0 by an interrupt request acknowledged or by a program
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 00b (timer mode).
Figure 15.27
Operation in Timer Mode (Timer B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 191 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
15.2.2
Event Counter Mode
In event counter mode, the timer counts overflows/underflows of another timer, or the external pulses. Table 15.10 lists specifications of event counter mode. Figure 15.28 shows an event counter mode operation. Table 15.10
Count source
Specifications of Event Counter Mode
Item Specification * External signal applied to the TBiIN pin (i = 0 to 5) (valid edge can be selected by a program) * TBj overflows or underflows (j = i - 1, except j = 2 if i = 0, j = 5 if i = 3) * Counter decrements When the timer underflows, the contents of the reload register are reloaded into the counter and the count continues. (n + 1) times n: Setting value of the TBi register 0000h to FFFFh The TBiS bit in the TABSR or TBSR register is set to 1 (count starts) The TBiS bit is set to 0 (count stops) Count source input A read from the TBi register returns a counter value. * A write to the TBi register while the count is stopped: The value is written to both the reload register and the counter. * A write to the TBi register while counting: The value is written to the reload register (It is transferred to the counter at the next reload timing).(1)
Count operation
Number of counting Count start condition Count stop condition TBiIN pin function Read from timer Write to timer
Interrupt request generation timing When the timer underflows
NOTE: 1. Wait for one or more count source cycles to write after the count starts.
FFFFh n
Count starts
Underflow
Count resumes Count stops
Reload Contents of the counter n = contents of the reload register
0000h Input to the TBiIN pin TBiS bit in the TABSR or TBSR regsiter IR bit in the TBiIC regsiter "H" "L" 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program
i = 0 to 5
(Condition) TBiMR register: Bits TMOD1 and TMOD0 are set to 01b (event counter mode) Bits MR1 and MR0 are set to 00b (count the falling edge of the external signal) The TCK1 bit is set to 0 (signal input to TBiIN pin)
Figure 15.28
Operation in Event Counter Mode (Timer B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 192 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
15.2.3
Pulse Period Measurement Mode, Pulse Width Measurement Mode
In pulse period measurement mode and pulse width measurement mode, the timer measures pulse period or pulse width of the external signal. Table 15.11 shows specifications in pulse period measurement mode and pulse width measurement mode. Figure 15.29 shows a pulse period measurement operation. Figure 15.30 shows a pulse width measurement operation. Table 15.11
Count source Count operation
Specifications of Pulse Period Measurement Mode, Pulse Width Measurement Mode
Item f1, f8, f2n(1), fC32 Specification * Counter increments The counter value is transferred to the reload register when the valid edge of a pulse is detected. Then the counter becomes 0000h and the count continues. The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 1 (count starts) The TBiS bit is set to 0 (count stops)
Count start condition Count stop condition
Interrupt request generation timing * When the valid edge of a pulse is input(2) * When the timer overflows(3) The MR3 bit in the TBiMR register is set to 1 (overflow) simultaneously. TBiIN pin function Read from timer Write to timer Pulse input A read from the TBi register returns the contents of the reload register (measurement results)(4) The TBi register cannot be written
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. An interrupt request is not generated when the first valid edge is input after the count starts. 3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit becomes 1, while the TBiS bit is set to 1. 4. A value read from the TBi register is undefined until the second valid edge is detected after the count starts.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 193 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
Pulse input to TBiIN pin(2)
"H" "L"
1st valid edge
2nd valid edge
FFFFh Contents of the counter (n = contents of the reload register) n
(note 1) 0000h
TBiS bit in the TABSR register or TBSR register IR bit in the TBiIC register Transfer timing from counter to reload register TBi register i = 0 to 5
1 0 1 0
Set to 0 by an interrupt request acknowledgement or by a program
Transfer (undefined value)
Transfer (measured value n)
Undefined value
n
NOTES: 1. Counter is reset due to the completion of the measurement. 2. If an overflow and a valid edge input occur simultaneously, an interrupt request is generated only once, which results in the valid edge not being recognized. Do not let an overflow occur.
Figure 15.29
Operation in Pulse Period Measurement Mode (Timer B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 194 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
15. Timer B
1st valid edge Pulse input to TBiIN pin "H" "L" FFFFh n Contents of the counter n = contents of the reload register 10000h + n
2nd valid edge
(note1) 0000h
(note2)
(note1)
TBiS bit in the TABSR or TBSR register MR3 bit in the TBiMR register
1 0 (note 3) 1 0 1 0 Set to 0 by an interrupt acknowledgement or by a program (note 4) (note 4)
IR bit in the TBiIC register
Transfer timing from counter to reload register TBi register i = 0 to 5
Transfer (undefined value) Undefined value
Transfer (measured value n) n
NOTES: 1. Counter is reset due to the completion of the measurement. 2. Overflow 3. To set the MR3 bit to 0 (no overflow), wait for one or more count source cycles to write to the TBiMR register after the MR3 bit becomes 1 (overflow), while the TBiS bit in TABSR or TBSR register is set to 1 (count starts). 4. Determine whether an interrupt source is a valid edge input or an overflow by reading the port level in the TBi interrupt routine.
Figure 15.30
Operation in Pulse Width Measurement Mode (Timer B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 195 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
16. Three-Phase Motor Control Timer Function
The PWM waveform can be output by using timers B2, A1, A2, and A4. Timer B2 is used for the carrier wave control, and timers A4, A1, and A2 for the U-, V-, and W-phase PWM control. Table 16.1 lists specifications of the three-phase motor control timer functions. Table 16.2 lists pin settings. Figure 16.1 shows a block diagram. Figures 16.2 to 16.10 show registers associated with the three-phase motor control timer function. Table 16.1
Control method Modulation modes Active level Timers to be used
Specifications of Three-Phase Motor Control Timers
Item Three-phase full wave method * Triangular wave modulation mode * Sawtooth wave modulation mode Selectable either active High or active Low * Timer B2 (Carrier wave cycle control: used in timer mode) * Timers A4, A1, and A2 (U-, V-, W-phase PWM control: used in one-shot timer mode): * Prevention function against upper and lower arm short circuit caused by program errors * Arm short circuit prevention function using dead time timer * Forced cutoff function by NMI input Specification
Short circuit prevention features
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 196 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
TB2 register PWCON
0 1
Reload register Timer B2 INV00 Timer A1 reload control signal INV01 INV11
ICTB2 register Counter Timer B2 interrupt request INV03 DQ T R
1 0
Timer A1 reload control signal
INV02 Interrupt request
f1
INV10 Write signal to TB2 register
Value written to INV03 bit Write signal to INV03 bit "1" write signal to INV07 bit Write signal to IDBi register INV06 INV06 SQ R Transfer trigger(1) DTT register RESET NMI INV05
INV02 INV04 U-phase W-phase V-phase upper/ lower arm short circuit detection signal
V-Phase Output Control Circuit
Dead timer timer start trigger
Start trigger INV16
0 1
Reload register Dead timer timer
fDT
INV15
Data Bus Timer A1 reload control signal INV11 DQ TQ DQ TA1 register TA11 register DV1 Data Bus DQ T DQ T DQ T
0 1
0 1
INV14
V
INV14
Three-phase output D Q shift register DV0 Data Bus
V
DQ T Dead timer timer start trigger D TQ
Start trigger
Reload register Timer A1 DQ DVB1 Data Bus Transfer trigger
DQ T
DQ T fDT Three-phase output shift register
D TQ
f1
DQ DVB0
Start trigger
DTT register
U-Phase Output Control Circuit
Transfer trigger Start trigger DTT register
U U W W
W-Phase Output Control Circuit
INV00 to INV07: bits in the INVC0 register INV10 to INV15: bits in the INVC1 register DVi, DVBi: bits in the IDBi register (i = 0, 1) PWCON: bit in the TB2SC register NOTE: 1. When the INV06 bit is set to 0 (triangular wave modulation mode), a transfer trigger is generated at the first timer B2 underflow after writing to the IDBi register (i = 0, 1).
Figure 16.1
Three-Phase Motor Control Timer Function Block Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 197 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol INVC0
Bit Symbol Bit Name
Address 0308h
Function
After Reset 00h
RW
INV00 ICTB2 count condition select bits INV01
0 0: Timer B2 underflow 0 1: 1 0: Timer B2 underflow at the rising edge of the timer A1 reload control signal(2) (every odd-numbered timer B2 underflow) 1 1: Timer B2 underflow at the falling edge of the timer A1 reload control signal(2) (every even-numbered timer B2 underflow) 0: Three-phase motor control timer function not used 1: Three-phase motor control timer function used(4,5) 0: Three-phase motor control timer output disabled(5,6) 1: Three-phase motor control timer output enabled 0: Simultaneous turn-on enabled 1: Simultaneous turn-on disabled 0: Not detected 1: Detected (7) 0: Triangular wave modulation mode 1: Sawtooth wave modulation mode Transfer trigger is generated when the INV07 bit is set to 1. Trigger for the dead time timer is also generated when the INV06 bit is set to 1. This bit is read as 0.
b1 b0
RW
RW
INV02
Three-phase motor control timer function enable bit(3) Three-phase motor control timer output control bit Upper and lower arm simultaneous turn-on disable bit Upper and lower arm simultaneous turn-on detect flag Modulation mode select bit
RW
INV03
RW
INV04
RW
INV05
RO
INV06
RW
INV07
Software trigger select bit
RW
NOTES: 1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set bits INV06 and INV02 to INV00 while timers A1,A2, A4, and B2 are stopped. 2. Set the INV01 bit to 1 after setting a value to the ICTB2 register. Also, when the INV01 bit is set to 1, set the timer A1 count start bit to 1 prior to the first timer B2 underflow. 3. Set pins after the INV02 bit is set to 1. Refer to the table, Pin settings when using three-phase motor control timer function . 4. Set the INV02 bit to 1 to operate the dead time timer, U-, V-, and W-phase output control circuits, and ICTB2 counter. 5. When the INV03 bit is set to 0 and the INV02 bit to 1, pins U, U, V, V, W, and W (including when other output functions are assiged to these pins) are all placed in high-impedance states. 6. The INV03 bit becomes 0 when one of the following occurs: -Reset -The both upper and lower arms output the active level signals at the same time while the INV04 bit is set to 1 -The INV03 bit is set to 0 by a program -Signal applied to the NMI pin changes from "H" to "L" (while an "L" is applied to the NMI pin, the INV03 bit cannot be set to 1). 7. The INV05 bit cannot be set to 1 by a program. To set the INV05 bit to 0, write a 0 to the INV04 bit.
Figure 16.2
INVC0 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 198 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol INVC1
Bit Symbol INV10 Bit Name Timers A1, A2, and A4 start trigger select bit
Address 0309h
Function
After Reset 00h
RW RW
0: Timer B2 underflow 1: Timer B2 underflow and a write to the TB2 register 0: Timers A11, A21, and A41 not used (Three-phase mode 0) 1: Timers A11, A21, and A41 used (Three-phase mode 1) 0: f1 1: f1 divided-by-2 0: Timer B2 underflow occurred an even number of times 1: Timer B2 underflow occurred an odd number of times 0: Active Low 1: Active High 0: Dead time enabled 1: Dead time disabled 0: Falling edge of one-shot pulse of timer (A4, A1, and A2 (3)) 1: Rising edge of the three-phase output shift register (U-, V-, W-phase) Set to 0
INV11
Timers A11, A21, and A41 control bit Dead time timer count source (fDT) select bit Carrier wave rise/fall detect flag(2)
RW
INV12
RW
INV13
RO
INV14
Active level control bit
RW
INV15
Dead time disable bit
RW
INV16
Dead time timer trigger select bit
RW
- (b7)
Reserved bit
RW
NOTES: 1. Set the INVC1 register after the PRC1 bit in the PRCR register is set to 1 (write enable). Set the INVC1 register while timers A1, A2, A4, and B2 are stopped. 2. The INV13 bit is enabled only when the INV06 bit is set to 0 (triangular wave modulation mode) and the INV11 bit to 1. 3. If the following conditions are all met, set the INV16 bit to 1. - The INV15 bit is set to 0 - Bits Dij (i = U, V or W, j = 0, 1) and DiBj in the IDBj register always have different values when the INV03 bit in the INVC0 register is set to 1 (three-phase control timer output enabled). (The upper arm and lower arm always output opposite level signals at any time except dead time.) If any of the above conditions is not met, set the INV16 bit to 0.
Figure 16.3
INVC1 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 199 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TB2MR
Bit Symbol TMOD0 Bit Name
Address 035Dh
Function
After Reset 00XX 0000b
RW RW
Operating mode select bits TMOD1
Set to 00b (timer mode) to use the three-phase motor control timer function RW
MR0 Disabled to use the three-phase motor control timer function. Can be set to either 0 or 1. MR1
RW
RW
MR2
Set to 0 to use the three-phase motor control timer function Unimplemented. Write 0. Read as undefined value.
RW
MR3
-
TCK0 Count source select bits TCK1 Set to 00b (f1) to use the three-phase motor control timer function
RW
RW
Figure 16.4
TB2MR Register when Using Three-Phase Motor Control Timer Function
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 200 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i = 1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
010010
Symbol TA1MR, TA2MR, TA4MR
Bit Symbol TMOD0 Bit Name
Address 0357h, 0358h, 035Ah
Function
After Reset 00h
RW RW
Operating mode select bits TMOD1
- (b2)
Set to 10b (one-shot timer mode) to use the three-phase motor control timer function RW
Reserved bit
Set to 0 Set to 0 to use the three-phase motor control timer function Set to 1 (selected by the TRGSR register) to use the three-phase motor control timer function
RW
MR1
External trigger select bit
RW
MR2
Trigger select bit
RW
MR3
Set to 0 to use the three-phase motor control timer function
RW
TCK0 Count source select bits TCK1 Set to 00b (f1) to use the three-phase motor control timer function
RW
RW
Figure 16.5
TA1MR, TA2MR, and TM4MR Registers when Using Three-Phase Motor Control Timer Function
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 201 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR
Bit Symbol TA1TGL Bit Name
Address 0343h
Function
After Reset 00h
RW RW
Timer A1 trigger select bits TA1TGH
Set to 01b (TB2 underflow) to use the V-phase output control circuit
RW
TA2TGL Timer A2 trigger select bits TA2TGH Set to 01b (TB2 underflow) to use the W-phase output control circuit
RW
RW
TA3TGL Timer A3 trigger select bits TA3TGH
b5 b4
0 0: Input to the TA3IN pin selected 0 1: TB2 overflow selected (1) 1 0: TA2 overflow selected (1) 1 1: TA4 overflow selected (1)
RW
RW
TA4TGL Timer A4 trigger select bits TA4TGH Set to 01b (TB2 underflow) to use the U-phase output control circuit
RW
RW
NOTE: 1. Overflow or underflow.
Figure 16.6
TRGSR Register when Using Three-Phase Motor Control Timer Function
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 202 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Timer B2 Special Mode Register(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Symbol TB2SC
Bit Symbol Bit Name
Address 035Eh
Function
After Reset 00h
RW
PWCON
Timer B2 reload timing switch bit
0: Timer B2 underflow 1: Timer B2 underflow at the rising edge of the timer A1 reload control signal (every odd-numbered timer B2 underflow) Set to 0
RW
- (b7-b1)
Reserved bits
RW
NOTE: 1. Set the TB2SC register after the PRC1 bit in the PRCR register is set to 1 (write enable).
Timer B2 Interrupt Generation Frequency Set Counter (1, 2)
b7 b6 b5 b4 b3 b0
Symbol ICTB2
Function
Address 030Dh
After Reset Undefined
Setting Range RW
- When the INV01 bit in the INVC0 register is set to 0 (the ICTB2 counter increments every timer B2 underflows) and a setting value is n, the timer B2 interrupt request is generated every n-th timer B2 underflow. - When bits INV01 and INV00 are set to 10b (the ICTB2 counter increments when the timer B2 underflow at the rising edge of the timer A1 reload control signal) and a setting value is n, the first timer B2 interrupt request is generated at the (2n-1)th timer B2 underflow. From the 2nd time on, the request is generated every 2n-th timer B2 underflow. - When bits INV01 and INV00 are set to 11b (the ICTB2 counter increments when the timer B2 underflow occurs at the falling edge of the timer A1 reload control signal) and a setting value is n; * When n > 1, the first timer B2 interrupt request is generated at the (2n-2)th timer B2 underflow. From the 2nd time on, the request is generated every 2n-th timer B2 underflow. * When n = 1, the timer B2 interrupt request is generated every 2n-th timer B2 underflow. Unimplemented. Write 0. Read as undefined value.
1 to 15
WO
-
NOTES: 1. Read-modify-write instructions cannot be used to set the ICTB2 register. Refer to Usage Notes for details. 2. If the INV01 bit in the INVC0 register is set to 1, set the ICTB2 register while the TB2S bit is set to 0 (count stops). If the INV01 bit is set to 0, do not set the ICTB2 register when timer B2 underflows, regardless of the TB2S bit setting.
Figure 16.7
TB2SC Register, ICTB2 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 203 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Timer B2 Register(1)
b15 b8 b7 b0
Symbol TB2
Function
Address 0355h - 0354h
After Reset Undefined
Setting Range 0000h to FFFFh RW RW
If a setting value is n, f1 is divided by n+1. Timers A1, A2, and A4 start every time timer B2 underflows.
NOTE: 1. Read and write this register in 16-bit units.
Dead Time Timer(1, 2, 3)
b7 b0
Symbol DTT
Function
Address 030Ch
After Reset Undefined
Setting Range RW
This one-shot timer is used to delay the timing for a turn-on signal to be switched to its active level in order to prevent the upper and lower arm short circuit. If a setting value is n, the count source is counted n times after the start trigger occurs, and then the timer stops.
01h to FFh
WO
NOTES: 1. Read-modify-write instructions cannot be used to set the DTT register. Refer to Usage Notes for details. 2. The DTT register setting is enabled when the INV15 bit in the INVC1 register is set to 0 (dead time enabled). No dead time is generated when the INV15 bit is set to 1 (dead time disabled). 3. The INV16 bit in the INVC1 register determines the start trigger of the DTT register. The INV12 bit determines the count source.
Figure 16.8
TB2 Register, DTT Register when Using Three-Phase Motor Control Timer Function
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Timer Ai, Ai1 Register(1, 2, 3, 4, 5) (i = 1, 2, 4)
b15 b8 b7 b0
Symbol TA1, TA2, TA4 TA11, TA21, TA41
Address 0349h - 0348h, 034Bh - 034Ah, 034Fh - 034Eh 0303h - 0302h, 0305h - 0304h, 0307h - 0306h
Function Setting Range
After Reset Undefined Undefined
RW
If a setting value is n, f1 is counted n times after a start trigger occurs, and then the timer stops. Output signal level for each phase changes when timers A1, A2, or A4 stop.
0000h to FFFFh
WO
NOTES: 1. Write these registers in 16-bit units. Read-modify-write instructions cannot be used to set registers TAi and TAi1. Refer to Usage Notes for details. 2. If the TAi or TAi1 register is set to 0000h, the counter does not start and the timer Ai interrupt is not generated. 3. When the INV15 bit in the INVC1 register is set to 0 (dead timer enabled), an output signal is switched to its active level with delay simultaneously with the dead time timer underflow. 4. When the INV11 bit is set to 0 (Timers A11, A21, and A41 not used (three-phase mode 0)), the contents of the TAi register are transferred to the reload register by a timer Ai start trigger. When the INV11 bit is set to 1 (Timers A11, A21, and A41 are used (three-phase mode 1)), the contents of the TAi1 register are transferred by the first timer Ai start trigger, and then contents of the TAi register are transferred by the next timer Ai start trigger. Subsequently, the contents of registers TAi1 and TAi are transferred alternately to the reload register by each timer Ai start trigger. 5. Do not set registers TAi and TAi1 in the timer B2 underflow timing.
Three-Phase Output Buffer Register i(1) (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IDB0, IDB1
Bit Symbol DUi Bit Name Upper arm (U-phase) output buffer i Lower arm (U-phase) output buffer i Upper arm (V-phase) output buffer i Lower arm (V-phase) output buffer i Upper arm (W-phase) output buffer i Lower arm (W-phase) output buffer i
Address 030Ah, 030Bh
Function
After Reset XX11 1111b
RW RW
Set output levels of the three-phase output shift registers. The set value is reflected in each turn-on signal as follows: 0: Active (ON) 1: Inactive (OFF) When read, the contents of the three-phase output shift registers are returned.
DUBi
RW
DVi
RW
DVBi
RW
DWi
RW
DWBi - (b7-b6)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. When values are written to registers IDB0 and IDB1, these values are transferred to the three-phase output shift registers by a transfer trigger. The value written in the IDB0 register becomes the initial output level of each phase when the transfer trigger occurs. The value written in the IDB1 register becomes the next output signal level when the falling edge of the timer A1, A2 and A4 one-shot pulses is detected.
Figure 16.9
TA1, TA2, TA4, TA11, TA21, and TA41 Registers, IDB0, IDB1 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Count Start Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR
Bit Symbol TA0S Bit Name
Address 0340h
Function 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts 0: Count stops 1: Count starts
After Reset 00h
RW RW
Timer A0 count start bit
TA1S
Timer A1 count start bit
RW
TA2S
Timer A2 count start bit
RW
TA3S
Timer A3 count start bit
RW
TA4S
Timer A4 count start bit
RW
TB0S
Timer B0 count start bit
RW
TB1S
Timer B1 count start bit
RW
TB2S
Timer B2 count start bit
RW
Figure 16.10 Table 16.2
Port P7_2 P7_3 P7_4 P7_5 P8_0 P8_1
TABSR Register when Using Three-Phase Motor Control Timer Function Pin Settings when Using Three-Phase Motor Control Timer Function(1)
Bit Setting Function V V W W U U PSC Register PSC_2 = 1 - - - - - PSL1, PSL2, Registers PSL1_2 = 0 PSL1_3 = 1 PSL1_4 = 1 PSL1_5 = 0 PSL2_0 = 1 PSL2_1 = 0 PS1, PS2 Registers(2) PS1_2 = 1 PS1_3 = 1 PS1_4 = 1 PS1_5 = 1 PS2_0 = 1 PS2_1 = 1
NOTES: 1. Set these registers after setting the INV02 bit in the INVC0 register to 1 (three-phase motor control timer function used). 2. Set registers PS1 and PS2 after setting the other registers.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
16.1
Triangular Wave Modulation Mode
In triangular wave modulation mode, one cycle of carrier waveform consists of two timer B2 underflow cycles. A timer Ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer B2 underflow signal as a trigger. Two of the timer Ai one-shot pulses are used to output one cycle of the PWM waveform. Table 16.3 lists specifications and settings of triangular wave modulation mode. Triangular wave modulation mode has two operation modes, three-phase mode 0 and three-phase mode 1. TAi register is used in three-phase mode 0. Every time a timer B2 underflow interrupt occurs, the one-shot pulse width is set in the TAi register. Registers TAi and TAi1 are used in three-phase mode 1. Two different widths of the one-shot pulse can be set in these registers. If a setting value of the ICTB2 register is n, a timer B2 underflow interrupt is generated every n-th or every 2n-th timer B2 underflow to set values in registers TAi and TAi1. Table 16.3
Item INV06 bit INV11 bit Bits INV01 and INV00 PWCON bit ICTB2 register Carrier wave cycle Upper arm active level output width INV13 bit Timer B2 interrupt generation timing
Specifications and Settings of Triangular Wave Modulation Mode
Three-Phase Mode 0 0 0 00b or 01b 0 1 2 x (m + 1) f1
1 x(m+1 - a 2k-1+a2k) f1
Three-Phase Mode 1 0 1 00b 10b 0 or 1 n 2 x (m+1) f1 1 x (m+1 - b +a ) kk f1 Indicates the timer A1 reload control signal state. Every n-th timer B2 underflow Every 2n-th timer B2 underflow Every odd-numbered (2n x j - 1) timer B2 underflow Every evennumbered (2n x j) timer B2 underflow 11b
0 or 1 Timer B2 underflow
Timer B2 reload timing Transfer timing from IDBp register to three-phase output shift register
Timer B2 underflow
* Timer B2 underflow (PWCON = 0) * Timer B2 underflow at the rising edge of the timer A1 reload control signal (PWCON = 1)
When a value is written to the IDBp register (p = 0, 1), the value is transferred only once by the first transfer trigger.
Dead time timer start * At the falling edge of the one-shot pulse of timer A1, A2 and A4 (INV16 = 0) timing * At the rising edge of the three-phase output shift register (INV16 = 1) a2k-1: Value set to the TAi register at odd-numbered time. a2k: Value set to the TAi register at even-numbered time. bk: Value set to the TAi1 register at k-th time. ak: Value set to the TAi register at k-th time. j: the number of interrupts
m: Value of the TB2 register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Figure 16.11 shows an example of the triangular wave modulation operation (three-phase mode 0). Figures 16.12 and 16.13 show examples of the triangular wave modulation operation (three-phase mode 1).
Triangular Waveform as a Carrier Wave (Three-phase mode 0)
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register Timer A4 start trigger signal (1) TA4 register Reload register(1) Timer A4 one-shot pulse(1) Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1) INV14 bit in INVC1 register = 0 (Active Low) U-phase U-phase U-phase Dead time Dead time U-phase
DU0 = 1 DU1 = 0 DUB1 = 1 DUB0 = 0
a1 a1 a1
a2 a2 a2
a3 a3 a3
a4 a4 a4
a5 a5 a5
a6 a6 a6
a7 a7 a7
a8 a8 a8
a9 a9
Rewrite registers IDB0 and IDB1
DU0 = 1 DU1 = 1
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB0 = 0 DUB1 = 0
INV14 bit in INVC1 register = 1 (Active High)
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: INV01 bit = 0 (ICTB2 counter is incremented by 1 when timer B2 underflows) INV02 bit = 1 (Three-phase motor control timer function used) INV03 bit = 1 (Three-phase motor control timer output enabled) INV06 bit = 0 (Triangular wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 0 (Timers A11, A21, A41 not used (Three-phase mode 0)) INV15 bit = 0 (Dead time enabled) INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase)) - ICTB2 register = 01h (Timer B2 interrupt is generated every timer B2 underflow) The following shows examples to change PWM output levels. - Default value of the timer: TA4 = a1 (The TA4 register is rewritten every time the timer B2 interrupt occurs.) First time TA4 = a2, second time TA4 = a3, third time TA4 = a4, fourth time TA4 = a5, fifth time TA4 = a6 - Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the sixth timer B2 interrupt.
Figure 16.11
Triangular Wave Modulation Operation (Three-Phase Mode 0)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Triangular Waveform as a Carrier Wave (Three-phase mode 1: INV01 and INV00 = 10b)
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register INV13 bit in the INVC1 register Timer A4 start trigger signal (1) TA4 register TA41 register Reload register(1) Timer A4 one-shot pulse (1) Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1) INV14 bit in INVC1 register = 0 (Active Low) U-phase U-phase U-phase Dead time Dead time U-phase
DU0 = 1 DU1 = 0 DUB1 = 1 DUB0 = 0
a1 b1 b1 b1 a1
a2 b2 b2 a1 b2 a2
a3 b3 b3 a2 a3 b3 a3
a4 b4 b4 a4 b4
a5 b5 b5 a4
Rewrite registers IDB0 and IDB1
DU0 = 1 DU1 = 1
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB0 = 0 DUB1 = 0
INV14 bit in INVC1 register = 1 (Active High)
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: Bits INV01 and INV00 = 10b (ICTB2 counter is incremented by 1 at the rising edge of the timer A1 reload control signal) INV02 bit = 1 (Three-phase motor control timer function used) INV03 bit = 1 (Three-phase motor control timer output enabled) INV06 bit = 0 (Triangular wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 1 (Timer A11, T21, A41 used (Three-phase mode 1)) INV15 bit = 0 (Dead time enabled) INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase)) - ICTB2 register = 01h (First timer B2 interrupt occurs when timer B2 underflows for the first time, and the subsequent interrupts occur every second timer B2 underflow.) The following shows examples to change PWM output levels. - Default value of the timer: TA41 = b1, TA4 = a1 (Registers TA4 and TA41 are rewritten every time the timer B2 interrupt occurs.) First time TA41 = b2, TA4 = a2, second time TA41 = b3, TA4 = a3 - Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the third timer B2 interrupt.
Figure 16.12
Triangular Wave Modulation Operation (Three-Phase Mode 1)(INV01 and INV00 = 10b)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Triangular Waveform as a Carrier Wave (Three-phase mode 1: INV0 and INV00 = 11b)
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register INV13 bit in the INVC1 register Timer A4 start trigger signal (1) TA4 register TA41 register Reload register(1) Timer A4 one-shot pulse (1) Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1) INV14 bit in INVC1 register = 0 (Active Low) U-phase U-phase Dead time INV14 bit in INVC1 register = 1 (Active High) U-phase Dead time U-phase
DU0 = 1 DU1 = 0 DUB1 = 1 DUB0 = 0
a1 b1 b1 b1 a1
b1
a2 b2 b2 b2 a2
b2
a3 b3 b3 a3 b3
b3
a4 b4 b4 a4 b4
b4
a5 b5 b5
a1
a2
a3
a4
Rewrite registers IDB0 and IDB1
DU0 = 1 DU1 = 1
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1
DUB0 = 0 DUB1 = 0
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: Bits INV01 and INV00 = 11b (ICTB2 counter is incremented by 1 at the falling edge of the timer A1 reload control signal) INV02 bit = 1 (Three-phase control timer function used) INV03 bit = 1 (Three-phase control timer output enabled) INV06 bit = 0 (Triangular wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 1 (Timers A11, A21, A41 used (Three-phase mode 1)) INV15 bit = 0 (Dead time enabled) INV16 bit = 1 (Rising edge of the three-phase output shift register (U-, V-, W-phase)) - ICTB2 register = 01h (Every second timer B2 underflow.) (ICTB2 register = 02h, if INV01 bit = 0) The following shows examples to change PWM output levels. - Default value of the timer: TA41 = b1, TA4 = a1 (Registers TA4 and TA41 are rewritten every time the timer B2 interrupt occurs.) First time TA41 = b2, TA4 = a2, second time TA41 = b3, TA4 = a3 - Default value of the registers IDB0 and IDB1: DU0 = 1, DUB0 = 0, DU1 = 0, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0 at the third timer B2 interrupt.
Figure 16.13
Triangular Wave Modulation Operation (Three-Phase Mode 1)(INV01 and INV00 = 11b)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
16.2
Sawtooth Wave Modulation Mode
In sawtooth wave modulation mode, one cycle of carrier waveform consists of one timer B2 underflow cycle. A timer Ai one-shot pulse (i = 1, 2, and 4) is generated by using a timer B2 underflow signal as a trigger. Single one-shot pulse from timer Ai is used to output one cycle of the PWM waveform. Table 16.4 lists specifications and settings of sawtooth wave modulation mode. Table 16.4
INV06 bit INV11 bit Bits INV01 and INV00 PWCON bit ICTB2 register INV16 bit Carrier wave cycle Upper arm active level output width Timer B2 interrupt generation timing Timer B2 reload timing Transfer timing from IDBp register to three-phase output shift register (p = 0, 1) Dead time timer start timing
Specifications and Settings of Sawtooth Wave Modulation Mode
Item Three-Phase Mode 0 1 0 00b or 01b 0 n 0 1 x (m + 1) f1 1 xa k f1 Every n-th timer B2 underflow Timer B2 underflow Every time a transfer trigger occurs.
* At the falling edge of the one-shot pulse of timer A1, A2 and A4 * Transfer trigger
m: Value of the TB2 register ak: Value set to the TAi register at k-th time.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
Figure 16.14 shows an example of the sawtooth wave modulation operation.
Sawtooth Waveform as a Carrier Wave
Carrier wave Signal wave
TB2S bit in the TABSR register
Timer B2 Set to 0 by an interrupt request acknowledgement or by a program IR bit in the TB2IC register Timer A4 start trigger signal (1) TA4 register Timer A4 one-shot pulse (1) Upper arm (U-phase) output signal(1) Lower arm (U-phase) output signal(1)
DU1 = 1 DU0 = 0 DUB0 = 1 DUB1 = 1 DUB0 = 0 DU0 = 1 DU1 = 1
a1 a1
a2 a2
a3 a3
a4 a4
a5 a5
a6 a6
a7 a7
a8 a8
Rewrite registers IDB0 and IDB1
DUB1 = 1
Values are transferred to the three-phase output shift register from registers IDB0 and IDB1 INV14 bit in INVC1 register = 0 (Active Low) U-phase Dead time U-phase U-phase Dead time U-phase
INV14 bit in INVC1 register = 1 (Active High)
NOTE: 1. Internal signals. See Three-Phase Motor Control Timer Function Block Diagram. The above applies under the following conditions: - INVC0 register: INV01 bit = 0 (ICTB2 counter is incremented by 1 when timer B2 underflows) INV02 bit = 1 (Three-phase motor control timer function used) INV03 bit = 1 (Three-phase motor control timer output enabled) INV06 bit = 1 (Sawtooth wave modulation mode) - INVC1 register: INV10 bit = 0 (Timer B2 underflow) INV11 bit = 0 (Timers A11, A21, A41 not used (Three-phase mode 0)) INV15 bit = 0 (Dead time enabled) INV16 bit = 0 (Falling edge of one-shot pulse of timers A1, A2, and A4) - ICTB2 register = 01h (Timer B2 interrupt is generated every timer B2 underflow) - TB2SC register: PWCON bit = 0 (Timer B2 underflow) The following shows examples to change PWM output levels. - Default value of the timer: TA4 = a1 (The TA4 register is changed every time the timer B2 interrupt occurs.) First time TA4 = a2, second time TA4 = a3, third time TA4 = a4, fourth time = a5 - Default value of the registers IDB0 and IDB1: DU0 = 0, DUB0 = 1, DU1 = 1, and DUB1 = 1 They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 1 at the fourth timer B2 interrupt.
Figure 16.14
Sawtooth Wave Modulation Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
16. Three-Phase Motor Control Timer Function
16.3 16.3.1
Short Circuit Prevention Features Prevention Against Upper/Lower Arm Short Circuit by Program Errors
This function prevents the upper and lower arm short circuit caused by setting the upper and lower output buffers in registers IDB0 and IDB1 to active simultaneously by program errors and so on. To use this function, set the INV04 bit in the INVC0 register to 1 (simultaneous turn-on signal output disabled). If any pair of output buffers (U and U, V and V, or W and W) are simultaneously set to active, the INV05 bit becomes 1 (detected), and the INV03 bit becomes 0 (three-phase motor control timer output disabled). Then, the port outputs are forcibly cutoff and the pins are placed in the high-impedance states. When this prevention function is performed, set the registers associated with the three-phase motor control timer function again.
16.3.2
Arm Short Circuit Prevention Using Dead Time Timer
The dead time timer prevents arm short circuit caused by turn-off delay of external upper and lower transistors. To enable the dead time timer, set the INV15 bit in the INVC1 register to 0 (dead time enabled). The count source for dead time timer (fDT) can be selected using the INV12 bit, and the dead time can be set using the DTT register. The dead time is obtained from the following formulas. 1 f1 2 f1 x n (INV12 = 0) x n (INV12 = 1) n: Value in the DTT register
Figure 16.15 shows an example of dead time timer operation.
U-phase output signal (internal signal)
OFF
ON
OFF
U-phase output signal (internal signal)
ON
OFF
ON
Dead time Dead time timer
Dead time
U-phase turn-on signal output
OFF
ON
OFF
U-phase turn-on signal output
ON
OFF
ON
Figure 16.15
Dead Time Timer Operation
16.3.3
Forced-Cutoff Function by the NMI Input
When an "L" signal is input to the NMI pin, the INV03 bit in the INVC0 register becomes 0 (three-phase motor control timer output disabled), the port outputs are forcibly cutoff, and then the pins are placed in the highimpedance states. Also, the NMI interrupt occurs at the same time. To enable the three-phase motor control timer function after the forced cutoff is performed, set the registers associated with the three-phase motor control timer function again while an "H" signal is input to the NMI pin. Forced-cutoff function by the NMI input can be used when the INV02 bit in the INVC0 register is set to 1 (three-phase motor control timer function used) and the INV03 bit is set to 1 (three-phase motor control timer output enabled).
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 213 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces
17. Serial Interfaces
NOTE The 144-pin package is described as an example in this chapter. UART6 is not provided in the 100-pin package.
Serial interfaces consist of seven channels (UART0 to UART6). Each UARTi (i = 0 to 6) has an exclusive timer to generate the serial clock and operates independently of each other. Table 17.1 lists a UART0 to UART6 function comparison. Table 17.1 UART0 to UART6 Function Comparison
Mode Clock synchronous mode Clock asynchronous mode (UART mode) Special mode 1 (I2C mode) Special mode 2 Special mode 3 (clock-divided synchronous function, GCI mode) Special mode 4 (SIM mode) Special mode 5 (IrDA mode) Special mode 6 (bus conflict detect function, IE mode) (optional)(1) NOTE: 1. Please contact a Renesas sales office for optional features. UART0 Provided Provided Provided Provided Provided Provided Provided Provided UART1 to UART4 UART5, UART6 Provided Provided Provided Provided Provided Provided Not provided Provided Provided Provided Not provided Not provided Not provided Not provided Not provided Not provided
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 214 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1
UART0 to UART4
Figure 17.1 shows a UART0 to UART4 block diagram. Figures 17.2 to 17.10 show the registers associated with UART0 to UART4. Refer to the tables listing for register and pin settings in each mode.
RXDi CLK1 and CLK0 00 CKDIR f1 01 0 f8 F2n(1) 10 1 1/16 SMD2 to SMD0 100, 101, 110 001 100, 101, 110 001 0 1 CKDIR Receive control circuit Transmit control circuit Receive Transmit/ clock receive unit Transmit clock
TXDi
UiBRG register 1/(m+1)
1/16
CKPOL CLKi CLKi input Function Select Register(2) CLKi output CTSi / RTSi Polarity switching Polarity switching
1/2
RTSi output CTSi input Function Select CRD Register(3) CRS
m = Setting value of the UiBRG register NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Select either Input/output port (CLKi input) or CLKi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) 3. Select either Input/output port or RTSi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) 0 IOPOL RXDi STPS 0 1 1 PRYE 001 0 SP PAR 1 100 101 110 001 101 b8 b7 110 100 b6 001 101 110 UARTi receive shift register b5 b4 b3 b2 b1 b0
SP
SMD2 to SMD0 0 0 0 0 0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic inverse circuit + MSB/LSB conversion circuit High-order bits of data bus Low-order bits of data bus Logic inverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB register
STPS 0 SP SP 1
PRYE 001 0 PAR 1 100 101 110
001 101 b8 b7 110
100 b6 001 101 110 b5 b4 b3 b2 b1 b0 UARTi transmit shift register UiERE 0 1 IOPOL TXDi
SMD2 to SMD0 i = 0 to 4 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, IOPOL, and CKDIR: bits in the UiMR register CLK1 and CLK0, CKPOL, CRD, and CRS: bits in the UiC0 register UiERE: bit in the UiC1 register
Error signal output circuit
0 1
Figure 17.1
UART0 to UART 4 Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi transmit/receive mode register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0MR to U2MR U3MR, U4MR
Bit Symbol SMD0 Bit Name
Address 0368h, 02E8h, 0338h 0328h,02F8h
Function
b2 b1 b0
After Reset 00h 00h
RW RW
SMD1
Serial interface mode select bits
0 0 0: Serial interface disabled 0 0 1: Clock synchronous mode 0 1 0: I2C mode 1 0 0: UART mode, 7-bit data length 1 0 1: UART mode, 8-bit data length 1 1 0: UART mode, 9-bit data length Do not set to values other than the above
RW
SMD2
RW
CKDIR
Clock select bit
0: Internal clock 1: External clock 0: 1 stop bit 1: 2 stop bits Enabled when PRYE=1 0: Odd parity 1: Even parity 0: Parity disabled 1: Parity enabled 0: Not inverted 1: Inverted
RW
STPS
Stop bit length select bit
RW
PRY
Parity select bit
RW
PRYE
Parity enable bit TXD, RXD input/output polarity switch bit
RW
IOPOL
RW
Figure 17.2
U0MR to U4MR Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 216 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Special Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0SMR to U2SMR U3SMR, U4SMR
Bit Symbol IICM
Address 0367h, 02E7h, 0337h 0327h, 02F7h
Bit Name I2C mode select bit Arbitration lost detect flag control bit(1) Bus busy flag(1, 2) Function 0 : Other than I 2C mode 1 : I2C mode 0: Updated per bit 1: Updated per byte 0: Stop condition detected (bus is free) 1: Start condition detected (bus is busy) Set to 0 0: Rising edge of serial clock 1: Timer Aj underflow (j = 0, 3, 4) (4) 0: No auto clear function 1: Auto cleared when bus conflict occurs 0 : Not related to RXDi 1 : Synchronized with RXDi 0: External clock not divided 1: External clock divided by 2
After Reset 00h 00h
RW RW
ABC
RW
BBS
- (b3)
RW
Reserved bit Bus conflict detect sampling clock select bit (3) Auto clear function select bit for transmit enable bit (3) Transmit start condition select bit(3) Clock division synchronous bit(5,6)
RW
ABSCS
RW
ACSE
RW
SSS
RW
SCLKDIV
RW
NOTES: 1. These bits are used in I 2C mode. 2. The BBS bit is set to 0 by writing a 0. Writing a 1 has no effect. 3. These bits are used in IE mode. 4. UART0: Timer A3 underflow signal, UART1: Timer A4 underflow signal, UART2: Timer A0 underflow signal, UART3: Timer A3 underflow signal, UART4: Timer A4 underflow signal. 5. The SCLKDIV bit is used in GCI mode. 6. Refer to the note for the SU1HIM bit in the UiSMR2 register.
Figure 17.3
U0SMR to U4SMR Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 217 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Special Mode Register 2 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR2 to U2SMR2 U3SMR2, U4SMR2
Bit Symbol IICM2 Bit Name I2C mode select bit 2
Address 0366h, 02E6h, 0336h 0326h, 02F6h
Function 0: ACK/NACK interrupt used 1: Transmit/receive interrupt used 0: Not clock synchronized 1: Clock synchronized
After Reset 00h 00h
RW RW
CSC
Clock synchronous bit(1)
RW
SWC
SCL wait output bit(2)
0: No wait state/release wait states 1:SCLi pin is held "L" after receiving 8th bit. When arbitration lost is detected, 0: SDAi output not stopped 1: SDAi output stopped When start condition is detected, 0: UARTi not initialized 1: UARTi initialized 0: Serial clock output from SCLi pin 1: SCLi pin is held "L" 0: Output data 1: Output stopped (Hi-impedance state) 0: Not synchronized with external clock 1: Synchronized with external clock
RW
ALS
SDA output auto stop bit (1)
RW
STC
UARTi auto initialization bit(2)
RW
SWC2
SCL wait output bit 2 (1)
RW
SDHI
SDA output stop bit(2) External clock synchronous enable bit(3)
RW
SU1HIM
RW
NOTES: 1. These bits are used when the MCU is in master mode in I 2C mode. 2. These bits are used when the MCU is in slave mode in I 2C mode. 3. The external clock synchronous function can be selected with the combination of the SU1HIM bit and the SCLKDIV bit in the UiSMR register. The SU1HIM bit is used in GCI mode. SCLKDIV Bit in the UiSMR register 0 0 1 SU1HIM Bit in the UiSMR2 register 0 1 0 or 1 External Clock Synchronous Function Select Not synchronized Same frequency as external clock External clock divided by 2
Figure 17.4
U0SMR2 to U4SMR2 Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 218 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Special Mode Register 3 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR3 to U2SMR3 U3SMR3, U4SMR3
Bit Symbol SSE Bit Name SS function enable bit(1)
Address 0365h, 02E5h, 0335h 0325h, 02F5h
Function 0: SS function disabled 1: SS function enabled(2) 0: No Clock delay 1: Clock delay
After Reset 00h 00h
RW RW
CKPH
Clock phase set bit (1)
RW
DINC
Serial input pin set bit (1)
0: Pins TXDi and RXDi selected (master mode) 1: Pins STXDi and SRXDi selected (slave mode) 0: CLKi is CMOS output 1: CLKi is N-channel open drain output 0: No mode error 1: Mode error occurred(3) SDAi output is delayed by the following cycles.
b7 b6 b5
RW
NODC
Clock output select bit
RW
ERR
Mode error flag(1)
RW
DL0
RW
DL1
SDAi digital delay set bits (4, 5)
DL2
0 0 0: No delay 0 0 1: 1-to-2 cycles of BRG count source 0 1 0: 2-to-3 cycles of BRG count source 0 1 1: 3-to-4 cycles of BRG count source 1 0 0: 4-to-5 cycles of BRG count source 1 0 1: 5-to-6 cycles of BRG count source 1 1 0: 6-to-7 cycles of BRG count source 1 1 1: 7-to-8 cycles of BRG count source
RW
RW
NOTES: 1. These bits are used in special mode 2. 2. When the SS pin is set to 1, set the CRD bit in the UiC0 register to 1 ( CTS function disabled). 3. The ERR bit is set to 0 by a program. Writing a 1 has no effect. 4. Digital delay is added to a SDAi output using bits DL2 to DL0 in I 2C mode. Set them to 000b (no delay) in other than I 2C mode. 5. When the external clock is selected, SDAi output is delayed by approximately 100 ns in addition.
Figure 17.5
U0SMR3 to U4SMR3 Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 219 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Special Mode Register 4 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0SMR4 to U2SMR4 U3SMR4, U4SMR4
Bit Symbol STAREQ Bit Name
Address 0364h, 02E4h, 0334h 0324h, 02F4h
Function 0: Clear 1: Start 0: Clear 1: Start 0: Clear 1: Start
After Reset 00h 00h
RW RW
Start condition generate bit(1, 3) Restart condition generate bit(1, 3) Stop condition generate bit(1, 3)
RSTAREQ
RW
STPREQ
RW
STSPSEL
SCL, SDA output select bit (1)
0: Serial input/output circuit selected 1: Start/stop condition generation circuit selected (4) 0: ACK 1: NACK 0: Serial data output 1: ACK data output When the bus is free, 0: SCLi output not stopped 1: SCLi output stopped 0: No wait state/release wait state 1: SCLi pin is held "L" after receiving 9th bit
RW
ACKD
ACK data bit(2)
RW
ACKC
ACK data output enable bit(2)
RW
SCLHI
SCL output stop bit(1)
RW
SWC9
SCL wait output bit 3 (1)
RW
NOTES: 1. These bits are used when the MCU is in master mode in I 2C mode. 2. These bits are used when the MCU is in slave mode in I 2C mode. 3. When each condition generation is completed, the corresponding bit becomes 0. When a condition generation is failed, the bit remains 1. 4. Set the STSPSEL bit to 1 (start/stop condition generation circuit selected) after setting the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start).
Figure 17.6
U0SMR4 to U4SMR4 Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 220 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Transmit/Receive Control Register 0 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U0C0 to U2C0 U3C0, U4C0
Bit Symbol CLK0 Bit Name
Address 036Ch, 02ECh, 033Ch 032Ch, 02FCh
Function
b1 b0
After Reset 0000 1000b 0000 1000b
RW RW
UiBRG count source select bits(1) CLK1
0 0: f1 selected 0 1: f8 selected 1 0: f2n selected (2) 1 1: Do not set to this value Enabled when CRD = 0 0: CTS function selected 1: CTS function not selected 0: Data in the transmit shift register (during transmit operation) 1: No data in the transmit shift register (transmit operation is completed) 0: CTS function enabled 1: CTS function disabled 0: TXDi/SDAi and SCLi are CMOS output ports 1: TXDi/SDAi and SCLi are N-channel open drain output ports 0: Transmit data output at the falling edge and receive data input at the rising edge of the serial clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the serial clock 0 : LSB first 1 : MSB first
RW
CRS
CTS function select bit
RW
TXEPT
Transmit shift register empty flag
RO
CRD
CTS function disable bit
RW
NCH
Data output select bit 3)
RW
CKPOL
CLK polarity select bit
RW
UFORM
Bit order select bit (4)
RW
NOTES: 1. Set the UiBRG register after setting bits CLK1 and CLK0. 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits CLK1 and CLK0 to 10b. 3. P7_0/TXD2, P7_1/SCL2 are N-channel open drain output ports. They cannot be set as CMOS output ports even if the NCH bit is set to 0. 4. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 101b (UART mode, 8-bit data length). Set the UFORM bit to 1 when bits SMD2 to SMD0 are set to 010b (I 2C mode), or to 0 when bits SMD2 to SMD0 are set to 100b (UART mode, 7-bit data length) or 110b (UART mode, 9-bit data length).
Figure 17.7
U0C0 to U4C0 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Baud Rate Register(1, 2) (i = 0 to 4)
b7 b0
Symbol U0BRG to U2BRG U3BRG, U4BRG
Function
Address 0369h, 02E9h, 0339h 0329h, 02F9h
After Reset Undefined Undefined
Setting Range 00h to FFh RW WO
If the setting value is n, the UiBRG register divides a count source by n+1
NOTES: 1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details. 2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
UARTi Transmit/Receive Control Register 1 (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U0C1 to U2C1 U3C1, U4C1
Bit Symbol TE Bit Name Transmit enable bit
Address 036Dh, 02EDh, 033Dh 032Dh, 02FDh
Function 0: Transmit operation disabled 1: Transmit operation enabled 0: Data in the UiTB register 1: No data in the UiTB register 0: Receive operation disabled 1: Receive operation enabled 0: No Data in the UiRB register 1: Data in the UiRB register
After Reset 0000 0010b 0000 0010b
RW RW
TI
UiTB register empty flag
RO
RE
Receive enable bit
RW
RI
Receive complete flag UARTi transmit interrupt source select bit Continuous receive mode enable bit Data logic select bit (1) Special mode 3 Clock-divided synchronous stop bit Special mode 4 Error signal output enable bit (2)
RO
UilRS
0: No data in the UiTB register (TI = 1) 1: Transmit operation is completed (TXEPT = 1) 0: Continuous receive mode disabled 1: Continuous receive mode enabled (3) 0: Not inverted 1: Inverted 0: Synchronization stopped 1: Synchronization started
RW
UiRRM
RW
UiLCH
RW
SCLKSTPB UiERE
RW 0: Not output 1: Output
NOTES: 1. The UiLCH bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode), 100b (UART mode, 7-bit data length), or 101b (UART mode, 8-bit data length). Set the UiLCH bit to 0 when bits SMD2 to SMD0 are set to 010b (I2C mode) or 110b (UART mode, 9-bit data length). 2. Set bits SMD2 to SMD0 before setting the UiERE bit. 3. When the UiRRM bit is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function.
Figure 17.8
U0BRG to U4BRG Registers, U0C1 to U4C1 Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 222 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
External Interrupt Source Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR
Bit Symbol IFSR0 Bit Name INT0 interrupt polarity select bit(1) INT1 interrupt polarity select bit(1) INT2 interrupt polarity select bit(1) INT3 interrupt polarity select bit(1) INT4 interrupt polarity select bit(1) INT5 interrupt polarity select bit(1) UART0, UART3 interrupt source select bit
Address 031Fh
Function 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges 0: One edge 1: Both edges
After Reset 00h
RW RW
IFSR1
RW
IFSR2
RW
IFSR3
RW
IFSR4
RW
IFSR5
RW
IFSR6
0: UART3 bus conflict, start condition detection, stop condition detection 1: UART0 bus conflict, start condition detection, stop condition detection 0: UART4 bus conflict, start condition detection, stop condition detection 1: UART1 bus conflict, start condition detection, stop condition detection
RW
IFSR7
UART1, UART4 interrupt source select bit
RW
NOTE: 1. Set the IFSRi bit (i = 0 to 5) to 0 to select a level-sensitive triggering. When selecting both edges, set the POL bit in the corresponding INTilC register to 0 (falling edge).
Figure 17.9
IFSR Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 223 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
UARTi Transmit Buffer Register (1) (i = 0 to 4)
b15 b8 b7 b0
Symbol U0TB to U2TB U3TB, U4TB
Bit Symbol
- (b7-b0) - (b8) - (b15-b9)
Address 036Bh - 036Ah, 02EBh - 02EAh, 033Bh - 033Ah 032Bh - 032Ah, 02FBh - 02FAh
Function Transmit data (D7 to D0)
After Reset Undefined Undefined
RW WO
Transmit data (D8) Unimplemented. Write 0. Read as undefined value.
WO
-
NOTE: 1. Read-modify-write instructions cannot be used to set the UiTB register. Refer to Usage Notes for details.
UARTi Receive Buffer Register (i = 0 to 4)
b15 b8 b7 b0
Symbol U0RB to U2RB U3RB, U4RB
Bit Symbol
- (b7-b0) - (b8) - (b10-b9)
Address 036Fh - 036Eh, 02EFh - 02EEh, 033Fh - 033Eh 032Fh - 032Eh, 02FFh - 02FEh
Bit Name
-
After Reset Undefined Undefined
RW RO
Function Received data (D7 to D0)
-
Received data (D8)
RO
Unimplemented. Write 0. Read as undefined value. Arbitration lost detect flag (1) 0: Not detected (won) 1: Detected (lost) 0: No overrun error 1: Overrun error 0: No framing error 1: Framing error 0: No parity error 1: Parity error 0 No error occurred 1: Error occurred
-
ABT
RW
OER
Overrun error flag(2)
RO
FER
Framing error flag(2, 3)
RO
PER
Parity error flag(2, 3)
RO
SUM
Error sum flag(2, 3)
RO
NOTES: 1. Only a 0 can be written to the ABT bit. 2. When bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive operation disabled), bits OER, FER, PER and SUM become 0. When all of bits OER, FER and PER become 0, the SUM bit also becomes 0. Bits FER and PER become 0 by reading the low-order byte in the UiRB register. 3. Bits FER, PER and SUM are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 010b (I2C mode). A read from these bits returns undefined value.
Figure 17.10
U0TB to U4TB Registers, U0RB to U4RB Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.1
Clock Synchronous Mode
Full-duplex clock synchronous serial communications are allowed in this mode. CTS/RTS function can be used for transmit and receive control. Table 17.2 lists specifications of clock synchronous mode. Table 17.3 lists pin settings. Figure 17.11 shows register settings. Figure 17.12 shows an example of a transmit and receive operation when an internal clock is selected. Figure 17.13 shows an example of a receive operation when an external clock is selected. Table 17.2
Data format Serial clock Baud rate
Clock Synchronous Mode Specifications
Item Data length: 8 bits long Internal clock or external clock can be selected by the CKDIR bit in the UiMR register (i = 0 to 4) * When the CKDIR bit is set to 0 (internal clock): fj / (2 (m + 1) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * When the CKDIR bit is set to 1 (external clock): clock input to the CLKi pin Selectable among the CTS function, RTS function, or CTS/RTS function disabled Internal clock is selected: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * "L" signal is applied to the CTSi pin when the CTS function is used External clock is selected(2): * Set the TE bit to 1 * The TI bit is 0 * Set the RE bit to 1 * The RI bit in the UiC1 register is 0 when the RTS function is used When above 4 conditions are met, RTSi pin outputs "L" If transmit-only operation is performed, the RE bit setting is not required in both cases. Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(3) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register * CLK polarity Transmit data output timing and receive data input timing can be selected * LSB first or MSB first Data is transmitted and received from either bit 0 or bit 7 * Serial data logic inverse Transmit and receive data are logically inverted * Continuous receive mode The TI bit becomes 0 by reading the UiRB register Specification
Transmit/receive control Transmit and receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, ensure that an "H" signal is applied to the CLKi pin when the CKPOL bit in the UiC0 register is set to 0, and that an "L" signal is applied when the CKPOL bit is set to 1. 3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 225 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.3
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(3) P7_1 P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
17. Serial Interfaces (UART0 to UART4)
Pin Settings in Clock Synchronous Mode
Bit Setting Function CTS0 input RTS0 output CLK0 input CLK0 output RXD0 input TXD0 output(4) CTS1 input RTS1 output CLK1 input CLK1 output RXD1 input TXD1 TXD2 output(4) output(4) PD6, PD7, PD9 Registers(2) PD6_0 = 0 - PD6_1 = 0 - PD6_2 = 0 - PD6_4 = 0 - PD6_5 = 0 - PD6_6 = 0 - - PD7_1 = 0 PD7_2 = 0 - PD7_3 = 0 - PD9_0 = 0 - PD9_1 = 0 - PD9_3 = 0 - PD9_4 = 0 - PD9_5 = 0 - - PD9_7 = 0 - - - - - - - - - - - - PSC_0 = 0 - - PSC_2 = 0 - PSC_3 = 0 - - - - - - - - - - PSC3_6 = 0 - PSC, PSC3 Registers PSL0, PSL1, PSL3 Registers - PSL0_0 = 0 - PSL0_1 = 0 - PSL0_3 = 0 - PSL0_4 = 0 - PSL0_5 = 0 - PSL0_7 = 0 PSL1_0 = 0 - - PSL1_2 = 0 - PSL1_3 = 0 - PSL3_0 = 0 - PSL3_2 = 0 PSL3_3 = 0 - PSL3_4 = 0 - PSL3_5 = 0 - - - PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_0 = 1 PS0_1 = 0 PS0_1 = 1 PS0_2 = 0 PS0_3 = 1 PS0_4 = 0 PS0_4 = 1 PS0_5 = 0 PS0_5 = 1 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS1_2 = 0 PS1_2 = 1 PS1_3 = 0 PS1_3 = 1 PS3_0 = 0 PS3_0 = 1 PS3_1 = 0 PS3_2 = 1 PS3_3 = 0 PS3_3 = 1 PS3_4 = 0 PS3_4 = 1 PS3_5 = 0 PS3_5 = 1 PS3_6 = 1 PS3_7 = 0
RXD2 input CLK2 input CLK2 output CTS2 input RTS2 output CLK3 input CLK3 output RXD3 input TXD3 output(4) CTS3 input RTS3 output CTS4 input RTS4 output CLK4 input CLK4 output TXD4 output(4) RXD4 input
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 is an N-channel open drain output port. 4. After UARTi (i = 0 to 4) operating mode is selected in the UiMR register and the pin function is set in the Function Select Registers, the TXDi pin outputs an "H" signal until a transmit operation starts (the TXDi pin is in a high-impedance state when N-channel open drain output is selected).
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 226 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
Start initial setting
I flag = 0
Interrupt disabled
UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit bits 7 to 4 = 0000b
Clock synchronous mode Clock select bit
UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register = 00h UiSMR4 register = 00h
UiC0 register: bits CLK1 and CLK0 CRS bit CRD bit NCH bit CKPOL bit UFORM bit When an internal clock is used UiBRG register = m
UiBRG register count source select bits CTS function select bit CTS function disable bit Data output select bit CLK polarity select bit Bit order select bit
m = 00h to FFh
Baud rate =
fj 2(m + 1)
fj: f1, f8, f2n (1)
UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit UiLCH bit Bit 7 = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit= 0
Transmit operation disabled Receive operation disabled UARTi transmit interrupt source select bit Continuous receive mode enable bit(2) Data logic select bit
Transmit interrupt priority level select bit Interrupt not requested Receive interrupt priority level select bit Interrupt not requested
Pin settings in the Function Select Registers
I flag = 1
Interrupt enabled
UiC1 register: TE bit = 1 RE bit = 1
Transmit operation enabled Receive operation enabled
End initial setting
Transmit/receive operation starts by writing data to the UiTB register. Read the UiRB register when a receive operation is completed. i = 0 to 4 NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. The UiRRM bit can be set to 1 (continuous receive mode enabled), only when the CKDIR bit in the UiMR register is set to 1 (external clock) and RTS function is disabled.
Figure 17.11
Register Settings in Clock Synchronous Mode
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 227 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
TC Internal clock TE bit in the UiC1 register 1 0 1 0 "H" "L" "H" "L" "H" "L" TXEP bit in the UiC0 register IR bit in the SiTIC register 1 0 1 0 "H" "L" 1 0 1 0
Set to 0 by an interrupt request acknowledgement or by a program D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Write data to the UiTB register
TI bit in the UiC1 register
Transfer data from UiTB register to UARTi transmit shift register
CTSi Input
TCLK
Communication stops because CTSi = "H"
Communication stops because TE bit = 0
CLKi output
TXDi output
RXDi input
D0 D1 D2 D3 D4 D5 D6 Transfer data from UARTi receive shift register to UiRB register
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5
RI bit in the UiC1 register IR bit in the SiRIC register
A read from the UiRB register
Set to 0 by an interrupt request acknowlegement or by a program
i = 0 to 4
TC = TCLK =
2(m + 1) fj
fj = f1, f8, f2n (1) The above applies under the following conditions: m = Setting value of the UiBRG register - UiMR register: CKDIR bit = 0 (internal clock) (00h to FFh) - UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used) CKPOL bit = 0 (transmit data output at the falling edge of the serial clock) - UiC1 register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register) NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.12
Transmit and Receive Operations when Internal Clock is Selected
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17. Serial Interfaces (UART0 to UART4)
RE bit in the UiC1 register TE bit in the UiC1 register TI bit in the UiC1 register
1 0 1 0 1 0 "H" "L" "H" "L" "H" "L" 1 0 1 0 1 0
Set to 0 by an interrupt request acknowledgement or by a program D0 D1 D2 D3 D4 D5 D6 Transfer data from UARTi receive shift register to UiRB register D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Write dummy data to UiTB register
Transfer data from UiTB register to UARTi transmit shift register 1 fEXT
RTSi output
Becomes "L" by reading UiRB register
CLKi input(1)
RXDi input
RI bit in the UiC1 register IR bit in the SiRIC register OER bit in the UiRB register i = 0 to 4
A read from UiRB register
fEXT = external clock frequency The above applies under the following conditions: - UiMR register: CKDIR bit = 1 (external clock) - UiC0 reigster: CRD bit = 1 (CTS function disabled) CKPOL bit = 0 (receive data input at the rising edge of the serial clock) NOTE: 1. Satisfy the following conditions, while the CLKi pin input is "H" before the data receive operation. - UiC1 register: TE bit = 1 (transmit operation enabled) RE bit = 1 (receive operation enabled) - Write dummy data to the UiTB register
Figure 17.13
Receive Operations when External Clock is Selected
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17. Serial Interfaces (UART0 to UART4)
17.1.1.1 CLK Polarity
As shown in figure 17.14, the CKPOL bit in the UiC0 register (i = 0 to 4) determines the polarity of the serial clock.
(1) When the CKPOL bit in the UiC0 register (i = 0 to 4) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock )
CLKi "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 (note 1)
TXDi
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)
CLKi "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 (note 2)
TXDi
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions: - UFORM bit in the UiC0 register is set to 0 (LSB first) - UiLCH bit in the UiC1 register is set to 0 (not inverted). NOTES: 1. The CLKi pin output level is "H" when no transmit and receive operation is in progress. 2. The CLKi pin output level is "L" when no transmit and receive operation is in progress.
Figure 17.14
Serial Clock Polarity
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17. Serial Interfaces (UART0 to UART4)
17.1.1.2 LSB First or MSB First
As shown in figure 17.15, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
CLKi "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
TXDi
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UFORM bit is set to 1 (MSB first)
CLKi "H" "L" "H" "L" "H" "L" D7 D6 D5 D4 D3 D2 D1 D0
TXDi
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
The above applies under the following conditions: - CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge) - UiLCH bit in the UiC1 register is set to 0 (not inverted).
Figure 17.15
Bit Order (8-Bit Data Length)
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17. Serial Interfaces (UART0 to UART4)
17.1.1.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted for transmit operation. A read from the UiRB register returns the inverted logic of receive data. Figure 17.16 shows an example of serial data logic inverse operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
Serial clock "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
TXDi "H" (not inverted) "L" RXDi "H" (not inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UiLCH bit is set to 1 (inverted)
Serial clock "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
TXDi "H" (inverted) "L" RXDi "H" (inverted) "L"
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions: - CKPOL bit in the UiC0 register is set to 0 (transmit data is output at the falling edge and received data is input at the rising edge) - UFORM bit in the UiC0 register is set to 0 (LSB first).
Figure 17.16
Serial Data Logic Inverse
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17. Serial Interfaces (UART0 to UART4)
17.1.1.4 Continuous Receive Mode
Continuous receive mode can be used when all of the following conditions are met. * External clock is selected (the CKDIR bit in the UiMR register (i = 0 to 4) is set to 1) * RTS function is disabled (RTSi pin is not selected in the Function Select Register) When the UiRRM bit in the UiC1 register is set to 1 (continuous receive mode enabled), the TI bit in the UiC1 register becomes 0 (data in the UiTB register) by reading the UiRB register. Do not set dummy data to the UiTB register if the UiRRM bit is set to 1.
17.1.1.5 CTS/RTS Function
* CTS Function
Transmit and receive operation is controlled by using the input signal to the CTSi pin (i = 0 to 4). To use the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function enabled), and the CRS bit to 0 (CTS function selected). With the CTS function used, the transmit and receive operation starts when all the following conditions are met and an "L" signal is applied to the CTSi pin. -The TE bit in the UiC1 register is set to 1 (transmit operation enabled) -The TI bit in the UiC1 register is 0 (data in the UiTB register) -The RE bit in the UiC1 register is set to 1 (receive operation enabled) (If transmit-only operation is performed, the RE bit setting is not required) When a high-level ("H") signal is applied to the CTSi pin during transmitting and receiving, the transmit and receive operation is disabled after the transmit and receive operation in progress is completed.
* RTS Function
The MCU can inform the external device that it is ready for a transmit and receive operation by using the output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register. With the RTS function used, the RTSi pin outputs an "L" signal when all the following conditions are met, and outputs an "H" when the serial clock is input to the CLKi pin. -The RI bit in the UiC1 register is 0 (no data in the UiRB register) -The TE bit is set to 1 (transmit operation enabled) -The RE bit is set to 1 (receive operation enabled) (If transmit-only operation is performed, the RE bit setting is not required) -The TI bit is 0 (data in the UiTB register)
17.1.1.6 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in clock synchronous mode. (1) Set the TE bit in the UiC1 register (i = 0 to 4) to 0 (transmit operation disabled) and the RE bit to 0 (receive operation disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous mode). (4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
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17. Serial Interfaces (UART0 to UART4)
17.1.2
Clock Asynchronous (UART) Mode
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.4 lists specifications of UART mode. Table 17.5 lists pin settings. Figure 17.17 shows register settings. Figure 17.18 shows an example of a transmit operation. Figure 17.19 shows an example of a receive operation. Table 17.4
Data format
UART Mode Specifications
Item Specification * Data length: selectable among 7 bits, 8 bits, or 9 bits long * Start bit: 1 bit long * Parity bit: selectable among odd, even, or none * Stop bit: selectable from 1 bit or 2 bits long fj / (16 (m + 1)) fj = f1, f8, f2n(1), fEXT m: setting value of the UiBRG register (00h to FFh) fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is set to 1 (external clock) Selectable among CTS function, RTS function or CTS/RTS function disabled To start transmit operation, all of the following must be met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected To start receive operation, all of the following must be met: * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * The RI bit is 1 (no data in UiRB register) when RTS function is used. When the above two conditions are met, the RTSi pin output an "L" signal. * The start bit is detected Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when the final stop bit is output from the UARTi transmit shift register Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(2) Overrun error occurs when the preceding bit of the final stop bit of the next data (the first stop bit when selecting 2 stop bits) is received before reading the UiRB register * Framing error Framing error occurs when the number of the stop bits set by the STPS bit in the UiMR register is not detected * Parity error Parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set by the PRY bit in the UiMR register. * Error sum flag Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs * LSB first or MSB first Data is transmitted or received from either bit 0 or bit 7 * Serial data logic inverse Transmit and receive data are logically inverted. The start bit and stop bit are not inverted * TXD and RXD I/O polarity inverse The level output from the TXD pin and the level applied to the RXD pin are inverted. All the data including the start bit and stop bit are inverted.
Baud rate
Transmit/receive control Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
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Table 17.5
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(3) P7_1 P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
17. Serial Interfaces (UART0 to UART4)
Pin Settings in UART Mode
Bit Setting Function CTS0 input RTS0 output CLK0 input RXD0 input CTS1 input RTS1 output CLK1 input RXD1 input TXD2 output(4) PD6, PD7, PD9 Registers(2) PD6_0 = 0 - PD6_1 = 0 PD6_2 = 0 PD6_4 = 0 - PD6_5 = 0 PD6_6 = 0 - PD7_1 = 0 PD7_2 = 0 PD7_3 = 0 - PD9_0 = 0 PD9_1 = 0 PD9_3 = 0 - PD9_4 = 0 - PD9_5 = 0 - PD9_7 = 0 - - - - - - - - - - PSC_0 = 0 - - - PSC_3 = 0 - - - - - - - - PSC3_6 = 0 - PSC, PSC3 Registers PSL0, PSL1, PSL3 Registers - PSL0_0 = 0 - - PSL0_3 = 0 - PSL0_4 = 0 - - PSL0_7 = 0 PSL1_0 = 0 - - - PSL1_3 = 0 - - PSL3_2 = 0 PSL3_3 = 0 - PSL3_4 = 0 - PSL3_5 = 0 - - PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_0 = 1 PS0_1 = 0 PS0_2 = 0 PS0_3 = 1 PS0_4 = 0 PS0_4 = 1 PS0_5 = 0 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS1_2 = 0 PS1_3 = 0 PS1_3 = 1 PS3_0 = 0 PS3_1 = 0 PS3_2 = 1 PS3_3 = 0 PS3_3 = 1 PS3_4 = 0 PS3_4 = 1 PS3_5 = 0 PS3_6 = 1 PS3_7 = 0
TXD0 output(4) -
TXD1 output(4) - RXD2 input CLK2 input CTS2 input RTS2 output CLK3 input RXD3 input CTS3 input RTS3 output CTS4 input RTS4 output CLK4 input TXD4 output(4) RXD4 input
TXD3 output(4) -
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 is an N-channel open drain output port. 4. After UARTi (i = 0 to 4) operating mode is selected in the UiMR register and the pin function is set in the Function Select Registers, the TXDi pin outputs an "H" signal until a transmit operation starts (the TXDi pin is in a high-impedance state when N-channel open drain output is selected).
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17. Serial Interfaces (UART0 to UART4)
Start initial setting
I flag = 0 UiMR register: bits SMD2 to SMD0 CKDIR bit STPS bit PRY bit PRYE bit IOPOL bit UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register = 00h UiSMR4 register = 00h UiC0 register: bits CLK1 and CLK0 CRS bit CRD bit NCH bit CKPOL bit = 0 UFORM bit UiBRG register = m UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit = 0 UiLCH bit bit 7 = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled UART mode(1) select bits Clock select bit Stop bit length select bit Parity select bit Parity enable bit TXD, RXD I/O polarity switch bit
UiBRG register count source select bits CTS function select bit CTS function disable bit Data output select bit Bit order select bit (2) m = 00h to FFh Baud rate = fj 16(m+1) fj = f1, f8, f2n (3), fEXT
Transmit operation disabled Receive operation disabled UARTi transmit interrupt source select bit Data logic select bit (4)
Transmit interrupt priority level select bits Interrupt not requested Receive interrupt priority level select bits Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End itinial setting
Transmit operation starts by writing data to the UiTB register Receive operation starts when the start bit is detected. Read the UiRB register when the receive operation is completed. i = 0 to 4 fEXT: clock input to the CLKi pin when the external clock is selected NOTES: 1. Set bits SMD2 to SMD0 to the following: 100b (7 bits long), 101b (8 bits long), or 110b (9 bits long). 2. A bit order can be selected when 8-bit data length is selected. Set to 0 when 7-bit or 9-bit data length is selected. 3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 4. Whether data logic is inverted or not can be selected when 7-bit or 8-bit data length is selected. Set to 0 when 9-bit data length is selected.
Figure 17.17
Register Settings in UART Mode
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17. Serial Interfaces (UART0 to UART4)
(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)
TC Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register CTSi input 1 0 1 0 "H" "L" "H" "L" 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) - UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used) - UiC1 register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed) Start bit Write data to UiTB register
Transfer data from UiTB register to UARTi transmit shift register
Stop bit Parity bit
Transmission stops because TE = 0
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0
TXDi output TXEPT bit in the UiC0 register IR bit in the SiTIC register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)
TC Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register TXDi output TXEPT bit in the UiC0 register IR bit in the SiTIC register 1 0 1 0 "H" "L" 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits) - UiC0 register: CRD bit = 1 (CTS function disabled) - UiC1 register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register) TC = 16(m + 1) fj fj: f1, f8, f2n (1), fEXT fEXT: clock input to the CLKi pin when the external clock is selected m: setting value of the UiBRG register (00h to FFh) Start bit Write data to UiTB register Transfer data from UiTB register to UARTi transmit shift register
Stop bits
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
i = 0 to 4 NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.18
Transmit Operation in UART Mode
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17. Serial Interfaces (UART0 to UART4)
Example of the receive operation timing (1 stop bit)
(note 1)
RXDi input
"H" "L"
Start bit Verify the level (note 2)
D0 Input the receive data
Stop bit
Clock divided by UiBRG register Internal receive clock
Set to 0 by an interrupt request acknowledgement or by a program
IR bit in the SiRIC register
1 0
RI bit in the UiC1 register
1 0 The output signal becomes "H" when the receive operation starts
This bit becomes 1 when the data is transferred from UARTi receive shift register to UiRB register
RTSi output
"H" "L"
The output signal becomes "L" when the RE bit in the UiC1 register is set to 1
The RI bit becomes 0 and RTSi output becomes "L" by reading the UiRB register
i = 0 to 4 The above applies under the following conditions: - UiMR register: STPS bit = 0 (1 stop bit) - UiC0 register: CRS bit = 1 (CTS function not used) NOTES: 1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive clock is generated after detecting the falling edge of the start bit, and then the receive operation starts. 2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled. When the receive operatin is cancelled, the RTSi output becomes "L".
Figure 17.19
Receive Operation in UART Mode
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17. Serial Interfaces (UART0 to UART4)
17.1.2.1 Baud Rate
In UART mode, the baud rate is the frequency of the clock divided by the setting value of the UiBRG register (i = 0 to 4) and again divided by 16. Table 17.6 lists an example of baud rate setting. UiBRG register count source 16 x (UiBRG register setting value + 1)
Actual baud rate = Table 17.6
Target Baud Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200
Baud Rate
UiBRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Clock: 16MHz UiBRG Setting Value: n 103(67h) 51(33h) 25(19h) 103(67h) 68(44h) 51(33h) 34(22h) 31(1Fh) 25(19h) 19(13h) Actual Baud Rate (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000 Peripheral Clock: 24MHz UiBRG Setting Value: n 155(9Bh) 77(4Dh) 38(26h) 155(9Bh) 103(67h) 77(4Dh) 51(33h) 47(2Fh) 38(26h) 28(1Ch) Actual Baud Rate (bps) 1202 2404 4808 9615 14423 19231 28846 31250 38462 51724 Peripheral Clock: 32MHz UiBRG Setting Value: n 207(CFh) 103(67h) 51(33h) 207(CFh) 138(8Ah) 103(67h) 68(44h) 63(3Fh) 51(33h) 38(26h) Actual Baud Rate (bps) 1202 2404 4808 9615 14388 19231 28986 31250 38462 51282
17.1.2.2 LSB First or MSB First
As shown in Figure 17.20, the UFORM bit in the UiC0 register (i = 0 to 4) determines a bit order. This function can be used when data length is 8 bits long.
(1) When the UFORM bit in the UiC0 register (i = 0 to 4) is set to 0 (LSB first)
TXDi "H" "L" "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UFORM bit is set to 1 (MSB first)
TXDi "H" "L" "H" "L" ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
The above applies under the following conditions: - UiC0 register: CKPOL bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock) - UiC1 register: UiLCH bit = 0 (not inverted) and the UiLCH bit in the UiC1 register is set to 0 (not inverted). ST: Start bit P: Parity bit SP: Stop bit
Figure 17.20
Bit Order
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.2.3 Serial Data Logic Inverse
When the UiLCH bit in the UiC1 register is set to 1 (inverted), data logic written in the UiTB register is inverted for transmit operation. A read from the UiRB register returns the inverted logic of receive data. This function can be used when data length is 7 bits or 8 bits long. Figure 17.21 shows an example of serial data logic inverse operation.
(1) When the UiLCH bit in the UiC1 register (i = 0 to 4) is set to 0 (not inverted)
TXDi (not inverted) "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) When the UiLCH bit is set to 1 (inverted)
TXDi (inverted) "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
The above applies under the following conditions: - UiC0 register: UFORM bit = 0 (LSB first) - UiMR register: STPS bit = 0 (1 stop bit) PRYE bit = 1 (parity enabled).
Figure 17.21
Serial Data Logic Inverse
17.1.2.4 TXD and RXD I/O Polarity Inverse
The level output from the TXD pin and the level applied to the RXD pin are inverted with this function. When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 1 (inverted), all the input/output data levels, including the start bit, stop bit and parity bit, are inverted. Figure 17.22 shows TXD and RXD I/O polarity inverse.
(1) When the IOPOL bit in the UiMR register (i = 0 to 4) is set to 0 (not inverted)
TXDi "H" (not inverted) "L" RXDi "H" (not inverted) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the IOPOL bit is set to 1 (inverted)
TXDi "H" (inverted) "L" RXDi "H" (inverted) "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
The above applies under the following conditions: - UiC0 register: UFORM bit = 0 (LSB first) - UiMR register: STPS bit = 0 (1 stop bit) PRYE bit = 1 (parity enabled)
ST: Start bit P: Parity bit SP: Stop bit
Figure 17.22
TXD and RXD I/O Polarity Inverse
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.2.5 CTS/RTS Function
* CTS Function
Transmit operation is controlled by using the input signal to the CTSi pin . To use the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function enabled), and the CRS bit to 0 (CTS function selected). With the CTS function used, the transmit operation starts when all the following conditions are met and an "L" signal is applied to the CTSi pin (i = 0 to 4). -The TE bit in the UiC1 register is set to 1 (transmit operation enabled) -The TI bit in the UiC1 register is 0 (data in the UiTB register) When a high-level ("H") signal is applied to the CTSi pin during transmitting, the transmit operation is disabled after the transmit operation in progress is completed.
* RTS Function
The MCU can inform the external device that it is ready for a receive operation by using the output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register. With the RTS function used, the RTSi pin outputs an "L" signal when all the following conditions are met, and outputs an "H" when the start bit is detected. -The RI bit in the UiC1 register is 0 (no data in the UiRB register) -The RE bit is set to 1 (receive operation enabled)
17.1.2.6 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in UART mode. (1) Set the TE bit in the UiC1 register (i = 0 to 4) to 0 (transmit operation disabled) and the RE bit to 0 (receive operation disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, 7-bit data length), 101b (UART mode, 8-bit data length), or 110b (UART mode, 9-bit data length). (4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.3
Special Mode 1 (I2C Mode)
In I2C mode, the simplified I2C helps to communicate with external devices. Table 17.7 lists specifications of I2C mode. Tables 17.8 and 17.9 list register settings. Tables 17.10 and 17.11 list individual functions in I2C mode. Table 17.12 lists pin settings. Figure 17.23 shows a block diagram of I2C mode. Figure 17.24 shows a transfer timing to the UiRB register (i = 0 to 4) and interrupt timing. Table 17.7
Data format Baud rate
I2C Mode Specifications
Item * Data length: 8 bits long * In master mode When the CKDIR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * In slave mode When the CKDIR bit is set to 1 (external clock): input from the SCLi pin To start transmit operation, all of the following must be met(2): * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) To start receive operation, all of the following must be met(2): * Set the TE bit to 1 (transmit operation enabled) * The TI bit is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * Start condition detection * Stop condition detection * ACK (Acknowledge) detection * NACK (Not-Acknowledge) detection * Overrun error(3) Overrun error occurs when the 8th bit of the next data is received before reading the UiRB register * Arbitration lost detect timing Update timing of the ABT bit in the UiRB register (i = 0 to 4) can be selected. * SDAi digital delay No digital delay or 2 to 8 cycle delay of the UiBRG count source can be selected. * Clock phase setting Clock delay or no clock delay can be selected. Specification
Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, satisfy the conditions while an "H" signal is applied to the SCLi pin. 3. If an overrun error occurs, a read from the UiRB register returns undefined values.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
(note 1, 2) NCH
SDAi
Select SDA output in Function Control Register
ABT DQ T ALS SDHI 0 1 ACKD IICM = 0 or IICM2 = 1 IICM = 1 and IICM2 = 0 DMA 0 to 3 request UARTi receive interrupt request ACK interrupt request ACKC STSPSEL Delay circuit
0 1
Noise filter
UARTi transmit shift register Transmission control circuit UARTi transmit shift register Reception control circuit
DMA 0 to 3 request UARTi transmit interrupt request NACK interrupt request
IICM = 0 or IICM2 = 1 IICM = 1 and IICM2 = 0
Start condition detection
BBS SQ NACK DQ T DQ T SQ R R
Start/stop condition detection interrupt request
Stop condition detection
Logic 0 write signal to PDk_m (note 1, 2) NCH Falling edge detection
Logic 1 write signal to PDk_m
ACK
Start/stop condition generation block
SCLi Select SCL output in Function Control Register 9th clock UARTi CLK control STSPSEL IICM 0 0 1 1
SWC2 SWC Falling edge of 9th bit SQ R
Noise filter
i = 0 to 4 IICM, BBS: bits in the UiSMR register IICM2, SWC, ALS, SWC2, SDHI: bits in the UiSMR2 register STSPSEL, ACKD, ACKC: bits in the UiSMR4 register NCH: bit in the UiC0 register ABT: UiRB register PDk_m: bit in the Port Pk Direction Register corresponding to the SCLi pin NOTES: 1. P7_0 and P7_1 do not have the dotted rectangular portion of the circuit. The absolute maximum rating of the input voltage for P7_0 and P7_1 is from - 0.3 V to 6.0 V. 2. P6_2, P6_3, P6_6, P6_7, P9_1, P9_2, P9_6, and P9_7 are used with turning off the P channel of the CMOS port all the time. The absolute maximum rating of the input voltage for these ports is from - 0.3 V to VCC1 + 0.3 V.
Figure 17.23
I2C Mode Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.8
Register UiMR
17. Serial Interfaces (UART0 to UART4)
Register Settings in I2C Mode (1/2)
Bit SMD2 to SMD0 CKDIR IOPOL Set to 010b Set to 0 Set to 0 Set to 1 Select an arbitration lost detect timing Disabled Bus busy flag Set to 00000b See Tables 17.10 and 17.11 Functions in I2C Mode Set to 1 to enable clock synchronization Set to 0 Set to 1 Setting Value Master Slave
UiSMR
IICM ABC BBS 7 to 3
UiSMR2
IICM2 CSC SWC ALS STC SWC2 SDHI SU1HIM
Set to 1 to hold an "L" signal output from SCLi at the falling edge of the ninth bit of the serial clock Set to 1 to abort an SDAi output when Set to 0 detecting the arbitration lost Set to 0 Set to 1 to initialize UARTi by detecting the start condition
Set to 1 to forcibly make a signal output from SCL an "L" Set to 1 to disable SDA output Set to 0 Set to 0 See Tables 17.10 and 17.11 Functions in I2C Mode Set to 0 Set SDAi digital delay value Set to 1 to generate the start condition Set to 1 to generate the restart condition Set to 1 to generate the stop condition Set to 1 when using a condition generation function Select ACK or NACK Set to 1 to output ACK data Set to 1 to enable SCL output stop when detecting the stop condition Set to 0 Set to 0 Set to 1 to hold an "L" signal output from SCLi at the falling edge of the ninth bit of the serial clock Set to 0
UiSMR3
SSE CKPH DINC, NODC, ERR DL2 to DL0
UiSMR4
STAREQ RSTAREQ STPREQ STSPSEL ACKD ACKC SCLHI SWC9
i = 0 to 4
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.9
Register UiC0
17. Serial Interfaces (UART0 to UART4)
Register Settings in I2C Mode (2/2)
Bit CLK1, CLK0 CRS TXEPT CRD, NCH CKPOL UFORM Setting Value Master Select the count source of the UiBRG Disabled register Disabled because the CRD bit is set to 1 Transmit shift register empty flag Set to 1 Set to 0 Set to 1 Set to 1 to enable transmit operation UiTB register empty flag Set to 1 to enable receive operation Receive operation complete flag Set to 0 Set baud rate Select the UARTi interrupt source Set transmit data Receive data can be read ACK or NACK is received Arbitration lost detect flag Overrun error flag Disabled Disabled Slave
UiC1
TE TI RE RI UiLCH, UiERE
UiBRG IFSR UiTB UiRB
7 to 0 IFSR7, IFSR6 7 to 0 7 to 0 8 ABT OER
i = 0 to 4
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
As shown in Table 17.10, I2C mode is entered when bits SMD2 to SMD0 in the UiMR register are set to 010b (I2C mode) and the IICM bit in the UiSMR register to 1 (I2C mode). Because an SDAi transmit output passes through a delay circuit, output signal from the SDAi pin changes after the SCLi pin level becomes low ("L") and the "L" output stabilizes. Table 17.10 Functions in I2C Mode (1/2)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) Function IICM2 = 0 (NACK/ACK interrupt) CKPH = 0 (no clock delay) Interrupt source for numbers 39 to 41(1) (See Figure 17.24) CKPH = 1 (clock delay) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (no clock delay) CKPH = 1 (clock delay)
Start condition or stop condition detection (See Table 17.13 STSPSEL Bit Function) UARTi transmit operation - at the rising edge of 9th bit of SCLi UARTi transmit operation - at the next falling edge after the 9th bit of SCLi
No acknowledgement detection (NACKi) Interrupt source for numbers 17, 19, 33, 35, at the rising edge of 9th bit of SCLi 37(1) (See Figure 17.24) Acknowledgement detection (ACKi) Interrupt source for numbers 18, 20, 34, 36, at the rising edge of 9th bit of SCLi 38(1) (See Figure 17.24) Data transfer timing At rising edge of 9th bit of SCLi from the UART receive shift register to the UiRB register UARTi transmit output delay Functions of P6_3, P6_7, P7_0, P9_2, P9_6 Functions of P6_2, P6_6, P7_1, P9_1, P9_7 Noise filter width Delay SDAi input and output
UARTi receive operation - at the falling edge of 9th bit of SCLi
Falling edge of 9th bit Falling edge and of SCLi rising edge of 9th bit of SCLi
SCLi input and output
200 ns
i = 0 to 4 NOTE: 1. Use the following procedures to change an interrupt source. (a) Disable an interrupt of the corresponding interrupt number. (b) Change an interrupt source. (c) Set the IR bit of a corresponding interrupt number to 0 (interrupt not requested). (d) Set bits ILVL2 to ILVL0 of the corresponding interrupt number.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.11 Functions in I2C Mode (2/2)
17. Serial Interfaces (UART0 to UART4)
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1) Function IICM2 = 0 (NACK/ACK interrupt) CKPH = 0 (no clock delay) CKPH = 1 (clock delay) IICM2 = 1 (UART transmit/receive interrupt) CKPH = 0 (no clock delay) CKPH = 1 (clock delay)
Reading RXDi, SCLi pin Can be read regardless of the corresponding port direction bit levels Default value of TXDi, SDAi output SCLi default and end values DMA source (See Figure 17.24) Storing receive data Value set in the port register before entering I2C mode(1) H L H L
Acknowledgement detection (ACKi) 1st to 8th bit of the receive data are stored into bits 7 to 0 in the UiRB register
UARTi receive operation - at the falling edge of 9th bit of SCLi 1st to 7th bits of the receive data are stored into bits 6 to 0 in the UiRB register. 8th bit is stored into bit 8 in the UiRB register 1st to 8th bits are stored into bits 7 to 0 in the UiRB register(2)
Reading receive data
The value in the UiRB register is read as it is
Bits 6 to 0 in the UiRB register are read as bits 7 to 1. Bit 8 in the UiRB register is read as bit 0(3)
i = 0 to 4 NOTES: 1. Set default value of the SDAi output while bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled). 2. Second data transfer to the UiRB register (at the rising edge of the ninth bit of SCLi). 3. First data transfer to the UiRB register (at the falling edge of the ninth bit of SCLi).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
(1) When the IICM2 bit is set to 0 (ACK or NACK interrupt) and the CKPH bit is set to 0 (no clock delay)
SCLi SDAi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK,NACK) ACK interrupt (DMA request) or NACK interrupt
b15
Transferred to the UiRB register
b9
b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(2) When the IICM2 bit is set to 0 and the CKPH bit is set to 1 (clock delay)
SCLi SDAi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK) ACK interrupt (DMA request) or NACK interrupt Transferred to the UiRB register
b15 b9 b8 b7 b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
Contents of the UiRB register
(3)When the IICM2 bit is set to 1 (UART transmit or receive interrupt) and the CKPH bit is set to 0
SCLi SDAi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK,NACK) Transmit interrupt
Receive interrupt (DMA request) Transferred to the UiRB register
b15 b9
b8 D0
b7 -
b0 D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register
(4) When the IICM2 bit is set to 1 and the CKPH bit is set to 1
SCLi SDAi
1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK) Transmit interrupt Transferred to the UiRB register (second time)
b15 b9 b8 b7 b0 D8 D7 D6 D5 D4 D3 D2 D1 D0
Receive interrupt (DMA request) Transferred to the UiRB register (first time)
b15 b9 b8 D0 b7 - b0 D7 D6 D5 D4 D3 D2 D1
Contents of the UiRB register i = 0 to 4 The above applies when the CKDIR bit in UiMR register is set to 1 (external clock)
Contents of the UiRB register
Figure 17.24
Transfer Timing to the UiRB Register and Interrupt Timing
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.12
Port P6_2 P6_3 P6_6 P6_7 P7_0(3) P7_1(3) P9_1 P9_2 P9_6 P9_7
17. Serial Interfaces (UART0 to UART4)
Pin Settings in I2C Mode
Bit Setting Function SCL0 output SCL0 input SDA0 output SDA0 input SCL1 output SCL1 input SDA1 output SDA1 input SDA2 output SDA2 input SCL2 output SCL2 input SCL3 output SCL3 input SDA3 output SDA3 input SDA4 output SDA4 input SCL4 output SCL4 input - PD6_2 = 0 - PD6_3 = 0 - PD6_6 = 0 - PD6_7 = 0 - PD7_0 = 0 - PD7_1 = 0 - PD9_1 = 0 - PD9_2 = 0 - PD9_6 = 0 - PD9_7 = 0 PD6, PD7, PD9 Registers(2) - - - - - - - - PSC_0 = 0 - PSC_1 = 0 - - - - - PSC3_6 = 0 - - - PSC, PSC3 Registers PSL0, PSL1, PSL3 Registers PSL0_2 = 0 - PSL0_3 = 0 - PSL0_6 = 0 - PSL0_7 = 0 - PSL1_0 = 0 - PSL1_1 = 0 - PSL3_1 = 0 - PSL3_2 = 0 - - - PSL3_7 = 0 - PS0, PS1, PS3 Registers(1)(2) PS0_2 = 1 PS0_2 = 0 PS0_3 = 1 PS0_3 = 0 PS0_6 = 1 PS0_6 = 0 PS0_7 = 1 PS0_7 = 0 PS1_0 = 1 PS1_0 = 0 PS1_1 = 1 PS1_1 = 0 PS3_1 = 1 PS3_1 = 0 PS3_2 = 1 PS3_2 = 0 PS3_6 = 1 PS3_6 = 0 PS3_7 = 1 PS3_7 = 0
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 and P7_1 are N-channel open drain output ports.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.3.1 Detecting Start Condition and Stop Condition
The MCU detects the start condition and stop condition. The start condition detection interrupt request is generated when the SDAi (i = 0 to 4) pin level changes from high ("H") to low ("L") while the SCLi pin level is held "H". The stop condition detection interrupt request is generated when the SDAi pin level changes from "L" to "H" while the SCLi pin level is held "H". The start condition detection interrupt shares the Interrupt Control Register and interrupt vector with the stop condition detection interrupt. The BBS bit in the UiSMR register determines which interrupt is requested.
6 cycles < setup time (1) 6 cycles < hold time (1) Setup time SCLi SDAi (start condition) SDAi (stop condition) i=0 to 4 NOTE: 1. These are cycles of the main clock oscillation frequency f(XIN). Hold time
Figure 17.25
Start Condition or Stop Condition Detection
17.1.3.2 Start Condition or Stop Condition Output
The start condition is generated when the STAREQ bit in the UiSMR4 register (i = 0 to 4) is set to 1 (start). The restart condition is generated when the RSTAREQ bit in the UiSMR4 register is set to 1 (start). The stop condition is generated when the STPREQ bit in the UiSMR4 is set to 1 (start). The following is the procedure to output the start condition, restart condition, or stop condition. (1) Set the STAREQ bit, RSTAREQ bit, or STPREQ bit to 1 (start). (2) Set the STSPSEL bit in the UiSMR4 register to 1 (start/stop condition generation circuit selected). Table 17.13 and Figure 17.26 show functions of the STSPSEL bit. Table 17.13 STSPSEL Bit Function
STSPSEL = 0 Output the serial clock and data. Output of the start condition or stop condition is controlled by software utilizing port functions. (The start condition and stop condition are not automatically generated by hardware) When start condition and stop condition are detected STSPSEL = 1 Output of the start condition or stop condition is controlled by the status of bits STAREQ, RSTAREQ, and STPREQ.
Function Output from pins SCLi and SDAi
Timing to generate start condition and stop condition interrupt requests
When start condition and stop condition generation are completed
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
(1) In slave mode, the CKDIR bit is set to 1 (external clock) and the STSPSEL bit is set to 0 (no start condition and stop condition output)
SCLi
SDAi Start condition detection interrupt IR bit in the BCNiIC register 1 0 Set to 0 by an interrupt request acknowledgement or by a program Stop condition detection interrupt
(2) In master mode, the CKDIR bit is set to 0 (internal clock) and the STSPSEL bit is set to 1 (start condition and stop condition output)
Setting value of STSPSEL bit SCLi 0 1 0 1 0
SDAi The STAREQ bit is set to 1 (start) IR bit in the BCNiIC register i = 0 to 4 1 0 Set to 0 by an interrupt request acknowledgement or by a program Start condition detection interrupt The STAREQ bit is set to 1 (start) Stop condition detection interrupt
Figure 17.26
STSPSEL Bit Function
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.3.3 Arbitration
The ABC bit in the UiSMR register (i = 0 to 4) determines an update timing of the ABT bit in the UiRB register. At the rising edge of the clock input to the SCLi pin, the MCU determines whether a transmit data matches data input to the SDAi pin. When the ABC bit is set to 0 (update per bit), the ABT bit becomes 1 (detected - arbitration is lost) as soon as a data discrepancy is detected. The ABT bit remains 0 (not detected - arbitration is won) if not detected. When the ABC bit is set to 1 (update per byte), the ABT bit becomes 1 at the falling edge of the ninth cycle of the serial clock if discrepancy is ever detected. When the ABT bit is updated per byte, set the ABT bit to 0 after an ACK detection in the first byte data is completed. Then the next byte data transfer can be started. When the ALS bit in the UiSMR2 register is set to 1 (SDAi output stopped) and the ABT bit becomes 1 (detected - arbitration is lost), the SDAi pin is placed in a high-impedance state simultaneously.
17.1.3.4 Serial Clock
The serial clock is used to transmit and receive data as is shown in Figure 17.24. By setting the CSC bit in the UiSMR2 register to 1 (clock synchronized), an internally generated clock (internal SCLi) is synchronized with the external clock applied to the SCLi pin. If the CSC bit is set to 1, the internal SCLi becomes low ("L") when the internal SCLi is held high ("H") and the external clock applied to the SCLi pin is at the falling edge. The contents of the UiBRG register are reloaded and a counting for "L" period is started. When the external clock applied to SCLi pin is held "L" and then the internal SCLi changes "L" to "H", the UiBRG counter stops. The counting is resumed when the clock applied to SCLi pin becomes "H". The UARTi serial clock is equivalent to logical AND operation of the internal SCLi and the clock signal applied to the SCLi pin. The serial clock is synchronized between a half cycle before the falling edge of the first bit and the rising edge of the ninth bit of the internal SCLi. Select the internal clock as the serial clock while the CSC bit is set to 1. The SWC bit in the UiSMR2 register determines whether an output signal from the SCLi pin is held "L" at the falling edge of the ninth cycle of the serial clock or not. When the SCLHI bit in the UiSMR4 register is set to 1 (SCLi output stopped), a SCLi output stops as soon as the stop condition is detected (the SCLi pin is in a high-impedance state). When the SWC2 bit in the UiSMR2 register is set to 1 (SCLi pin is held "L"), the SCLi pin forcibly outputs an "L" even in the middle of transmitting and receiving. The fixed "L" output from the SCLi pin is cancelled by setting the SWC2 bit to 0 (serial clock), and then the serial clock inputs to or outputs from the SCLi pin. When the CKPH bit in the UiSMR3 register is set to 1 (clock delay) and the SWC9 bit in the UiSMR4 register is set to 1 (SCLi pin is held "L" after receiving 9th bit), an output signal from the SCLi pin is held "L" at the next falling edge to the ninth bit of the clock. The fixed "L" output from the SCLi pin is cancelled by setting the SWC9 bit to 0 (no wait state/release wait state).
17.1.3.5 SDA Output
Values set in bits 7 to 0 (D7 to D0) in the UiTB register are output in descending order from D7. The ninth bit (D8) is ACK or NACK. Set the default value of SDAi transmit output, while the IICM bit in the UiSMR register is set to 1 (I2C mode) and bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled). Bits DL2 to DL0 in the UiSMR3 register determine no delay or delay of 2 to 8 UiBRG register count source cycles are added to an SDAi output. When the SDHI bit in the UiSMR2 register is set to 1 (SDA output stopped), the SDAi pin is forcibly placed in a high-impedance state. Do not write to the SDHI bit at the rising edge of the UARTi serial clock. The ABT bit in the UiRB register may become 1 (detected).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.3.6 SDA Input
When the IICM2 bit in the UiSMR2 register (i = 0 to 4) is set to 0, the first eight bits of received data are stored into bits 7 to 0 (D7 to D0) in the UiRB register. The ninth bit (D8) is ACK or NACK. When the IICM2 bit is set to 1, the first seven bits (D7 to D1) of received data are stored into bits 6 to 0 in the UiRB register. The eighth bit (D0) is stored into bit 8 in the UiRB register. If the IICM2 bit is set to 1 and the CKPH bit in the UiSMR3 register is set to 1 (clock delay), the same data as that of when setting the IICM2 bit to 0 can be returned, by reading the UiRB register after the rising edge of the ninth bit of the serial clock.
17.1.3.7 ACK, NACK
When the STSPSEL bit in the UiSMR4 register is set to 0 (start/stop condition not output) and the ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the SDAi pin outputs the setting value, ACK or NACK, of the ACKD bit in the UiSMR4 register. If the IICM2 bit is set to 0, the NACK interrupt request is generated when the SDAi pin is held high ("H") at the rising edge of the ninth bit of the serial clock. The ACK interrupt request is generated when the SDAi pin is held low ("L") at the rising edge of the ninth bit of the serial clock. When ACK is selected to generate a DMA request source, the DMA transfer is activated by an ACK detection.
17.1.3.8 Transmit and Receive Operation Initialization
The following occurs when the STC bit in the UiSMR2 register is set to 1 (UARTi initialized) and the start condition is detected: * The UARTi transmit shift register is initialized and the contents of the UiTB register are transferred to the UARTi transmit shift register. Then, the transmit operation is started at the next serial clock input to the SCLi pin. UARTi output value remains the same as when the start condition was detected until the first bit data is output. * The UARTi receive shift register is initialized and the receive operation is started at the next serial clock input to the SCLi pin. * The SWC bit in the UiSMR2 register becomes 1 (SCLi pin is held "L" after receiving 8th bit). An output from the SCLi pin becomes "L" at the falling edge of the ninth bit of the serial clock. When UARTi transmit/receive operation is started with setting the STC bit to 1, the TI bit in the UiC1 register remains unchanged. Also, select the external clock as the serial clock to start UARTi transmit/receive operation with setting the STC bit to 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.4
Special Mode 2
Full-duplex clock synchronous serial communications are allowed in this mode. SS function is used for transmit and receive control. The input signal to the SSi pin (i = 0 to 4) determines whether the transmit and receive operation is enabled or disabled. When it is disabled, the output pin is placed in a high-impedance state. Table 17.14 lists specifications of special mode 2. Table 17.15 lists pin settings. Figure 17.27 shows register settings. Table 17.14
Data format Baud rate
Special Mode 2 Specifications
Item Data length: 8 bits long * The CKDiR bit in the UiMR register (i = 0 to 4) is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * The CKDIR bit to 1 (external clock): input from the CLKi pin * SS function Output pin is placed in a high-impedance state to avoid data conflict between a master and other masters, or a slave and other slaves. Internal clock is selected (master mode): * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * "H" signal is applied to the SSi pin when the SS function is used External clock is selected (slave mode)(2): * Set the TE bit to 1 * The TI bit is 0 * Set the RE bit to 1 * "L" signal is applied to the SSi pin If transmit-only operation is performed, the RE bit setting is not required in both cases. Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(3) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register * Mode error Mode error occurs when an "L" signal is applied to the SSi pin in master mode * CLK polarity Transmit data output timing and receive data input timing can be selected * LSB first or MSB first Data is transmitted or received from either bit 0 or bit 7 * Serial data logic inverse Transmit and receive data are logically inverted * TXD and RXD I/O polarity Inverse The level output from the TXD pin and the level applied to the RXD pin are inverted. * Clock phase One of four combinations of serial clock polarity and phase can be selected Specification
Transmit/receive control
Transmit and receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, ensure that an "H" signal is applied to the CLKi pin when the CKPOL bit in the UiC0 register is set to 0, and that an "L" signal is applied when the CKPOL bit is set to 1. 3. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.15
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(3) P7_1(3) P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
17. Serial Interfaces (UART0 to UART4)
Pin Settings in Special Mode 2
Bit Setting Function SS0 input CLK0 input (slave) RXD0 input (master) PD6, PD7, PD9 Registers(2) PD6_0 = 0 PD6_1 = 0 PD6_2 = 0 - - - - - - - - - - - - - - PSC_0 = 0 - - - PSC_2 = 0 - - - - - - - - - - - - PSC3_6 = 0 - - - PSC, PSC3 Registers PSL0, PSL1, PSL3 Registers - PSL0_1 = 0 - - PSL0_2 = 1 PSL0_3 = 0 - - PSL0_5 = 0 - - PSL0_6 = 1 PSL0_7 = 0 - PSL1_0 = 0 - - PSL1_1 = 1 PSL1_2 = 0 - - PSL3_0 = 0 - - PSL3_1 = 1 PSL3_2 = 0 - PSL3_3 = 0 PSL3_4 = 0 - PSL3_5 = 0 - PSL3_6 = 0 - PSL3_7 = 1 PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_1 = 1 PS0_1 = 0 PS0_2 = 0 PS0_2 = 1 PS0_3 = 1 PS0_3 = 0 PS0_4 = 0 PS0_5 = 1 PS0_5 = 0 PS0_6 = 0 PS0_6 = 1 PS0_7 = 1 PS0_7 = 0 PS1_0 = 1 PS1_0 = 0 PS1_1 = 0 PS1_1 = 1 PS1_2 = 1 PS1_2 = 0 PS1_3 = 0 PS3_0 = 1 PS3_0 = 0 PS3_1 = 0 PS3_1 = 1 PS3_2 = 1 PS3_2 = 0 PS3_3 = 0 PS3_4 = 0 PS3_5 = 1 PS3_5 = 0 PS3_6 = 1 PS3_6 = 0 PS3_7 = 0 PS3_7 = 1
CLK0 output (master) -
STXD0 output (slave) - TXD0 output (master) - SRXD0 input (slave) SS1 input CLK1 input (slave) RXD1 input (master) PD6_3 = 0 PD6_4 = 0 PD6_5 = 0 PD6_6 = 0
CLK1 output (master) -
STXD1 output (slave) - TXD1 output (master) - SRXD1 input (slave) SRXD2 input (slave) RXD2 input (master) PD6_7 = 0 PD7_0 = 0 PD7_1 = 0 TXD2 output (master) -
STXD2 output (slave) - CLK2 output (master) - CLK2 input (slave) SS2 input CLK3 input (slave) RXD3 input (master) PD7_2 = 0 PD7_3 = 0 PD9_0 = 0 PD9_1 = 0
CLK3 output (master) -
STXD3 output (slave) - TXD3 output (master) - SRXD3 input (slave) SS3 input SS4 input CLK4 input (slave) SRXD4 input (slave) RXD4 input (master) PD9_2 = 0 PD9_3 = 0 PD9_4 = 0 PD9_5 = 0 PD9_6 = 0 PD9_7 = 0
CLK4 output (master) - TXD4 output (master) -
STXD4 output (slave) -
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 and P7_1 are N-channel open drain output ports.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
Start initial setting
I flag = 0 UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit IOPOL bit = 0 UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register: SSE bit = 1 CKPH bit DINC bit NODC bit = 0 bits DL2 to DL0 = 000b UiSMR4 register = 00h UiC0 register: bits CLK1 to CLK0 CRD bit = 1 NCH bit CKPOL bit UFORM bit When an internal clock is used UiBRG register = m
Interrupt disabled Clock synchronous mode Clock select bit (1)
SS function enabled Clock phase set bit (2) Serial input pin set bit(1)
UiBRG count source select bits CTS function disabled Data output select bit CLK polarity select bit (2) Bit order select bit
m = 00h to FFh
Baud rate =
fj 2(m + 1)
fj: f1, f8, f2n (3)
UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit = 0 UiLCH bit = 0 bit 7 = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin setting in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Transmit operation disabled Receive operation disabled UARTi transmit interrupt souce select bit
Transmit interrupt priority level select bit Interrupt not requested Receive interrupt priority level select bit Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End initial setting
Transmit/receive operation starts by writing data to UiTB register. Read the UiRB register when the receive operation is completed. i = 0 to 4 NOTES: 1. Set to 0 in master mode, and set to 1 in slave mode. 2. The clock phase is determined by the combination of the CKPH and CKPOL bits in the UiSMR3 register. 3. Bits CNT3 to CNT0 select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.27
Register Settings in Special Mode 2
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.4.1 Master Mode
Master mode is entered when the DINC bit in the UiSMR3 register (i = 0 to 4) is set to 1. The following pins are used in master mode. * TXDi: transmit data output * RXDi: receive data input * CLKi: serial clock output To use the SS function, set the SSE bit in the UiSMR3 register to 1. A transmit and receive operation is performed while an "H" is applied to the SSi pin. If an "L" is applied to the SSi pin, the ERR bit in the UiSMR3 register becomes 1 (mode error occurred) and pins CLKi and TXDi are placed in high-impedance states. Set the UiIRS bit in the UiC1 register to 1 (Transmit completion as interrupt source) to verify whether a mode error has occurred or not by checking the EER bit in the transmission complete interrupt routine. To resume serial communication after a mode error occurs, set the ERR bit to 0 (no mode error) while an "H" signal is applied to the SSi pin. Pins TXDi and CLKi become in output mode.
17.1.4.2 Slave Mode
Slave mode is entered when the DINC bit in the UiSMR3 register is set to 0. The following pins are used in slave mode. * STXDi: transmit data output * SRXDi: receive data input * CLKi: serial clock input To use the SS function, set the SSE bit in the UiSMR3 register to 1. When an "L" signal is applied to the SSi input pin, the serial clock input is enabled, and a transmit and receive operation becomes available. When an "H" signal is applied to the SSi pin, the serial clock input to the CLKi pin is ignored and the STXDi pin is placed in a high-impedance state.
MCU P1_3 P1_2 P9_3(SS3) P9_0(CLK3) P9_1(RXD3) P9_2(TXD3) (Master) P9_3(SS3) P9_0(CLK3) P9_1(STXD3) P9_2(SRXD3) (Slave) MCU MCU
P9_3(SS3) P9_0(CLK3) P9_1(STXD3) P9_2(SRXD3) (Slave)
Figure 17.28
Serial Bus Communication Control with SSi Pin
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.4.3 Clock Phase Setting Function
The clock polarity and clock phase are selected from four combinations of the CKPH and CKPOL bits in the UiSMR3 register (i = 0 to 4). The master must have the same serial clock polarity and phase as the slaves involved in the communication. Figure 17.29 shows a transmit and receive operation timing.
(1) When the CKPH = 0 (no clock delay)
CLKi I/O (CKPOL = 0) "H" "L" "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
CLKi I/O (CKPOL = 1)
SSi input pin In master mode (internal clock) (DINC = 0)
TXDi output Receive data input timing SSi input pin
"H" "L" "H" "L" Hi-Z
undefined
In slave mode (external clock) (DINC = 1)
STXDi output (1) Receive data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Hi-Z
(2) When the CKPH = 1 (clock delay)
CLKi I/O (CKPOL = 0) "H" "L" "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
CLKi I/O (CKPOL = 1)
SSi input pin In master mode (internal clock) (DINC = 0)
TXDi output Receive data input timing SSi input pin
"H" "L" "H" "L" Hi-Z D0 D1 D2 D3 D4 D5 D6 D7
In slave mode (external clock) (DINC = 1)
STXDi output (1) Receive data input timing
Hi-Z
i=0 to 4
CKPH, DINC: bits in the UiSMR3 register CKPOL: bit in the UiC0 register NOTE: 1. P7_0 and P7_1 are N-channel open drain output ports. They must be pulled up externally to output data.
Figure 17.29
Transmit and Receive Operation Timing in Special Mode 2
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.5
Special Mode 3 (GCI Mode)
Full-duplex clock synchronous serial communications are allowed in this mode. When a trigger is input to the CTSi (i = 0 to 4) pin, the internal clock which is synchronized with the continuous external clock is generated, and a transmit and receive operation is started. Table 17.16 lists specifications of GCI mode. Table 17.17 lists pin settings. Figure 17.30 shows register settings. Table 17.16
Data format Serial clock
GCI Mode Specifications
Specification Data length: 8 bits long Select the external clock Set the CKDIR bit in the UiMR register (i = 0 to 4) to 1 (external clock). When a trigger is input, the external clock or the clock divided by 2 becomes the serial clock. A transmit and receive operation starts when a trigger is input to the CTSi pin after all the following are met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 1 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * Set the SCLKSTPB bit in the UiC1 register is set to 0 (clock-divided synchronization stopped) The SCLKSTPB bit becomes 1 (clock-divided synchronization started) when a trigger is input to the CTSi pin The SCLKSTPB bit in the UiC1 register is set to 0 Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) Overrun error(1) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register
Item
Transmit and receive start condition
Transmit and receive stop condition Interrupt request generation timing
Error detection
NOTE: 1. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.17
Port P6_0 P6_1 P6_2 P6_3 P6_4 P6_5 P6_6 P6_7 P7_0(4) P7_1 P7_2 P7_3 P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7
17. Serial Interfaces (UART0 to UART4)
Pin Settings in GCI Mode
Bit Setting Function CTS0 input(3) CLK0 input RXD0 input TXD0 output CTS1 input(3) CLK1 input RXD1 input TXD1 output TXD2 output RXD2 input CLK2 input CTS2 input(3) CLK3 input RXD3 input TXD3 output CTS3 CTS4 input(3) input(3) PD6, PD7, PD9 Registers(2) PD6_0 = 0 PD6_1 = 0 PD6_2 = 0 - PD6_4 = 0 PD6_5 = 0 PD6_6 = 0 - - PD7_1 = 0 PD7_2 = 0 PD7_3 = 0 PD9_0 = 0 PD9_1 = 0 - PD9_3 = 0 PD9_4 = 0 PD9_5 = 0 - PD9_7 = 0 - - - - - - - - PSC_0 = 0 - - - - - - - - - PSC3_6 = 0 - PSC, PSC3 Registers PSL0, PSL1, PSL3 Registers - - - PSL0_3 = 0 - - - PSL0_7 = 0 PSL1_0 = 0 - - - - - PSL3_2 = 0 PSL3_3 = 0 PSL3_4 = 0 PSL3_5 = 0 - - PS0, PS1, PS3 Registers(1)(2) PS0_0 = 0 PS0_1 = 0 PS0_2 = 0 PS0_3 = 1 PS0_4 = 0 PS0_5 = 0 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS1_2 = 0 PS1_3 = 0 PS3_0 = 0 PS3_1 = 0 PS3_2 = 1 PS3_3 = 0 PS3_4 = 0 PS3_5 = 0 PS3_6 = 1 PS3_7 = 0
CLK4 input TXD4 output RXD4 input
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. CTS input is used as a trigger signal input. 4. P7_0 is an N-channel open drain output port.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
Start initial setting
I flag = 0 UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit = 1 IOPOL bit = 0 UiSMR register: bits 6 to 0 = 0000000b SCLKDIV bit UiSMR2 register: bits 6 to 0 = 0000000b SU1HIM bit UiSMR3 register = 00h UiSMR4 register = 00h UiC0 register: bits CLK1 and CLK0 = 00b CRD bit = 1 NCH bit CKPOL bit = 0 UFORM bit = 0 UiBRG register = 00h UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit UiRRM bit = 0 UiLCH bit = 0 SCLKSTPB bit = 0 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin setting in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled Clock synchronous mode Select external clock
Clock division synchronous bit (1)
External clock synchronous enable bit (1)
CTS function disabled Data output select bit
Transmit operation disabled Receive operation disabled UARTi transmit interrupt source select bit Clock-divided synchronization stopped Transmit interrupt priority level select bits Interrupt not requested Receive interrupt priority level select bits Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End initial setting
Transmit/receive operation starts when a trigger is input to the CTSi pin after writing data to the UiTB register. Read the UiRB register when a receive operation is completed.
i = 0 to 4 NOTE: 1. The external clock synchronization function is determined by the combination of the SCLKDIV bit in the UiSMR register and the SU1HIM bit in the UiSMR2 register. Refer to the table " Clock-Divided Synchronous Function Select" for details.
Figure 17.30
Register Settings in GCI Mode
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 261 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
Set the SU1HIM bit in the UiSMR2 register (i = 0 to 4) and the SCLKDIV bit in the UiSMR register to values shown in Table 17.18, and apply a trigger signal to the CTSi pin. Then, the SCLKSTPB bit becomes 1 and a transmit and receive operation starts. Either the same clock cycle as the external clock or the external clock cycle divided by two can be selected for the serial clock. When the SCLKSTPB bit in the UiC1 register is set to 0, a transmission and reception in progress stops immediately. Figure 17.31 shows an example of the clock-divided synchronous function. Table 17.18 Clock-Divided Synchronous Function Select
SU1HIM bit in the UiSMR2 register 0 1 0 or 1 Clock-Divided Synchronous Function Not synchronized Same clock cycle as the external clock External clock cycle divided by 2
SCLKDIV bit in the UiSMR register 0 0 1
External clock from the CLKi pin Trigger signal input to the CTSi pin 1 More than 1 clock cycle is required
Serial clock A TXDi
2
3
4
5
6
7
8 The clock is stopped by the SCLKSTPB bit in the UiC1 register
1
2
3
4
5
6
7
8
Serial clock B TXDi i = 0 to 4 A: When the SCLKDIV bit in the UiSMR register is set to 0, and the SU1HIM bit in the UiSMR2 register is set to 1 B: When the SCLKDIV bit is set to 1, and SU1HIM bit is set to either 0 or 1. 1 2 3 4 5 6 7 8
Figure 17.31
Clock-Divided Synchronous Function
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.6
Special Mode 4 (SIM Mode)
In SIM mode, the MCU can communicate with SIM interface devices using UART mode. Both direct and inverse formats are available. The TXDi pin (i = 0 to 4) outputs a low-level ("L") signal when a parity error is detected. Table 17.19 lists specifications of SIM mode. Table 17.20 list pin settings. Figure 17.32 lists register settings. Figure 17.33 shows an example of SIM interface operation. Figure 17.34 shows an example of SIM interface connection. Table 17.19
Data format
SIM Mode Specifications
Specification * Data length 8-bit UART mode * One stop bit * Direct format: Parity: even Data logic: direct (not inverted) Bit order: LSB first * Inverse format: Parity: odd Data logic: inverse (inverted) Bit order: MSB first Set the CKDIR bit in the UiMR register is 0 (internal clock): fj / (16 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) CTS/RTS function disabled To start transmit operation, all of the following must be met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) To start receive operation, all of the following must be met: * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * The start bit is detected Transmit interrupt: * Set the UiIRS bit in the UiC1 register to 1 (transmit operation completed) when the stop bit is output from the UARTi transmit shift register Receive interrupt: * when data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(2) Overrun error occurs when the preceding bit of the stop bit of the next data is received before reading the UiRB register * Framing error Framing error occurs when the number of the stop bits set using the STPS bit in the UiMR register is not detected * Parity error Parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set with the PRY bit in the UiMR register. * Error sum flag Error sum flag becomes 1 when an overrun, framing, or parity error occurs
Item
Baud rate
Transmit/receive control Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC register remains unchanged as 0 (interrupt not requested).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.20
Port P6_2 P6_3 P6_6 P6_7 P7_0(3) P7_1 P9_1 P9_2 P9_6 P9_7
17. Serial Interfaces (UART0 to UART4)
Pin Settings in SIM Mode
Bit Setting Function RXD0 input TXD0 output RXD1 input TXD1 output TXD2 output RXD2 input RXD3 input TXD3 output TXD4 output RXD4 input PD6, PD7, PD9 Registers(2) PD6_2 = 0 - PD6_6 = 0 - - PD7_1 = 0 PD9_1 = 0 - - PD9_7 = 0 - - - - PSC_0 = 0 - - - PSC3_6 = 0 - PSC, PSC3 Registers PSL0, PSL1, PSL3 Registers - PSL0_3 = 0 - PSL0_7 = 0 PSL1_0 = 0 - - PSL3_2 = 0 - - PS0, PS1, PS3 Registers(1)(2) PS0_2 = 0 PS0_3 = 1 PS0_6 = 0 PS0_7 = 1 PS1_0 = 1 PS1_1 = 0 PS3_1 = 0 PS3_2 = 1 PS3_6 = 1 PS3_7 = 0
NOTES: 1. Set registers PS0, PS1, and PS3 after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. P7_0 is an N-channel open drain output port.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
Start initial setting
I flag = 0 UiMR register: bits SMD2 to SMD0 = 101b CKDIR bit = 0 STPS bit = 0 PRY bit PRYE bit = 1 IOPOL bit = 0 UiSMR register = 00h UiSMR2 register = 00h UiSMR3 register = 00h UiSMR4 register = 00h UiC0 register: bits CLK1 and CLK0 CRD bit = 1 NCH bit = 1 CKPOL bit = 0 UFORM bit UiBRG register = m UiC1 register: TE bit = 0 RE bit = 0 UiIRS bit = 1 UiRRM bit = 0 UiLCH bit UiERE bit = 1 SiTIC register: bits ILVL2 to ILVL0 IR bit = 0 SiRIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin setting in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled UART mode: 8-bit data length Select internal clock Select 1 stop bit Parity select bit (1) Parity enabled
UiBRG register count source select bits CTS function disabled N-channel open drain output Bit order select bit(2) m = 00h to FFh Baud rate = fj 16(m + 1) fj = f1, f8, f2n (3)
Transmit operation disabled Receive operation disabled Transmit completion as transmit interrupt source Data logic select bit (2) Error signal output enabled Transmit interrupt priority level select bits Interrupt not requested Receive interrupt priority level select bits Interrupt not requested
Interrupt enabled Transmit operation enabled Receive operation enabled
End initial setting
Transmit operation starts by writing data to the UiTB register Receive operation starts when the start bit is detected. Read the UiRB register when the receive operation is completed.
i = 0 to 4 NOTES: 1. Set to 1 in the direct format, and set to 0 in the inverse format. 2. Set to 0 in the direct format, and set to 1 in the inverse format. 3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 4. Determine whether an "L" is output from the TXDi pin by reading the port that shares a pin with the RXDi pin in the receive operation complete interrupt routine. When an "L" is output, wait for one clock cycle to read the UiRB register.
Figure 17.32
Register Settings in SIM Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
(1) Transmit operation
Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register TXDi output Parity error signal sent back from receiving device Signal line level(2) TXEPT bit in the UiC0 register IR bit in the SiTIC register 1 0 1 0 1 0 1 0 "H" "L"
TC
(note 1) Data is set in UiTB register
Data is transfer from UiTB register to UARTi transmit shift register
Start bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit
Detect the level in interrupt routine
"L" level is sent back from the SIM card since parity error has occurred
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) - UiC1 register: UiIRS bit = 1 (transmit interrupt is generated at the transmit completion)
(2) Receive operation
Internal receive clock RE bit in the UiC1 register Transmit waveform sent by transmitting device TXDi ouput "H" "L" 1 0
TC
Start bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Parity bit "L" level is sent back from the SIM card since parity error has occurred
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
Signal line level(3) RI bit in the UiC1 register IR bit in the SiRIC register 1 0 1 0
Read from the UiRB register
Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) i = 0 to 4 TC = 16( m+ 1) fj fj: f1, f8, f2n (4) m: setting value of the UiBRG register (00 to FF)
NOTES: 1. Transmit operation is started when UiBRG overflows after data is set in the UiTB register in the indicated timing. 2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity error signal from the receiving device, is generated. 3. Because pins TXDi and RXDi are connected, a composite waveform consisting of transmit waveform from the transmitting device and parity error signal from the TXDi pin, is generated. 4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.33
SIM Interface Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
MCU SIM card
TXDi
RXDi
i = 0 to 4 NOTE: 1. Connect the TXDi and RXDi pins and pull up these pins.
Figure 17.34
SIM Interface Connection
17.1.6.1 Parity Error Signal Output Function
When the UiERE bit in the UiC1 register (i = 0 to 4) is set to 1 (error signal output), the parity error signal output is enabled. The parity error signal is output when a parity error is detected upon receiving data, and an "L" signal is output from the TXDi pin in the timing shown in Figure 17.35. If the UiRB register is read while a parity error signal is output, the PER bit in the UiRB register is set to 0 (no parity error) and the TXDi pin level becomes back to "H". To determine whether the parity error signal is output or not, read the port that shares a pin with the RXDi pin in the transmission complete interrupt routine.
RXDi
"H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TXDi
"H" "L"
Hi-Z
Receive operation complete flag
1 0
i = 0 to 4 ST: Start bit P: Even parity bit SP: Stop bit
The above applies under direct format conditions: - UiMR register: PRY bit = 1 (even parity) - UiC0 register: UFORM bit = 0 (LSB first) - UiC1 register: UiLCH bit = 0 (not inverted)
Figure 17.35
Parity Error Signal Output Timing
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.6.2 Formats 17.1.6.2.1 Direct Format
When data is transmitted, data set in the UiTB register (i = 0 to 4) is transmitted with even parity, starting from D0. When data is received, received data is stored into the UiRB register, starting from D0. A parity error is determined with even parity. Set the bits as follows to transmit or receive in the direct format. * Set the PRYE bit in the UiMR register to 1 (parity enabled). * Set the PRY bit in the UiMR register to 1 (even parity). * Set the UFORM bit in the UiC0 register to 0 (LSB first). * Set the UiLCH bit in the UiC1 register to 0 (not inverted).
17.1.6.2.2 Inverse Format
When data is transmitted, values set in the UiTB register are logically inverted. The data with the inverted values is transmitted with odd parity, starting from D7. When data is received, received data is logically inverted to be stored into the UiRB register, starting from D7. A parity error is determined with odd parity. Set the bits as follows to transmit or receive in the inverse format. * Set the PRYE bit to 1 (parity enabled). * Set the PRY bit to 0 (odd parity). * Set the UFORM bit to 1 (MSB first). * Set the UiLCH bit to 1 (inverted).
(1) Direct format
TXDi "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7
P: Even parity P SP
(2) Inverse format
TXDi "H" "L" ST D7 D6 D5 D4 D3 D2 D1 D0
P: Odd parity P SP ST: Start bit SP: Stop bit
i = 0 to 4
Figure 17.36
SIM Interface Formats
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
17.1.7
Special Mode 5 (IrDA mode) * * * UART0
Input and output data in clock asynchronous mode are converted into the format supporting IrDA physical layer specification v.1.0. The UART0 transmit data is encoded and output in the RZI (Return to Zero Inverted) format. Input data in the RZI format is decoded to the NRZ (None Return to Zero) format and becomes the UART0 reception input data. Refer to the 17.1.2 Clock Asynchronous (UART) Mode for details on clock asynchronous mode. Table 17.21 lists specifications of IrDA mode. Figure 17.37 shows a block diagram. Figure 17.38 shows a register associated with IrDA mode. Figure 17.39 shows an IrDA operation. Table 17.21 IrDA Mode Specifications
Specification * PLSSEL bit in the IRCON register is set to 0 (3/16 of the bit rate) 3 16 bit time
Item "0" output pulse width
* PLSSEL bit is set to 1 (set by bits IRPD0, IRPD1, IRCK) Selectable among "0" input pulse width I/O polarity 1 2 4 8 3 fi fi , fi , fi , fi fi = f1 or f8
Input the pulse which is longer than
Encode logic "0" to a high pulse, decode a high pulse as logic "0" Encode logic "0" to a low pulse, decode a low pulse as logic "0"
IRPD1 and IRPD0 00 01 f1 f8 0 1 IRCK 1/2 1/2 1/2 10 11 PLSSEL
1 U0BRG clock Internal transmit clock UART0 Module Transmission output Internal receive clock Reception input IRSEL 1 0 0
0 Pulse Encoder 1
IRTPOL 1 0 IRSEL TXD0/IrDAOUT 3 fi
IRRPOL Pulse Decoder
0 1
Eliminate the pulse shorter than Filter
RXD0/IrDAIN
Figure 17.37
IrDA Mode Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
IrDA Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IRCON
Bit Symbol IRSEL Bit Name IrDA select bit
Address 0372h
Function 0: TXD0, RXD0 1: IrDAOUT, IrDAIN 0: 3/16 of the bit rate 1: Set by bits IRPD0, IRPD1, IRCK 0: Encode logic "0" as a high pulse 1: Encode logic "0" as a low pulse 0: Decode high pulse as logic "0" 1: Decode low pulse as logic "0"
b5 b4
After Reset X000 0000b
RW RW
PLSSEL
Logic "0" output pulse width select bit IrDAOUT output polarity switch bit IrDAIN input polarity switch bit
RW
IRTPOL
RW
IRRPOL
RW
IRPD0 Logic "0" output pulse width set bits IRPD1 Logic "0" output pulse count source select bit (1) Unimplemented. Write 0. Read as undefined value.
0 0 1 1
0: 1/fi (fi = f1, f8) 1: 2/fi 0: 4/fi 1: 8/fi
RW
IRCK
0: f1 1: f8
RW
- (b7)
-
NOTE 1. IRCK bit is enabled when the PLSSEL bit is set to 1.
Figure 17.38
IRCON Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART0 to UART4)
(1) Transmit operation
Start bit
8-bit data
Stop bit
UART0 transmission output IrDA output (IRTPOL = 0) IrDA output (IRTPOL = 1)
"0"
"1"
"0"
"1"
"1"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"1"
"1"
"0"
"1"
"0"
"1"
"0" (2) Receive operation IrDA input (IRRPOL = 1) "0" IrDA input (IRRPOL = 0) "0"
"1"
"0"
"1"
"1"
"1"
"0"
"1"
"0"
"1"
"1"
"0"
"1"
"1"
"1"
"0"
"1"
"0"
"1"
"1"
Start bit
"0"
"1"
"1"
"1" 8-bit data
"0"
"1"
"0"
"1"
Stop bit
UART0 reception input
"0"
"1"
"0"
"1"
"1"
"1"
"0"
"1"
"0"
"1"
Figure 17.39
IrDA Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2
UART5 and UART6
Figure 17.40 shows a UART5 and UART6 block diagram. Figures 17.41 to 17.45 show the registers associated with UART5 and UART6. Refer to the tables listing register and pin settings in each mode. Refer to 11.11 Intelligent I/O, CAN, UART5, UART6, and INT6 to INT8 Interrupts for details on UART5 and UART6 transmit/receive interrupts.
RXDi CLK1 and CLK0 00 CKDIR f1 01 0 f8 1 1/16
SMD2 to SMD0 100, 101, 110 001 100, 101, 110 001 0 1 CKDIR UiBRG register 1/(m+1) Receive control circuit Transmit control unit
TXDi Receive Transmit/ clock receive unit Transmit clock
F2n(1) 10
1/16
CKPOL CLKi CLKi input Function Select Register(2) CLKi output CTSi / RTSi Polarity switching Polarity switching
1/2
RTSi output CTSi input Function Select (3) CRD Register CRS
m: Setting value of the UiBRG register NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. Select either I/O port (CLKi input) or CLKi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) 3. Select either I/O port or RTSi output in the Function Select Registers. (Refer to the chapter Programmable I/O Ports.) 001 101 b8 b7 110 UARTi receive shift register b6 001 101 110 b5 b4 b3 b2 b1 b0
RXDi
SP
STPS 0 1
PRYE 001 0 SP PAR 1 100 101 110
100
SMD2 to SMD0 0 0 0 0 0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UiRB register
Logic inverse circuit + MSB/LSB conversion circuit High-order bits of data bus Low-order bits of data bus Logic inverse circuit + MSB/LSB conversion circuit D8 D7 D6 D5 D4 D3 D2 D1 D0 UiTB register
STPS 0 SP SP 1
PRYE 001 0 PAR 1 100 101 110
001 101 b8 b7 110
100 b6 001 101 110 b5 b4 b3 b2 b1 b0 TXDi UARTi transmit shift register
SMD2 to SMD0
i = 5, 6 SP: Stop bit PAR: Parity bit SMD2 to SMD0, STPS, PRYE, CKDIR: bits in the UiMR register CLK1 to CLK0, CKPOL, CRD, CRS: bits in the UiC0 register
Figure 17.40
UART5 and UART6 Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
UART5, UART6 Input Pin Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U56IS
Bit Symbol U5CLK Bit Name
Address 01D1h
Function 0: P7_7 1: P15_1 0: P8_0 1: P15_2 0: P8_1 1: P15_3
After Reset X000 X000b
RW RW
CLK5 input pin select bit(1)
U5RXD
RXD5 input pin select bit (1)
RW
U5CTS
CTS5 input pin select bit(1) Unimplemented. Write 0. Read as undefined value. CLK6 input pin select bit(2)
RW
- (b3)
U6CLK
-
0: P15_6 1: P12_1 0: P15_5 1: P12_2 0: P15_7 1: P12_3
RW
U6RXD
RXD6 input pin select bit (2)
RW
U6CTS
CTS6 input pin select bit(2) Unimplemented. Write 0. Read as undefined value.
RW
- (b7)
-
NOTES: 1. Set bits U5CLK, U5RXD, and U5CTS to 0 in the 100-pin package. 2. Bits U6CLK, U6RXD, and U6CTS are provided in the 144-pin package only.
Figure 17.41
U56IS Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
UARTi Transmit/Receive Mode Register (i = 5, 6)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U5MR, U6MR
Bit Symbol SMD0 Bit Name
Address 01C0h, 01C8h
Function
After Reset 00h
RW RW
b2 b1 b0
SMD1
Serial interface mode select bits
SMD2
0 0 0: Serial interface disabled 0 0 1: Clock synchronous mode 1 0 0: UART mode, 7-bit data length 1 0 1: UART mode, 8-bit data length 1 1 0: UART mode, 9-bit data length Do not set values other than the above
RW
RW
CKDIR
Clock select bit
0: Internal clock 1: External clock 0: 1 stop bit 1: 2 stop bits Enables when PRYE = 1 0: Odd parity 1: Even parity 0: Parity disabled 1: Parity enabled Set to 0
RW
STPS
Stop bit length select bit
RW
PRY
Parity select bit
RW
PRYE
Parity enable bit
RW
- (b7)
Reserved bit
RW
Figure 17.42
U5MR and U6MR Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 274 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
UARTi Transmit/Receive Control Register 0 (i = 5, 6)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U5C0, U6C0
Bit Symbol CLK0 UiBRG count source select bits(1) CLK1 Bit Name
Address 01C4h, 01CCh
Function
b1 b0
After Reset 0000 1000b
RW RW
0 0: f1 selected 0 1: f8 selected 1 0: f2n selected(2) 1 1: Do not set to this value Enabled when CRD=0 0: CTS function selected 1: CTS function not selected 0: Data in the transmit shift register (during transmit operation) 1: No data in the transmit shift register (transmit operation is completed) 0: CTS function enabled 1: CTS function disabled Set to 0 0: Transmit data output at the falling edge and receive data input at the rising edge of the serial clock 1: Transmit data output at the rising edge and receive data input at the falling edge of the serial clock 0: LSB first 1: MSB first
RW
CRS
CTS function select bit
RW
TXEPT
Transmit shift register empty flag
RO
CRD
CTS function disable bit
RW
- (b5)
Reserved bit
RW
CKPOL
CLK polarity select bit
RW
UFORM
Bit order select bit (3)
RW
NOTES: 1. Set bits CLK1 and CLK0 before setting the UiBRG register. 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). To select f2n, set the CST bit in the TCSPR register to 1 before setting bits CLK1 and CLK0 to 10b . 3. The UFORM bit is enabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) or 101b (UART mode, 8-bit data length). Set the UFORM bit to 0 when bits SMD2 to SMD0 are set to 100b (UART mode, 7-bit data length) or 110b (UART mode, 9-bit data length).
UARTi Baud Rate Register(1, 2) (i = 5, 6)
b7 b0
Symbol U5BRG, U6BRG
Function
Address 01C1h, 01C9h
After Reset Undefined
Setting Range 00h to FFh RW WO
If the setting value is n, the UiBRG register divides the count source by n+1
NOTES: 1. Read-modify-write instructions cannot be used to set the UiBRG register. Refer to Usage Notes for details. 2. Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register.
Figure 17.43
U5C0 and U6C0 Registers, U5BRG and U6BRG Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
UART5, UART6 Transmit/Receive Control Register
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol U56CON
Bit Symbol U5IRS Bit Name UART5 transmit interrupt source select Bit UART6 transmit interrupt source select Bit
Address 01D0h
Function
After Reset X000 0000b
RW RW
0: No data in the U5TB register (TI = 1) 1: Transmit operation is completed (TXEPT = 1) 0: No data in the U6TB register (TI = 1) 1: Transmit operation is completed (TXEPT = 1) 0: Continuous receive mode disabled 1: Continuous receive mode enabled (1) 0: Continuous receive mode disabled 1: Continuous receive mode enabled (1) Set to 0
U6IRS
RW
U5RRM
UART5 continuous receive mode enable bit UART6 continuous receive mode enable bit Reserved bits Unimplemented. Write 0. Read as undefined value.
RW
U6RRM
RW
- (b6-b4) - (b7)
RW
-
NOTE: 1. When the UiRRM bit (i = 5, 6) is set to 1, set the CKDIR bit in the UiMR register to 1 (external clock) and also disable the RTS function.
UARTi Transmit/Receive Control Register 1 (i = 5, 6)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U5C1, U6C1
Bit Symbol TE Bit Name Transmit enable bit
Address 01C5h, 01CDh
Function 0: Transmit operation disabled 1: Transmit operation enabled 0: Data in the UiTB register 1: No data in the UiTB register 0: Receive operation disabled 1: Receive operation enabled 0: No data in the UiRB register 1: Data in the UiRB register
After Reset XXXX 0010b
RW RW
TI
UiTB register empty flag
RO
RE
Receive enable bit
RW
RI
Receive complete flag Unimplemented. Write 0. Read as undefined value.
RO
- (b7-b4)
-
Figure 17.44
U56CON Register, U5C1 and U6C1 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
UARTi Transmit Buffer Register(1) (i = 5, 6)
b15 b8 b7 b0
Symbol U5TB, U6TB
Bit Symbol
Address 01C3h - 01C2h, 01CBh - 01CAh
Function Transmit data (D7 to D0)
After Reset Undefined
RW WO
- (b7-b0) - (b8) - (b15-b9)
Transmit data (D8) Unimplemented. Write 0. Read as undefined value.
WO
-
NOTE: 1. Read-modify-write instructions cannot be used to set the UiTB register. Refer to Usage Notes for details.
UARTi Receive Buffer Register (i = 5, 6)
b15 b8 b7 b0
Symbol U5RB, U6RB
Bit Symbol Bit Name
Address 01C7h - 01C6h,01CFh - 01CEh
Function Receive data (D7 to D0)
After Reset Undefined
RW RO
- (b7-b0) - (b8) - (b11-b9)
OER Unimplemented. Write 0. Read as undefined value. Overrun error flag(1)
Receive data (D8)
RO
-
0 : No overrun error 1 : Overrun error 0 : No framing error 1 : Framing error 0 : No parity error 1 : Parity error 0: No error occurred 1: Error occurred
RO
FER
Framing error flag(1, 2)
RO
PER
Parity error flag(1, 2)
RO
SUM
Error sum flag(1, 2)
RO
NOTES: 1. When bits SMD2 to SMD0 in the UiMR register are set to 000b (serial interface disabled) or the RE bit in the UiC1 register is set to 0 (receive operation disabled), bits OER, FER, PER, and SUM become 0. When all of bits OER, FER, and PER become 0, the SUM bit also becomes 0. Bits FER and PER become 0 by reading the low-order byte in the UiRB register. 2. Bits FER, PER, and SUM are disabled when bits SMD2 to SMD0 in the UiMR register are set to 001b (clock synchronous mode) . A read from these bits returns undefined value.
Figure 17.45
U5TB and U6TB Registers, U5RB and U6RB Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.1
Clock Synchronous Mode
Full-duplex clock synchronous serial communications are allowed in this mode. CTS/RTS function can be used for transmit and receive control. Table 17.22 lists specifications of clock synchronous mode. Table 17.23 lists pin settings. Figure 17.46 shows register settings. Figure 17.47 shows an example of a transmit and receive operation when an internal clock is selected. Figure 17.48 shows an example of a receive operation when an external clock is selected. Table 17.22
Data format Serial clock Baud rate
Clock Synchronous Mode Specifications
Specification Data length: 8 bits long Internal clock or external clock can be selected with the CKDIR bit in the UiMR register (i = 5 and 6). * When the CKDIR bit is set to 0 (internal clock): fj / (2 (m + 1)) fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh) * When the CKDIR bit is set to 1 (external clock): clock input to the CLKi pin Selectable among the CTS function, RTS function, or CTS/RTS function disabled Internal clock is selected: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * "L" signal is applied to the CTSi pin when the CTS function is used External clock is selected(2): * Set the TE bit to 1 * The TI bit is 0 * Set the RE bit to 1 * The RI bit in the UiC1 register is 0 when the RTS function is used When above 4 conditions are met, RTSi pin outputs "L" If transmit-only operation is performed, the RE bit setting is not required in both cases. Transmit interrupt (The UiIRS bit in the U56CON register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when data transmit operation from the UARTi transmit shift register is completed Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) Overrun error(3) Overrun error occurs when the 7th bit of the next data is received before reading the UiRB register * CLK polarity Transmit data output timing and receive data input timing can be selected * LSB first or MSB first Data is transmitted and received from either bit 0 or bit 7 * Continuous receive mode The TI bit becomes 0 by reading the UiRB register
Item
Transmit/receive control Transmit and receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an external clock is selected, ensure that an "H" signal is applied to the CLKi pin when the CKPOL bit in the UiC0 register is set to 0, and that an "L" signal is applied when the CKPOL bit is set to 1. 3. If an overrun error occurs, a read from the UiRB register returns undefined values. The U5RR bit in the IIO0IR register and the U6RR bit in the IIO9IR register remain unchanged as 0 (interrupt not requested).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.23 Pin Settings in Clock Synchronous Mode
17. Serial Interfaces (UART5 and UART6)
Bit Setting Port Function PD7, PD8, PD12, PD15 Registers - - U56IS Register PSE1, PSE2 Registers PSD1, PSD2 Registers PSC, PSC2, PSC6 Registers PSL1, PSL2, PSL6, PSL9 Registers - - - PS1, PS2, PS6, PS9 Registers
(1)
P7_6 P7_7 P8_0 P8_1 P12_0 P12_1 P12_2 P12_3 P15_0 P15_1 P15_2 P15_3 P15_4 P15_5 P15_6 P15_7
TXD5 output(2) -
PSE1_6 = 1 PSD1_6 = 1 PSC_6 = 0 PSL1_6 = 0 PS1_6 = 1 - - - - - - - - - - - - - - - - - - - - - - - - PS1_7 = 0 PS2_0 = 0 PS2_1 = 0 PSE1_7 = 0 PSD1_7 = 1 - PSL1_7 = 1 PS1_7 = 1
CLK5 input CLK5 output RXD5 input CTS5 input RTS5 output CLK6 input CLK6 output RXD6 input CTS6 input RTS6 output CLK5 input(3)
PD7_7 = 0 - PD8_0 = 0 PD8_1 = 0 -
U5CLK = 0 - U5RXD = 0 - U5CTS = 0 - - - - - -
PSE2_1 = 0 PSD2_1 = 1 PSC2_1 = 1 PSL2_1 = 1 PS2_1 = 1 PSC6_0 = 1 PSL6_0 = 0 PS6_0 = 1 - - - - - - - - - - - - - - - - - - PS6_1 = 0 - PS6_3 = 0 PSC6_1 = 1 PSL6_1 = 0 PS6_1 = 1
TXD6 output(2) -
PD12_1 = 0 U6CLK = 1 - - PD12_2 = 0 U6RXD = 1 - PD12_3 = 0 U6CTS = 1 - - - - - - - -
PSC6_3 = 1 PSL6_3 = 0 PS6_3 = 1 PSL9_0 = 1 PS9_0 = 1 - - - - - - - - - PS9_1 = 0 - PS9_3 = 0 PS9_3 = 1 - PS9_6 = 0 PS9_6 = 1 PS9_7 = 0 PS9_7 = 1 PSL9_1 = 1 PS9_1 = 1
TXD5 output(2) -
PD15_1 = 0 U5CLK = 1 - -
CLK5 output
RXD5 input(3) PD15_2 = 0 U5RXD = 1 - CTS5 input(3) PD15_3 = 0 U5CTS = 1 - RTS5 output - - - - -
TXD6 output(2) -
PSL9_4 = 1 PS9_4 = 1
RXD6 input(3) PD15_5 = 0 U6RXD = 0 - CLK6 CTS6 input(3) input(3) PD15_6 = 0 U6CLK = 0 - - - - - - - PD15_7 = 0 U6CTS = 0 - CLK6 output RTS6 output
NOTE: 1. Set registers PS1, PS2, PS6 and PS9 after setting the other registers. 2. After UARTi (i = 5, 6) operating mode is selected in the UiMR register and the pin function is set in the Function Select Registers, the TXDi pin outputs an "H" signal until a transmit operation starts. 3. Set both the IPSB_k bit in the IPSB register and the IPS2 bit in the IPS register to 0, when the port P15_k (k = 0 to 7) is used for a peripheral function input.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
Start initial setting
I flag = 0 IIOkIE register: UiTE bit = 0 UiRE bit = 0 U56IS register: UiCLK bit UiRXD bit UiCTS bit UiMR register: bits SMD2 to SMD0 = 001b CKDIR bit bits 7 to 4 = 0000b UiC0 register: bits CLK1 and CLK0 CRS bit CRD bit bit 5 = 0 CKPOL bit UFORM bit < When an internal clock is used> UiBRG register = m
Interrupt disabled UARTi transmit interrupt disabled UARTi receive interrupt disabled CLKi input pin select bit RXDi input pin select bit CTSi input pin select bit Clock synchronous mode Clock select bit
UiBRG register count source select bits CTS function select bit CTS function disable bit CLK polarity select bit Bit order select bit
m = 00h to FFh
Baud rate =
fj 2(m + 1)
fj: f1, f8, f2n (1)
U56CON register: UiIRS bit UiRRM bit bits 6 to 4 = 000b IIOkIR register = 00h (3) IIOkIE register: IRLT bit = 1 IIOkIE register: UiTE bit = 1 UiRE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in the Function Select Registers I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
UARTi transmit interrupt source select bit Continuous receive mode enable bit(2)
UARTi receive interrupt not requested Uses an interrupt request for interrupt UARTi transmit interrupt enabled UARTi receive interrupt enabled Interrupt priority level select bit Interrupt not requested
Do not set these bits simultaneously. Enable the interrupts after setting the IRLT bit to 1.
Interrupt enabled Transmit operation enabled Receive operation enabled
End initial setting
Transmit/receive operation starts by writing data to the UiTB register. Read the UiRB register when a receive operation is completed. k = 0, 1 when i = 5, k = 9, 10 when i = 6 NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. The UiRRM bit can be set to 1 (continuous receive mode enabled), only when the CKDIR bit in the UiMR register is set to 1 (external clock) and RTS function is disabled. 3. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated. (An interrupt does not be occur.)
Figure 17.46
Register Settings in Clock Synchronous Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
TC Internal clock TE bit in the UiC1 register 1 0 1 0 "H" "L" "H" "L" "H" "L" 1 0 1 0 "H" "L" 1 0 1 0
Set to 0 by an interrupt request acknowledgement or by a program D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Write data to the UiTB register
TI bit in the UiC1 register
Transfer data from UiTB register to UARTi transmit shift register
CTSi Input
TCLK
Communication stops because CTSi = "H"
Communication stops because TE bit = 0
CLKi output
TXDi output TXEP bit in the UiC0 register UiTR bit in the IIOjIR register
RXDi input
D0 D1 D2 D3 D4 D5 D6 Transfer data from UARTi receive shift register to UiRB register
D7
D0 D1 D2 D3 D4 D5 D6
D7
D0 D1 D2 D3 D4 D5
RI bit in the UiC1 register UiRR bit in the IIOkIR register
A read from the UiRB register
Set to 0 by an interrupt request acknowlegement or by a program
j = 1, k = 0 when i = 5, j = 10, k = 9 when i = 6
TC = TCLK =
2(m + 1) fj
fj = f1, f8, f2n (1) The above applies under the following conditions: m = Setting value of the UiBRG register - UiMR register: CKDIR bit = 0 (internal clock) (00h to FFh) - UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used) CKPOL bit = 0 (transmit data output at the falling edge of the serial clock) - U56CON register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register) NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.47
Transmit and Receive Operation when Internal Clock is Selected
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
RE bit in the UiC1 register TE bit in the UiC1 register TI bit in the UiC1 register
1 0 1 0 1 0 "H" "L" "H" "L" "H" "L" 1 0 1 0 1 0
Set to 0 by an interrupt request acknowledgement or by a program D0 D1 D2 D3 D4 D5 D6 Transfer data from UARTi receive shift register to UiRB register D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Write dummy data to UiTB register
Transfer data from UiTB register to UARTi transmit shift register 1 fEXT
RTSi output
Becomes "L" by reading UiRB register
CLKi input(1)
RXDi input
RI bit in the UiC1 register UiRR bit in the IIOkIR register OER bit in the UiRB register
A read from UiRB register
k = 0 when i = 5, k = 9 when i = 6 fEXT = external clock frequency The above applies under the following conditions: - UiMR register: CKDIR bit = 1 (external clock) - UiC0 reigster: CRD bit = 1 (CTS function disabled) CKPOL bit = 0 (receive data input at the rising edge of the serial clock) NOTE: 1. Satisfy the following conditions, while the CLKi pin input is "H" before the data receive operation. - UiC1 register: TE bit = 1 (transmit operation enabled) RE bit = 1 (receive operation enabled) - Write dummy data to the UiTB register
Figure 17.48
Receive Operation when External Clock is Selected
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.1.1 CLK Polarity
As shown in Figure 17.49, the CKPOL bit in the UiC0 register (i = 5, 6) determines the polarity of the serial clock.
(1) When the CKPOL bit in the UiC0 register (i = 5, 6) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock )
CLKi "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 (note 1)
TXDi
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock)
CLKi "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7 (note 2)
TXDi
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
The above applies under the following conditions: - UiC0 regsiter: UFORM bit = 0 (LSB first). NOTES: 1. The CLKi pin output level is "H" when no transmit and receive operation is in progress. 2. The CLKi pin output level is "L" when no transmit and receive operation is in progress.
Figure 17.49
Serial Clock Polarity
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.1.2 LSB First or MSB First
As shown in Figure 17.50, the UFORM bit in the UiC0 register (i = 5, 6) determines a bit order.
(1) When the UFORM bit in the UiC0 register (i = 5, 6) is set to 0 (LSB first)
CLKi "H" "L" "H" "L" "H" "L" D0 D1 D2 D3 D4 D5 D6 D7
TXDi
RXDi
D0
D1
D2
D3
D4
D5
D6
D7
(2) When the UFORM bit is set to 1 (MSB first)
CLKi TXDi "H" "L" "H" "L" "H" "L" D7 D6 D5 D4 D3 D2 D1 D0
RXDi
D7
D6
D5
D4
D3
D2
D1
D0
The above applies under the following conditions: - UiC0 register: CKPOL bit = 0 (transmit data is output at the falling edge of the serial clock and received data is input at the rising edge).
Figure 17.50
Bit order (8-Bit Data Length)
17.2.1.3 Continuous Receive Mode
Continuous receive mode can be used when all of the following conditions are met. * External clock is selected (the CKDIR bit in the UiMR register (i = 5 and 6) is set to 1) * RTS function is disabled (RTSi pin is not selected in the Function Select Register) When the UiRRM bit in the U56CON register is set to 1 (continuous receive mode enabled), the TI bit in the UiC1 register becomes 0 (data in the UiTB register) by reading the UiRB register. Do not set dummy data to the UiTB register if the UiRRM bit is set to 1.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.1.4 CTS/RTS Function
* CTS Function
Transmit and receive operation is controlled by using the input signal to the CTSi pin (i = 5 and 6). To use the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function enabled), and the CRS bit to 0 (CTS function selected). With the CTS function used, the transmit and receive operation starts when all the following conditions are met and an "L" signal is applied to the CTSi pin. -The TE bit in the UiC1 register is set to 1 (transmit operation enabled) -The TI bit in the UiC1 register is 0 (data in the UiTB register) -The RE bit in the UiC1 register is set to 1 (receive operation enabled) (If transmit-only operation is performed, the RE bit setting is not required) When a high-level ("H") signal is applied to the CTSi pin during transmitting and receiving, the transmit and receive operation is disabled after the transmit and receive operation in progress is completed.
* RTS Function
The MCU can inform the external device that it is ready for a transmit and receive operation by using the output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register. With the RTS function used, the RTSi pin outputs an "L" signal when all the following conditions are met, and outputs an "H" when the serial clock is input to the CLKi pin. -The RI bit in the UiC1 register is 0 (no data in the UiRB register) -The TE bit is set to 1 (transmit operation enabled) -The RE bit is set to 1 (receive operation enabled) (If transmit-only operation is performed, the RE bit setting is not required) -The TI bit is 0 (data in the UiTB register)
17.2.1.5 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in clock synchronous mode. (1) Set the TE bit in the UiC1 register (i = 5 and 6) to 0 (transmit operation disabled) and the RE bit to 0 (receive operation disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 001b (clock synchronous mode). (4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.2
Clock Asynchronous (UART) Mode
Full-duplex asynchronous serial communications are allowed in this mode. Table 17.24 lists specifications of UART mode. Table 17.25 lists pin settings. Figure 17.51 shows register settings. Figure 17.52 shows an example of a transmit operation. Figure 17.53 shows an example of a receive operation. Table 17.24
Data format
UART Mode Specifications
Specification * Data length: selectable among 7 bits, 8 bits, or 9 bits long * Start bit: 1 bit long * Parity bit: selectable among odd, even, or none * Stop bit: selectable from 1 bit or 2 bits long fj / (16 (m + 1)) fj = f1, f8, f2n(1), fEXT m: setting value of the UiBRG register (00h to FFh) (i = 5, 6) fEXT: clock input to the CLKi pin when the CKDIR bit in the UiMR register is set to 1 (external clock) Selectable among CTS function, RTS function or CTS/RTS function disabled To start transmit operation, all of the following must be met: * Set the TE bit in the UiC1 register to 1 (transmit operation enabled) * The TI bit in the UiC1 register is 0 (data in the UiTB register) * Apply a low-level ("L") signal to the CTSi pin when the CTS function is selected To start receive operation, all of the following must be met: * Set the RE bit in the UiC1 register to 1 (receive operation enabled) * The RI bit is 1 (no data in UiRB register) when RTS function is used. When the above two conditions are met, the RTSi pin output an "L" signal. * The start bit is detected Transmit interrupt (The UiIRS bit in the U56CON register selects one of the following): * The UiIRS bit is set to 0 (no data in the UiTB register): when data is transferred from the UiTB register to the UARTi transmit shift register (transmit operation started) * The UiIRS bit is set to 1 (transmit operation completed): when the final stop bit is output from the UARTi transmit shift register Receive interrupt: * When data is transferred from the UARTi receive shift register to the UiRB register (receive operation completed) * Overrun error(2) Overrun error occurs when the preceding bit of the final stop bit of the next data (the first stop bit when selecting 2 stop bits) is received before reading the UiRB register * Framing error Framing error occurs when the number of the stop bits set by the STPS bit in the UiMR register is not detected * Parity error Parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set by the PRY bit in the UiMR register. * Error sum flag Error sum flag is set to 1 when any of overrun, framing, and parity errors occurs * LSB first or MSB first Data is transmitted or received from either bit 0 or bit 7
Item
Baud rate
Transmit/receive control Transmit start condition
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTES: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 2. If an overrun error occurs, the content of the UiRB register is undefined. The U5RR bit in the IIO0IR register and the U6RR bit in the IIO9IR register remain unchanged as 0 (interrupt not requested).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 17.25 Pin Settings in UART Mode
17. Serial Interfaces (UART5 and UART6)
Bit Setting Port Function PD7, PD8, PD12, PD15 Registers - U56IS Register PSE1, PSE2 Registers PSD1, PSD2 Registers PSC, PSC2, PSC6 Registers PSL1, PSL2, PSL6, PSL9 Registers - - - PS1, PS2, PS6, PS9 Registers
(1)
P7_6 P7_7 P8_0 P8_1 P12_0 P12_1 P12_2 P12_3 P15_0 P15_1 P15_2 P15_3 P15_4 P15_5 P15_6 P15_7
TXD5 output(2) -
PSE1_6 = 1 PSD1_6 = 1 PSC_6 = 0 PSL1_6 = 0 PS1_6 = 1 - - - - - - - - - - - - - - - - - - - - - PS1_7 = 0 PS2_0 = 0 PS2_1 = 0
CLK5 input RXD5 input CTS5 input RTS5 output CLK6 input RXD6 input CTS6 input RTS6 output CLK5 RXD5 CTS5 input(3) input(3) input(3)
PD7_7 = 0 PD8_0 = 0 PD8_1 = 0 -
U5CLK = 0 - U5RXD = 0 - U5CTS = 0 - - - -
PSE2_1 = 0 PSD2_1 = 1 PSC2_1 = 1 PSL2_1 = 1 PS2_1 = 1 PSC6_0 = 1 PSL6_0 = 0 PS6_0 = 1 - - - - - - - - - - - - - - - - PS6_1 = 0 - PS6_3 = 0
TXD6 output(2) -
PD12_1 = 0 U6CLK = 1 - PD12_2 = 0 U6RXD = 1 - PD12_3 = 0 U6CTS = 1 - - - - - -
PSC6_3 = 1 PSL6_3 = 0 PS6_3 = 1 PSL9_0 = 1 PS9_0 = 1 - - - - - - - - PS9_1 = 0 - PS9_3 = 0 PS9_3 = 1 - PS9_6 = 0 PS9_7 = 0 PS9_7 = 1
TXD5 output(2) -
PD15_1 = 0 U5CLK = 1 - PD15_2 = 0 U5RXD = 1 - PD15_3 = 0 U5CTS = 1 - - - - - -
RTS5 output RXD6 CLK6 input(3) input(3)
TXD6 output(2) -
PSL9_4 = 1 PS9_4 = 1
PD15_5 = 0 U6RXD = 0 - PD15_6 = 0 U6CLK = 0 - - - -
CTS6 input(3) PD15_7 = 0 U6CTS = 0 - RTS6 output
NOTES: 1. Set registers PS1, PS2, PS6, and PS9 after setting the other registers. 2. After UARTi (i = 5, 6) operating mode is selected in the UiMR register and the pin function is set in the Function Select Registers, the TXDi pin outputs an "H" signal until a transmit operation starts. 3. Set both the IPSB_k bit in the IPSB register and the IPS2 bit in the IPS register to 0, when the port P15_k (k = 0 to 7) is used for a peripheral function input.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
Start initial setting
I flag = 0 IIOkIE register: UiTE bit = 0 UiRE bit = 0 U56IS register: UiCLK bit UiRXD bit UiCTS bit UiMR register: bits SMD2 to SMD0 CKDIR bit STPS bit PRY bit PRYE bit UiC0 register: bits CLK1 to CLK0 CRS bit CRD bit bit 5 = 0 CKPOL bit = 0 UFORM bit UiBRG register = m U56CON register: UiIRS bit UiRRM bit = 0 bits 6 to 4 = 000b IIOkIR register = 00h (4) IIOkIE register: IRLT bit = 1 IIOkIE register: UiTE bit = 1 UiRE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in the Function Select Regsiters I flag = 1 UiC1 register: TE bit = 1 RE bit = 1
Interrupt disabled UARTi transmit interrupt disabled UARTi receive interrupt disabled CLKi input pin select bit RXDi input pin select bit CTSi input pin select bit UART mode(1) select bits Clock select bit Stop bit length select bit Parity select bit Parity enable bit UiBRG register count source select bits CTS function select bit CTS function disable bit Bit order select bit(2) m = 00h to FFh Baud rate = fj 16(m+1) fj = f1, f8, f2n (3), fEXT
UARTi transmit interrupt request source select bit
UARTi transmit/receive interrupt not requested Uses an interrupt request for interrupt UARTi transmit interrupt enabled UARTi receive interrupt enabled Interrupt priority level select bits Interrupt not requested
Do not set these bits simultaneously. Enable the interrupts after setting the IRLT bit to 1.
Interrupt enabled Transmit operation enabled Receive operation enabled
End initial setting
Transmit operation starts by writing data to the UiTB register Receive operation starts when the start bit is detected. Read the UiRB register when the receive operation is completed. k = 0, 1 when i = 5, k = 9, 10 when i = 6 fEXT: clock input to the CLKi pin when the external clock is selected NOTES: 1. Set bits SMD2 to SMD0 to the following: 100b (7 bits long), 101b (8 bits long), 110b (9 bits long). 2. A bit order can be selected when 8-bit data length is selected. Set to 0 when 7-bit or 9-bit data length is selected. 3. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15). 4. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated. (An interrupt does not be occur.)
Figure 17.51
Register Settings in UART Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
(1) Example of the transmit operation timing in 8-bit data length (parity enabled, 1 stop bit)
TC Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register CTSi input 1 0 1 0 "H" "L" "H" "L" 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit) - UiC0 register: CRD bit = 0 and CRS bit = 0 (CTS function used) - U56CON register: UiIRS bit = 1 (transmit interrupt is generated when the transmit operation is completed) Start bit Write data to UiTB register
Transfer data from UiTB register to UARTi transmit shift register
Stop bit Parity bit
Transmission stops because TE = 0
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP ST D0
TXDi output TXEPT bit in the UiC0 register UiTR bit in the IIOjIR register
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
(2) Example of the transmit operation timing in 9-bit data length (parity disabled, 2 stop bit)
TC Internal transmit clock TE bit in the UiC1 register TI bit in the UiC1 register TXDi output TXEPT bit in the UiC0 register UiTR bit in the IIOjIR register 1 0 1 0 "H" "L" 1 0 1 0 Set to 0 by an interrupt request acknowledgement or by a program The above applies under the following conditions: - UiMR register: PRYE bit = 0 (parity disabled), STPS bit = 1 (2 stop bits) - UiC0 register: CRD bit = 1 (CTS function disabled) - U56CON register: UiIRS bit = 0 (transmit interrupt is generated when no data in the UiTB register) TC = 16(m + 1) fj fj: f1, f8, f2n (1), fEXT fEXT: clock input to the CLKi pin when the external clock is selected m: setting value of the UiBRG register (00h to FFh) Start bit Write data to UiTB register Transfer data from UiTB register to UARTi transmit shift register
Stop bits
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
j = 1 when i = 5, j = 10 when i = 6 NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Figure 17.52
Transmit Operation in UART mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
Example of the receive operation timing (1 stop bit)
(note 1)
RXDi input
"H" "L"
Start bit Verify the level (note 2)
D0 Input the receive data
Stop bit
Clock divided by UiBRG register Internal receive clock
Set to 0 by an interrupt request acknowledgement or by a program
UiRR bit in the IIOjIR register
1 0
RI bit in the UiC1 register
1 0 "H" "L" The output signal becomes "L" when the RE bit in the UiC1 register is set to 1 The output signal becomes "H" when the receive operation starts
This bit becomes 1 when the data is transferred from UARTi receive shift register to UiRB register
RTSi output
The RI bit becomes 0 and RTSi output becomes "L" by reading the UiRB register
j = 0 when i = 5, j = 9 when i = 6 The above applies under the following conditions: - UiMR register: STPS bit = 0 (1 stop bit) - UiC0 register: CRS bit = 1 (CTS function not used) NOTES: 1. RXDi input is sampled using the clock divided by the setting value of the UiBRG register. The internal receive clock is generated after detecting the falling edge of the start bit, and then the receive operation starts. 2. When "L" is detected, the receive operation continues. When "H" is detected, the receive operation is cancelled. When the receive operatin is cancelled, the RTSi output becomes "L".
Figure 17.53
Receive Operation in UART Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.2.1 Baud Rate
In UART mode, the baud rate is the clock frequency divided by the setting value of the UiBRG register (i = 5 and 6) and again divided by 16. Table 17.26 lists an example of baud rate setting. Actual baud rate = UiBRG register count source 16 x (UiBRG register setting value + 1)
Table 17.26
Target Baud Rate (bps) 1200 2400 4800 9600 14400 19200 28800 31250 38400 51200
Baud Rate
UiBRG Count Source f8 f8 f8 f1 f1 f1 f1 f1 f1 f1 Peripheral Clock: 16MHz UiBRG Setting Value: n 103(67h) 51(33h) 25(19h) 103(67h) 68(44h) 51(33h) 34(22h) 31(1Fh) 25(19h) 19(13h) Actual Baud Rate (bps) 1202 2404 4808 9615 14493 19231 28571 31250 38462 50000 Peripheral Clock: 24MHz UiBRG Setting Value: n 155(9Bh) 77(4Dh) 38(26h) 155(9Bh) 103(67h) 77(4Dh) 51(33h) 47(2Fh) 38(26h) 28(1Ch) Actual Baud Rate (bps) 1202 2404 4808 9615 14423 19231 28846 31250 38462 51724 Peripheral Clock: 32MHz UiBRG Setting Value: n 207(CFh) 103(67h) 51(33h) 207(CFh) 138(8Ah) 103(67h) 68(44h) 63(3Fh) 51(33h) 38(26h) Actual Baud Rate (bps) 1202 2404 4808 9615 14388 19231 28986 31250 38462 51282
17.2.2.2 LSB First or MSB First
As shown in Figure 17.54, the UFORM bit in the UiC0 register (i = 5 and 6) determines a bit order. This function is can be used when data length is 8 bits long.
(1) When the UFORM bit in the UiC0 register (i = 5, 6) is set to 0 (LSB first)
TXDi "H" "L" "H" "L" ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
(2) When the UFORM bit is set to 1 (MSB first)
TXDi "H" "L" "H" "L" ST D7 D6 D5 D4 D3 D2 D1 D0 P SP
RXDi
ST
D7
D6
D5
D4
D3
D2
D1
D0
P
SP
The above applies under the following conditions: - UiC0 register: CKPOL bit = 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock) ST: Start bit P: Parity bit SP: Stop bit
Figure 17.54
Bit Order
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
17. Serial Interfaces (UART5 and UART6)
17.2.2.3 CTS/RTS Function
* CTS Function
Transmit operation is controlled by using the input signal to the CTSi pin (i = 5 and 6). To use the CTS function, select the I/O port in the Function Select Register, set the CRD bit in the UiC0 register to 0 (CTS function enabled), and the CRS bit to 0 (CTS function selected). With the CTS function used, the transmit operation starts when all the following conditions are met and an "L" signal is applied to the CTSi pin. -The TE bit in the UiC1 register is set to 1 (transmit operation enabled) -The TI bit in the UiC1 register is 0 (data in the UiTB register) When a high-level ("H") signal is applied to the CTSi pin during transmitting, the transmit operation is disabled after the transmit operation in progress is completed.
* RTS Function
The MCU can inform the external device that it is ready for a receive operation by using the output signal from the RTSi pin. To use the RTS function, select the RTSi pin in the Function Select Register. With the RTS function used, the RTSi pin outputs an "L" signal when all the following conditions are met, and outputs an "H" when the start bit is detected. -The RI bit in the UiC1 register is 0 (no data in the UiRB register) -The RE bit is set to 1 (receive operation enabled)
17.2.2.4 Procedure When the Communication Error is Occurred
Follow the procedure below when a communication error is occurred in UART mode. (1) Set the TE bit in the UiC1 register (i = 5 and 6) to 0 (transmit operation disabled) and the RE bit to 0 (receive operation disabled). (2) Set bits SMD2 to SMD0 in the UiMR register to 000b (serial interface disabled). (3) Set bits SMD2 to SMD0 in the UiMR register to 100b (UART mode, 7-bit data length), 101b (UART mode, 8-bit data length), or 110b (UART mode, 9-bit data length). (4) Set the TE bit to 1 (transmit operation enabled) and the RE bit to 1 (receive operation enabled).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18. A/D Converter
NOTE The 144-pin package is described as an example in this chapter. Pins AN15_0 to AN15_7 are not provided in the 100-pin package.
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has one 10-bit successive approximation A/D converter with a capacitance coupled amplifier. The results of A/D conversion are stored into the AD0i registers (i = 0 to 7) corresponding to the selected pins. When using DMAC operating mode, the conversion results are stored only into the AD00 register. Table 18.1 lists specifications of the A/D converter. Figure 18.1 shows a block diagram of the A/D converter. Figures 18.2 to 18.6 show registers associated with the A/D converter. Table 18.1 A/D Converter Specifications
Item A/D conversion method Analog input voltage Operating clock Resolution Operating modes AD(1) 0 V to AVCC (VCC1) fAD, fAD/2, fAD/3, fAD/4, fAD/6, fAD/8 Selectable from 8 bits or 10 bits * One-shot mode * Repeat mode * Single sweep mode * Repeat sweep mode 0 * Repeat sweep mode 1 * Multi-port single sweep mode * Multi-port repeat sweep mode 0 144 pin package: 34 pins 8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7), AN2 (AN2_0 to AN2_7), and AN15 (AN15_0 to AN15_7) 2 extended input pins (ANEX0 and ANEX1) 100 pin package: 26 pins 8 pins each for AN (AN_0 to AN_7), AN0 (AN0_0 to AN0_7), AN2 (AN2_0 to AN2_7) 2 extended input pins (ANEX0 and ANEX1) * Software trigger The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts). * External trigger (retrigger is enabled) When the falling edge is detected at the ADTRG pin after the ADST bit is set to 1. * Hardware trigger (retrigger is enabled) Timer B2 interrupt request of the three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Specification Successive approximation (with capacitance coupled amplifier)
Analog input pins(2)
A/D conversion start condition
Conversion rate per pin
NOTES: 1. The AD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5 V. The AD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5 V. Without the sample and hold function, the AD frequency must be 250 kHz or higher. With the sample and hold function, the AD frequency must be 1 MHz or higher. 2. AVCC = VCC1 VCC2 AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) VCC1, AD input (AN0_0 to AN0_7, AN2_0 to AN2_7) VCC2
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
Software trigger
0 1
TRG bit in AD0CON0 register Start trigger ADST bit
000 001 010 011 100 101 110 111 000 001
AN2_0 AN2_1 AN2_2 AN2_3 AN2_4 AN2_5 AN2_6 AN2_7 AN0_0 AN0_1 AN0_2 AN0_3 AN0_4 AN0_5 AN0_6 AN0_7 AN15_0 AN15_1 AN15_2 AN15_3 AN15_4 AN15_5 AN15_6 AN15_7 P15(2, 3) P0(1, 3) P2(1, 3)
ADTRG
0
Timer B2 interrupt request 1 (after ICTB2 register completes TRG0 bit in counting) of the three-phase control timer function AD0CON2 register
Bits OPA1 and OPA0 in AD0CON1 register
P9_6 P9_5 ANEX1 ANEX0
1X X1 11 01
010 011 100 101 110 111
AN_0 AN_1 AN_2 P10(3) AN_3 AN_4 AN_5 AN_6 AN_7
000 000 001 010 011 100 101 110 111 00 11 00 01 10 001 010 011 100 101 110 111
Bits APS1 and APS0 in AD0CON2 register
Bits CH2 to CH0 in AD0CON0 register
Bits CH2 to CH0 in AD0CON0 register AD00 register AD01 register AD02 register
AD0CON0 register
AD0CON1 register
AD03 register AD04 register
Decoder
Comparator
AD0CON2 register
AD05 register AD06 register AD07 register
AD0CON3 register
Successive conversion register
AD0CON4 register Resistor ladder CKS0 bit in AD0CON0 register
1
1/3 1/2 fAD
1 0
0 1
1 0
AD
1/2
1/2
0
CKS2 bit in AD0CON3 register NOTES: 1. These pins can be used in single-chip mode only. 2. These pins are provided in the 144-pin package only. 3. AVCC = VCC1 VCC2, AD input (AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, ANEX1) VCC1, (AN0_0 to AN0_7, AN2_0 to AN2_7) VCC2
CKS1 bit in AD0CON1 register
Figure 18.1
A/D Converter Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
A/D0 Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AD0CON0
Bit Symbol CH0 Analog input pin select bits(2, 3) Bit Name
Address 0396h
Function
b2 b1 b0
After Reset 00h
RW RW
CH1
CH2
0 0 0: ANi_0 0 0 1: ANi_1 0 1 0: ANi_2 0 1 1: ANi_3 1 0 0: ANi_4 1 0 1: ANi_5 1 1 0: ANi_6 1 1 1: ANi_7 (i = none, 0, 2, 15) When the MSS bit in the AD0CON3 register = 0
b4 b3
RW
RW
MD0
A/D operating mode select bits 0 (2)
0 0: One-shot mode 0 1: Repeat mode 1 0: Single sweep mode 1 1: Repeat sweep mode 0, repeat sweep mode 1 When the MSS bit in the AD0CON3 register = 1
b4 b3
RW
MD1
0 0: Do not set to these values. 0 1: 1 0: Multi-port single sweep mode 1 1: Multi-port repeat sweep mode 0 Trigger select bit 0: Software trigger 1: External trigger, hardware trigger (4) 0: A/D conversion stops 1: A/D conversion starts (4) (Note 5)
RW
TRG
RW
ADST
A/D conversion start bit
RW
CKS0
Frequency select bit 0
RW
NOTES: 1. If the AD0CON0 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. Analog input pins must be configured again after an A/D operating mode is changed. 3. Bits CH2 to CH0 are enabled in one-shot mode and repeat mode. 4. To set the TRG bit to 1, select a trigger source using the TRG0 bit in the AD0CON2 register. Then, set the ADST bit to 1 after the TRG bit is set to 1. 5. AD frequency must be 16 MHz or lower when VCC1 = 4.2 to 5.5V. AD frequency must be 10 MHz or lower when VCC1 = 3.0 to 5.5V. AD is selected by the combination of the CKS0 bit, the CKS1 in the AD0CON1 register, and the CKS2 bit in the AD0CON3 register. CKS2 bit in AD0CON3 register CKS0 bit in AD0CON0 register 0 0 1 CKS1 bit in AD0CON1 register 0 1 0 1 0 1
AD
fAD divided by 4 fAD divided by 3 fAD divided by 2 fAD fAD divided by 8 fAD divided by 6
1
0
Figure 18.2
AD0CON0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
A/D0 Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AD0CON1
Bit Symbol Bit Name
Address 0397h
Function
After Reset 00h
RW
Single sweep mode and repeat sweep mode 0 SCAN0 0 0: ANi_0, ANi_1 (i = none, 0, 2, 15) 0 1: ANi_0 to ANi_3 1 0: ANi_0 to ANi_5 1 1: ANi_0 to ANi_7 Repeat sweep mode 1 (3) 0 0: ANi_0 0 1: ANi_0, ANi_1 1 0: ANi_0 to ANi_2 1 1: ANi_0 to ANi_3 Multi-port single sweep mode and multi-port repeat sweep mode 0(4) Set to 11b. 0: Other than repeat sweep mode 1 1: Repeat sweep mode 1 0: 8-bit mode 1: 10-bit mode (Note 5) 0: VREF not connected (7) 1: VREF connected
b7 b6 b1 b0 b1 b0
RW
A/D sweep pin select bits (2)
SCAN1
RW
MD2
A/D operating mode select bit 1(4) Resolution select bit
RW
BITS
RW
CKS1
Frequency select bit 1
RW
VCUT
VREF connection bit (8)
RW
OPA0 Extended input pin function select bits(4, 6) OPA1
0 0: ANEX0 and ANEX1 are not used 0 1: Signal applied to ANEX0 is A/D converted 1 0: Signal applied to ANEX1 is A/D converted 1 1: External op-amp connection
RW
RW
NOTES: 1. If the AD0CON1 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. Bits SCAN1 and SCAN0 are enabled in single sweep mode, repeat sweep mode 0, 1, multi-port single sweep mode, and multiport repeat sweep mode 0. 3. These are prioritized pins used for A/D conversion when the MD2 bit is set to 1. 4. When the MSS bit in the AD0CON3 register is set to 1 (multi-port sweep mode used); -set bits SCAN1 and SCAN0 to 11b -set the MD2 bit to 0 -set bits OPA1 and OPA0 to 00b. 5. Refer to the note for the CKS0 bit in the AD0CON0 register. 6. Bits OPA1 and OPA0 can be set to 01b or 10b in one-shot mode and repeat mode. Set these bits to 00b or 11b in other modes. 7. Do not set the VCUT bit to 0 during A/D conversion. Even if the VCUT bit is set to 0, VREF remains connected to the D/A converter. 8. When the VCUT bit is set to 1 from 0, wait for 1 s or more to start the A/D conversion.
Figure 18.3
AD0CON1 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
A/D0 Control Register 2(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol AD0CON2
Bit Symbol SMP Bit Name A/D conversion method select bit
Address 0394h
Function 0: Without sample and hold 1: With sample and hold
After Reset XX0X X000b
RW RW
When the MSS bit in the AD0CON3 register = 0 APS0 Analog input port select bits(3) APS1
b2 b1
0 0: AN_0 to AN_7, ANEX0, ANEX1 0 1: AN15_0 to AN15_7(2) 1 0: AN0_0 to AN0_7 1 1: AN2_0 to AN2_7 When the MSS bit in the AD0CON3 register = 1 Set to 01b.
RW
RW
- (b4-b3)
Unimplemented. Write 0. Read as undefined value. 0: ADTRG selected 1: Timer B2 interrupt request of the three-phase motor control timer function (after the ICTB2 register completes counting) selected Set to 0. Read as undefined value.
-
TRG0
External trigger source select bit
RW
- (b7-b6)
Reserved bits
RW
NOTES: 1. If the AD0CON2 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. In the 100-pin package, do not set to 01b. 3. Set to 00b or 01b in memory expansion mode and microprocessor mode.
Figure 18.4
AD0CON2 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
A/D0 Control Register 3(1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol AD0CON3
Bit Symbol DUS Bit Name DMAC operating mode select bit Multi-port sweep mode select bit Frequency select bit 2
Address 0395h
Function 0: DMAC operating mode not used 1: DMAC operating mode used 0: Multi-port sweep mode not used 1: Multi-port sweep mode used (3) (Note 4)
After Reset XXXX X000b
RW RW
MSS
RW
CKS2
RW
MSF0 Multi-port sweep status flags MSF1
(5)
b4 b3
0 0: AN_0 to AN_7 0 1: AN15_0 to AN15_7 1 0: AN0_0 to AN0_7 1 1: AN2_0 to AN2_7 Set to 0. Read as undefined value.
RO
RO
- (b7-b5)
Reserved bits
RW
NOTES: 1. If the AD0CON3 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. The AD0CON3 register may return an incorrect value if read during A/D conversion. It must be read or written after the A/D conversion stops. 3. When the MSS bit is set to 1; -set the DUS bit to 1 and configure DMAC. -set bits MD1 and MD0 in the AD0CON0 register to 10b or 11b. -set bits SCAN1 and SCAN0 in the AD0CON1 register to 11b, the MD2 bit to 0, bits OPA1 and OPA0 to 00b. -set bits APS1 and APS0 in the AD0CON2 register to 01b. -set bits MPS11 and MPS10 to 01b, 10b, or 11b. 4. Refer to the note for the CKS0 bit in the AD0CON0 register. 5. Bits MSF1 and MSF0 are enabled when the MSS bit is set to 1. When the MSS bit is set to 0, a read from these bits returns an undefined value.
Figure 18.5
AD0CON3 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
A/D0 Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
00
Symbol AD0CON4
Bit Symbol - (b1-b0) MPS10 Multi-port sweep port select bits(2, 3) MPS11 - (b7-b4) Bit Name Reserved bits
Address 0392h
Function Set to 0. Read as undefined value.
b3 b2
After Reset XXXX 00XXb
RW RW
0 0: (Note 4) 0 1: AN_0 to AN_7, AN15_0 to AN15_7 1 0: AN_0 to AN_7, AN0_0 to AN0_7 1 1: AN_0 to AN_7, AN2_0 to AN2_7 Set to 0. Read as undefined value.
RW
RW
Reserved bits
RW
NOTES: 1. If the AD0CON4 register is rewritten during A/D conversion, the conversion result will be incorrect. 2. Do not set bits MPS11 and MPS10 to 01b in the 100-pin package. 3. Bits MPS11 and MPS10 cannot be set to 10b or 11b in memory expansion mode or microprocessor mode. 4. When the MSS bit in the AD0CON3 register is set to 0 (multi-port sweep mode not used), set bits MPS11 and MPS10 to 00b. When the MSS bit is set to 1 (multi-port sweep mode used), set bits MPS11 and MPS10 to other than 00b.
A/D0 Register i(1, 2, 3, 4) (i = 0 to 7)
b15 b8 b7 b0
0 00 0 0 0
Symbol AD00 AD01 to AD03 AD04 to AD06 AD07
Address 0381h - 0380h 0383h - 0382h, 0385h - 0384h, 0387h - 0386h 0389h - 0388h, 038Bh - 038Ah, 038Dh - 038Ch 038Fh - 038Eh
Function
After Reset 00000000 00000000 00000000 00000000 XXXXXXXXb XXXXXXXXb XXXXXXXXb XXXXXXXXb
RW RO
8 low-order bits of A/D conversion result In 10-bit mode: 2 high-order bits of A/D conversion result In 8-bit mode: Read as 0. Reserved bits. Read as 0.
RO
RO
NOTES: 1. When the AD0i register is read by a program in DMAC operating mode, the conversion result is incorrect. 2. If the next A/D conversion result is stored before reading the previous result in the AD0i register, the result will be incorrect. 3. Only AD00 register is enabled in DMAC operating mode. The contents of other registers are undefined. 4. When using both DMAC operating mode and 10-bit mode, select a 16-bit transfer for DMAC.
Figure 18.6
AD0CON4 Register, AD00 to AD07 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
If analog input shares the pin with other peripheral function inputs, a through current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin. To prevent through current, set the control bit for the corresponding pin to 1, and other peripheral inputs are disconnected. Table 18.2 lists settings of an analog input pin. Table 18.2
Port P9_5 P9_6 P10_4 P10_5 P10_6 P10_7 P15_0 P15_1 P15_2 P15_3 P15_4 P15_5 P15_6 P15_7
Analog Input Pin Setting
Function ANEX0 ANEX1 AN_4 AN_5 AN_6 AN_7 AN15_0 AN15_1 AN15_2 AN15_3 AN15_4 AN15_5 AN15_6 AN15_7 - - - - - - IPSB_0 = 1 IPSB_1 = 1 IPSB_2 = 1 IPSB_3 = 1 IPSB_4 = 1 IPSB_5 = 1 IPSB_6 = 1 IPSB_7 = 1 IPS2 = 1(1) Control Bit IPSB Register - - - - - - - - - - - - - - PSC_7 = 1 IPS Register - - PSC Register PSL3 Register PSL3_5 = 1 PSL3_6 = 1 - - - - - - - - - - - -
NOTE: 1. When the IPSB_i bit (i = 0 to 7) is set to 1, the peripheral function inputs which are assigned to the P15_i pin are disconnected. When the IPS2 bit is set to 1, the peripheral function inputs which are assigned to pins P15_0 to P15_7 are all disconnected.
18.1
Mode Descriptions
The A/D converter has seven different modes. Table 18.3 lists settings for these modes. Table 18.3 Mode Settings
Mode One-shot mode Repeat mode Single sweep mode Repeat sweep mode 0 Repeat sweep mode 1 Multi-port single sweep mode Multi-port repeat sweep mode 0 AD0CON0 register MD1 bit 0 0 1 1 1 1 1 MD0 bit 0 1 0 1 1 0 1 AD0CON1 register MD2 bit 0 0 0 0 1 0 0 AD0CON3 register MSS bit 0 0 0 0 0 1 1 DUS bit 0 or 1 0 or 1 0 or 1 0 or 1 0 or 1 1 1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.1
One-Shot Mode
In one-shot mode, analog voltage applied to a selected pin is converted to a digital code once. Table 18.4 lists specifications of one-shot mode. Table 18.4
Function Analog input pins
One-Shot Mode Specifications
Item Specification Analog voltage applied to a selected pin is converted once Select one pin from AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, or ANEX1 The following register settings determine which pin is used: * Bits CH2 to CH0 in the AD0CON0 register * Bits OPA1 and OPA0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * The ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * A/D conversion is completed (the ADST bit becomes 0 when software trigger is selected). * Set the ADST bit to 0 by a program (A/D conversion stops). * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
Start Condition
Stop condition
Interrupt request generation timing When the A/D conversion is completed Reading A/D conversion result
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.2
Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 18.5 lists specifications of repeat mode. Table 18.5
Function Analog input pins
Repeat Mode Specifications
Item Specification Analog voltage applied to a selected pin is repeatedly converted Select one pin from AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, or ANEX1 The following register settings determine which pin is used: * Bits CH2 to CH0 in the AD0CON0 register * Bits OPA1 and OPA0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is not generated. * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed. Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.3
Single Sweep Mode
In single sweep mode, analog voltage that is applied to multiple selected pins is converted to a digital code once for each pin. Table 18.6 lists specifications of single sweep mode. Table 18.6
Function Analog input pins
Single Sweep Mode Specifications
Item Specification Analog voltage applied to selected pins is converted once for each pin Select one of the following. * 2 pins (ANi_0 and ANi_1) (i = none, 0, 2, 15) * 4 pins (ANi_0 to ANi_3) * 6 pins (ANi_0 to ANi_5) * 8 pins (ANi_0 to ANi_7) The following register settings determine which pins are used: * Bits SCAN1 and SCAN0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * A sequence of A/D conversions is completed (the ADST bit becomes 0 when software trigger is selected) * Set the ADST bit to 0 by a program (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is generated after a sequence of A/D conversions is completed. * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.4
Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to multiple selected pins is repeatedly converted to a digital code. Table 18.7 lists specifications of repeat sweep mode 0. Table 18.7
Function Analog input pins
Repeat Sweep Mode 0 Specifications
Item Specification Analog voltage applied to selected pins is repeatedly converted Select one of the following. 2 pins (ANi_0 and ANi_1) (i = none, 0, 2, 15) 4 pins (ANi_0 to ANi_3) 6 pins (ANi_0 to ANi_5) 8 pins (ANi_0 to ANi_7) The following register settings determine which pins are used: * Bits SCAN1 and SCAN0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is not generated * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.5
Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage applied to eight pins, prioritizing one to four pins, is repeatedly converted to a digital code. Table 18.8 lists specifications of repeat sweep mode 1. Table 18.8
Function Analog input pins Prioritized pins
Repeat Sweep Mode 1 Specification
Item Specification Analog voltage applied to 8 selected pins, prioritizing one to four pins, is repeatedly converted. ANi_0 to ANi_7 (8 pins are selected from these pins) (i = none, 0, 2, 15) Select one of the following. * single pin (ANi_0) * 2 pins (ANi_0 and ANi_1) * 3 pins (ANi_0 to ANi_2) * 4 pins (ANi_0 to ANi_3) The following register settings determine which pins are used: * Bits SCAN1 and SCAN0 in the AD0CON1 register * Bits APS1 and APS0 in the AD0CON2 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. (retrigger of external trigger is invalid) Set the ADST bit is set to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing * DMAC operating mode is not used (DUS bit in the AD0CON3 register = 0): Interrupt request is not generated. * DMAC operating mode is used (DUS bit = 1): Interrupt request is generated every time each A/D conversion is completed. Reading A/D conversion result * DMAC operating mode is not used (DUS bit = 0): Read the AD0j register (j = 0 to 7) corresponding to a selected pin by a program. * DMAC operating mode is used (DUS bit = 1): A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. (Refer to 13. DMAC for DMAC settings)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
When ANi_0 is prioritized (single pin) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 and ANi_1 are prioritized (2 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 to ANi_2 are prioritized (3 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 to ANi_3 are prioritized (4 pins) ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 : A/D conversion i = none, 0, 2, 15
Time
Figure 18.7
Transition Diagram of Pins used in A/D Conversion in Repeat Sweep Mode 1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.6
Multi-Port Single Sweep Mode
In multi-port single sweep mode, analog voltage applied to 16 selected pins is converted to a digital code once for each pin. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode used). Table 18.9 lists specifications of multi-port single sweep mode. Table 18.9
Function Analog input pins
Multi-Port Single Sweep Mode Specifications
Item Specification Analog voltage applied to the 16 selected pins is repeatedly converted once for each pin in the following order: AN_0 to AN_7 ANi_0 to ANi_7 (i = 0, 2, 15) Select one of the following. * AN_0 AN_1 . . . AN_7 AN0_0 AN0_1 . . . AN0_7 * AN_0 AN_1 . . . AN_7 AN2_0 AN2_1 . . . AN2_7 * AN_0 AN_1 . . . AN_7 AN15_0 AN15_1 . . . AN15_7 The following register settings determine which pins are used: Bits MPS11 and MPS10 in the AD0CON4 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. * A sequence of A/D conversions is completed (the ADST bit becomes 0 when software trigger is selected) * Set the ADST bit to 0 by a program (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed (Set the DUS bit in the AD0CON3 register to 1) Reading A/D conversion result A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. Refer to 13. DMAC for DMAC settings. (Set the DUS bit in the AD0CON3 register to 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.1.7
Multi-Port Repeat Sweep Mode 0
In multi-port repeat sweep mode 0, analog voltage that is applied to 16 selected pins is repeatedly converted to a digital code. Set the DUS bit in the AD0CON3 register to 1 (DMAC operating mode used). Table 18.10 lists specifications of multi-port repeat sweep mode 0. Table 18.10
Function Analog input pins
Multi-Port Repeat Sweep Mode 0 Specifications
Item Specification Analog voltage applied to the 16 selected pins is repeatedly converted in the following order: AN_0 to AN_7 ANi_0 to ANi_7 (i = 0, 2, 15) Select one of the following. * AN_0 AN_1 . . . AN_7 AN0_0 AN0_1 . . . AN0_7 * AN_0 AN_1 . . . AN_7 AN2_0 AN2_1 . . . AN2_7 * AN_0 AN_1 . . . AN_7 AN15_0 AN15_1 . . . AN15_7 The following register settings determine which pins are used: Bits MPS11 and MPS10 in the AD0CON4 register Software trigger is selected (TRG bit in the AD0CON0 register = 0): * the ADST bit in the AD0CON0 register is set to 1 (A/D conversion starts) External trigger, hardware trigger is selected (TRG bit = 1): * TRG0 bit in the AD0CON2 register = 0 The falling edge is detected on the ADTRG pin after the ADST bit is set to 1 * TRG0 bit = 1 Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting) is generated after the ADST bit is set to 1. Set the ADST bit is set to 0 (A/D conversion stops)
Start condition
Stop condition
Interrupt request generation timing An interrupt request is generated every time each A/D conversion is completed (Set the DUS bit in the AD0CON3 register to 1) Reading A/D conversion result A/D conversion result is stored into the AD00 register after A/D conversion is completed. Then, DMAC transfers the data from the AD00 register to a given memory space. Refer to 13. DMAC for DMAC settings (Set the DUS bit in the AD0CON3 register to 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.2 18.2.1
Functions Resolution
The BITS bit in the AD0CON1 register determines the resolution. When the BITS bit is set to 1 (10-bit mode), the A/D conversion result is stored into bits 9 to 0 in the AD0i register (i = 0 to 7). When the BITS bit is set to 0 (8-bit mode), the A/D conversion result is stored into bits 7 to 0 in the AD0i register.
18.2.2
Sample and Hold
When the SMP bit in the AD0CON2 register is set to 1 (with sample and hold), the A/D conversion rate per pin increases to 28 AD cycles for 8-bit resolution and 33 AD cycles for 10-bit resolution. The sample and hold function is available in all operating modes. Start A/D conversion after selecting whether the sample and hold circuit is used or not.
18.2.3
Trigger Select Function
The TRG bit in the AD0CON0 register and the TRG0 bit in the AD0CON2 register determine a trigger to start A/D conversion. Table 18.11 lists setting values for the trigger select function. Table 18.11 Trigger Select Function Setting Values
Bit and Setting AD0CON0 Register TRG = 0 AD0CON2 Register - Trigger Software trigger A/D conversion starts when the ADST bit in the AD0CON0 register is set to 1 by a program External trigger(2) Falling edge of a signal applied to ADTRG Hardware trigger(2) Timer B2 interrupt request of three-phase motor control timer function (after the ICTB2 register completes counting)
TRG = 1(1)
TRG0 = 0 TRG0 = 1
NOTES: 1. A/D conversion starts when the ADST bit is set to 1 (A/D conversion starts) and a trigger is generated. 2. A/D conversion starts over from the beginning, if an external trigger or a hardware trigger is inserted during A/D conversion. (A/D conversion in progress is aborted.)
18.2.4
DMAC Operating Mode
DMAC operating mode is available in all operating modes. To select multi-port single sweep mode or multiport repeat sweep mode 0, DMAC operating mode must be used. When the DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode used), all A/D conversion results are stored into the AD00 register. DMAC transfers the result from the AD00 register to a given memory space every time A/D conversion on a single pin is completed. 8-bit DMA transfer must be selected for 8-bit resolution and 16-bit DMA transfer for 10-bit resolution. Refer to 13. DMAC for DMAC instructions. When using DMAC operating mode in single sweep mode, repeat sweep mode 0, repeat sweep mode 1, multiport single sweep mode, or multi-port repeat sweep mode 0, do not generate an external retrigger or hardware retrigger.
18.2.5
Extended Analog Input Pins
In one-shot mode and repeat mode, the ANEX0 pin or ANEX1 pin can be used as the analog input pin. These pins can be selected using bits OPA1 and OPA0 in the AD0CON1 register. The A/D conversion result for ANEX0 input is stored into the AD00 register, and for ANEX1 input into the AD01 register. Both results are stored into the AD00 register when the DUS bit in the AD0CON3 register is set to 1 (DMAC operating mode used). Set bits APS1 and APS0 in the AD0CON2 register to 00b (AN_0 to AN_7, ANEX0, ANEX1) and the MSS bit in the AD0CON3 register to 0 (multi-port sweep mode not used).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.2.6
External Operating Amplifier (Op-Amp) Connection Mode
In external op-amp connection mode, multiple analog voltage can be amplified by one external op-amp using extended analog input pins, ANEX0 and ANEX1. When bits OPA1 and OPA0 are set to 11b (external op-amp connection), voltage applied to pins AN_0 to AN_7 are output from the ANEX0. Amplify this output signal by external op-amp and apply it to the ANEX1. Analog voltage applied to ANEX1 is converted to a digital code and the A/D conversion result is stored into the corresponding AD0i register (i = 0 to 7). The A/D conversion rate varies depending on the response characteristics of the external op-amp. The ANEX0 pin cannot be connected to the ANEX1 pin directly. Set bits APS1 and APS0 in the AD0CON2 register to 00b (AN_0 to AN_7, ANEX0, ANEX1). Figure 18.8 shows a connection example of external op-amp connection mode. Table 18.12
OPA1 Bit 0 0 1 1
Extended Analog Input Pin Settings
OPA0 Bit 0 1 0 1 Not used P9_5 as an analog input Not used Output to external op-amp ANEX0 Function Not used Not used P9_6 as an analog input Input from external op-amp ANEX1 Function
AD0CON1 Register
AN_0 AN_1 AN_2 Analog input AN_3 AN_4 AN_5 AN_6 AN_7
Resistor ladder
Successive conversion register
ANEX0
00b Bits APS1 and APS0 in the AD0CON2 register
ANEX1 External op-amp
Comparator
Figure 18.8
Connection Example in External Op-Amp Connection Mode
18.2.7
Power Consumption Reduce Function
When not using the A/D converter, the VCUT bit in the AD0CON1 register can disconnect the resistor ladder of the A/D converter from the reference voltage input pin (VREF). As a result, power consumption can be reduced by shutting off any current flow into the resistor ladder from the VREF pin. When using the A/D converter, set the VCUT bit to 1 (VREF connected) prior to setting the ADST bit in the AD0CON0 register to 1 (A/D conversion starts). Do not set the VCUT bit to 0 (VREF not connected) during A/D conversion. Even if the VCUT bit is set to 0, VREF remains connected to the D/A converter.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
18.3
Read from the AD0i Register (i = 0 to 7)
Use the following procedure to read the AD0i register by a program. * In one-shot mode and single sweep mode: Ensure that the A/D conversion is completed before reading the corresponding AD0i register. The IR bit in the AD0IC register becomes 1 when the A/D conversion is completed. * In repeat mode, repeat sweep mode 0, and repeat sweep mode 1: Read the AD0i register after setting the CPU clock as follows. (1) Set the PM24 bit in the PM2 register to 0 (clock selected by the CM07 bit). (2) Set the CM07 bit in the CM0 register to 0 (clock selected by the CM21 bit divided by the MCD register). (3) Set the MCD register to 12h (no division).
18.4
Output Impedance of Sensor Equivalent Circuit under A/D Conversion
To take full advantage of the A/D converter performance, Internal capacitor (C) charge shown in Figure 18.9 must be completed within the specified period (T) as sampling time. Output impedance of the sensor equivalent circuit (R0) is determined by the following equation:
- ---------------------------t C ( R0 + R ) VC = VIN 1 - e X 1 - X VC = VIN - --- VIN = VIN --- Y Y
1
When t = T, e
1 - --------------------------- T C ( R0 + R )
1 X - --------------------------- T = ln --C ( R0 + R ) Y T R0 = - ------------- - R X C ln --Y
X = --Y
where: VC = Internal capacitor voltage R = Internal resistance of the MCU X = Accuracy (error) of the A/D converter Y = Resolution (1024 in 10-bit mode, and 256 in 8-bit mode) Figure 18.9 shows a connection example of analog input pin and external sensor equivalent circuit. In the following example, the impedance R0 is obtained from the equation above when VC changes from 0 to VIN-(1/1024)VIN within the time (T), if the difference between VIN and VC becomes 1LSB. (1/1024) means that A/D accuracy drop, due to insufficient capacitor charge, is held to 1LSB at time of A/D conversion in the 10-bit mode. Actual error, however, is the value of absolute accuracy added to 1LSB. When AD = 10 MHz, T = 0.3 s in A/D conversion with the sample and hold function. Output impedance (R0) enough to complete charging the capacitor (C) within the time (T) is determined by the following equation:
Using T = 0.3 s, R = 2.0 k, C = 9.0 pF, X = 1, Y = 1024,
3 0.3 x 10 R0 = - ---------------------------------------------------- - 2.0 x 10 2.8 x 10 3 - 12 1 ln -----------9.0 x 10 1024
-6
Thus, the allowable output impedance R0 of the sensor equivalent circuit, making the accuracy (error) 1LSB or less, is approximately 2.8 k maximum.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
18. A/D Converter
Sensor equivalent Circuit R0 VIN
MCU
R (2.0 k) C (9.0 pF) VC Sampling time Sample and hold is enabled : Sample and hold is disabled :
3 AD 2 AD
Figure 18.9
Analog Input Pin and External Sensor Equivalent Circuit
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
19. D/A Converter
19. D/A Converter
The D/A converter consists of two independent 8-bit R-2R ladder D/A converter circuits. Digital code is converted to analog voltage every time a value to be converted is written to the corresponding DAi register (i = 0, 1), if bits DATi1 and DATi0 in the DACON1 register are set to 00b. Every time the selected timer underflows, a value in the DAi register is transferred to the DAi buffer and the D/A conversion is performed, if bits DATi1 and DATi0 are set to 01b, 10b, or 11b. The values in the DAi buffer is 00h after reset. The DAiE bit in the DACON register determines whether the D/A conversion result is output or not. When the DAiE bit is set to 1 (output enabled), the corresponding port cannot be pulled up. When the D/A converter is not used, set registers DAi and DACON1 to 00h and the DAiE bit to 0 (output disabled). Output analog voltage (V) is obtained from the following equation using the value n (n = decimal) set in the DAi register.
V=
VREF x n 256
(n = 0 to 255)
VREF: Reference voltage (VREF remains connected even if the VCUT bit in the AD0CON1 register is set to 0) Table 19.1 lists specifications of the D/A converter. Figure 19.1 shows a block diagram of the D/A converter. Table 19.2 lists pin settings of DA0 and DA1. Figure 19.2 shows registers associated with the D/A converter. Figure 19.3 shows a D/A converter equivalent circuit. Table 19.1 D/A Converter Specifications
Item D/A conversion method Resolution Analog output pin R-2R 8 bits 2 channels Specification
Low-order bits of data bus DAi1 to DAi0 DAi register DAi buffer(1) Read 00 DAi1 to DAi0 01 10 11 00 01 10 11 TA3 underflow TA4 underflow TB0 underflow
DAiE
i = 0, 1 DAiE: bit in the DACON register DAi1, DAi0: bits in the DACON1 register NOTE: 1. When bits DATi1 and DATi0 are set to 01b, 10b or 11b, a value in the DAi register is transferred to the DAi buffer every time the selected timer underflows. The value in the DAi buffer is 00h after reset.
R-2R Resistor Ladder
DAi
Figure 19.1 Table 19.2
Port P9_3 P9_4
D/A Converter Block Diagram Pin Settings
Function DA0 output DA1 output Bit Setting PD9 Register(2) PD9_3=0 PD9_4=0 PSL3 Register PSL3_3=1 PSL3_4=1 PS3 Register(1)(2) PS3_3=0 PS3_4=0
NOTES: 1. Set the PS3 register after setting the other registers. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
19. D/A Converter
D/A Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON
Bit Symbol DA0E Bit Name D/A0 output enable bit
Address 039Ch
Function 0: Output disabled 1: Output enabled 0: Output disabled 1: Output enabled
After Reset XXXX XX00b
RW RW
DA1E
D/A1 output enable bit Unimplemented. Write 0. Read as undefined value.
RW
- (b7-b2)
-
D/A Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON1
Bit Symbol DAT00 D/A0 conversion timing select bits(1)(2) DAT01 Bit Name
Address 039Dh
Function
b1 b0
After Reset XXXX 0000b
RW RW
0 0 1 1
0: When a value is written to D/A register 0 1: Timer A3 underflow 0: Timer A4 underflow 1: Timer B0 underflow
RW
DAT10 D/A1 conversion timing select bits(1)(2) DAT11
b3 b2
0 0 1 1
0: When a value is written to D/A register 1 1: Timer A3 underflow 0: Timer A4 underflow 1: Timer B0 underflow
RW
RW
- (b7-b4)
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. Set the selected timer for the conversion timing to timer mode. 2. Set bits DAi1 and DAi0 to 00b when the D/A converter is not used. (i = 0, 1)
D/A Register i (i = 0, 1)
b7 b0
Symbol DA0, DA1
Function Set output value to be D/A converted.
Address 0398h, 039Ah
After Reset Undefined
Setting Range 00h to FFh RW RW
Figure 19.2
DACON Register, DACON1 Register, DA0 and DA1 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
19. D/A Converter
DA0E 0 DA0 r 1 2R MSB Set in the DA0 register or DA0 buffer 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R
0
1
AVSS VREF(4) NOTES: 1. The above applies when the DA0 register is set to 2Ah. 2. D/A1 has the same circuitry as the avove. 3. When the D/A converter is not used, set the DAiE bit (i = 0,1) in the DACON register to 0 (output disabled) and registers DACON1 and DAi to 00h to stop current from flowing into the R-2R resistor to reduce unnecessary power consumption. 4. VREF remains connected even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected).
Figure 19.3
D/A Converter Equivalent Circuit
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
20. CRC Calculation
20. CRC Calculation
The CRC (Cyclic Redundancy Check) calculation detects an error in data blocks. A generator polynomial of CRC CCITT (X16 + X12 + X5 + 1) generates CRC code. The CRC code is a 16-bit code generated for a given length of the data block in bytes. The CRC code is stored in the CRCD register every time one-byte data is transferred to the CRCIN register after a default value is written to the CRCD register. CRC code generation for one-byte data is completed in two bus clock cycles. Figure 20.1 shows a block diagram of the CRC circuit. Figure 20.2 shows CRC-associated registers. Figure 20.3 shows an example of the CRC calculation.
High-order bits of data bus Low-order bits of data bus 8 low-order bits 8 high-order bits
CRCD register
CRC code generation circuit X16 + X12 + X5 + 1
CRCIN register
Figure 20.1
CRC Calculation Block Diagram
CRC Data Register
b15 b8 b7 b0
Symbol CRCD
Function
Address 037Dh - 037Ch
After Reset Undefined
Setting Range RW
After an initial value is written to the CRCD register, the CRC code can be read from the CRCD register by writing data to the CRCIN register. Bit position of the initial value is inverted. The inverted value is read as the CRC code.
0000h to FFFFh
RW
CRC Input Register
b7 b0
Symbol CRCIN
Function Data input. Inverse bit position of data
Adddress 037Eh
After Reset Undefined
Setting Range 00h to FFh RW RW
Figure 20.2
CRCD Register, CRCIN Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
20. CRC Calculation
CRC Calculation and Setup Procedure to Generate CRC Code for 80C4h
CRC Calculation for M32C
CRC code: a remainder of division, value of the CRCIN register with inversed bit position Generator polynomial
Generator polynomial: X16 + X12 + X5 + 1 (1 0001 0000 0010 0001b)
Setting Steps
(1) Invert a bit position of 80C4h per byte by a program 80h 01h, C4h 23h
b15 b0
(2) Set 0000h (default value)
CRCD register
b7
b0
(3) Set 01h
CRCIN register
Bit position of the CRC code for 80h (9188h) is inverted to 1189h, which is stored into the CRCD register in the 3rd cycle. b15 b0
1189h
CRCD register
b7
b0
(4) Set 23h
CRCIN register
Bit position of the CRC code for 80C4h (8250h) is inverted to 0A41h, which is stored into the CRCD register in the 3rd cycle.
b15
b0
0A41h
CRCD register
Details of CRC Calculation
As shown in (3) above, bit position of 01h (00000001b) written to the CRCIN register is inverted to 10000000b. Add 1000 0000 0000 0000 0000 0000b, as 10000000b plus 16 digits, to 0000h as the initial value of the CRCD register to perform the modulo-2 division. 1000 1000 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 Generator polynomial 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 CRC code 0001 0001 1000 1001b (1189h), the remainder 1001 0001 1000 1000b (9188h) with inversed bit position, can be read from the CRCD register. When going on to (4) above, 23h (00100011b) written in the CRCIN register is inverted to 11000100b. Add 1100 0100 0000 0000 0000 0000b plus 16 digits, to 1001 0001 1000 1000b as a remainder of (3) left in the CRCD register to perform the modulo-2 division. 0000 1010 0100 0001b (0A41h), the remainder with inverted bit position, can be read from CRCD register. Data Modulo-2 Arithmetic is calculated on the law below 0+0=0 0+1=1 1+0=1 1+1=0 -1 = 1
Figure 20.3
CRC Calculation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
21. X/Y Conversion
21. X/Y Conversion
The X/Y conversion rotates a 16 x 16 matrix data by 90 degrees and also inverts high-order bits and low-order bits of a 16-bit data. Figure 21.1 shows the XYC register. The 16-bit XiR register (i = 0 to 15) and 16-bit YjR register (j = 0 to 15) are allocated to the same address. The XiR register is a write-only register, while the YjR register is a read-only register. Access registers XiR and YjR from an even address in 16-bit units. Performance cannot be guaranteed if registers XiR and YjR are accessed in 8-bit units.
X/Y Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol XYC
Bit Symbol XYC0 Bit Name Read mode set bit
Address 02E0h
Function 0: Data converted 1: Data not converted 0: Bit alignment not converted 1: Bit alignment converted
After Reset XXXX XX00b
RW RW
XYC1
Write mode set bit Unimplemented. Write 0. Read as undefined value.
RW
- (b7-b2)
-
Figure 21.1
XYC Register
The XYC0 bit in the XYC register determines how to read the YjR register. When setting the XYC0 bit to 0 (data converted) and reading the YjR register, all the bits j in registers X0R to X15R can be read. For example, bit 0 in the X0R register can be read when reading bit 0 in the Y0R register, bit 0 in the X1R register when reading bit 1 in the Y0R register..., bit 0 in the X14R register when reading bit 14 in the Y0R register, and bit 0 in the X15R register when reading bit 15 in the Y0R register. Figure 21.2 shows a conversion table when the XYC0 bit is set to 0. Figure 21.3 shows an example of the X/Y conversion.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
21. X/Y Conversion
Read address
Y15R register Y14R register Y13R register Y12R register Y11R register Y10R register Y8R register Y9R register Y7R register Y6R register Y5R register Y4R register Y3R register Y2R register Y1R register Y0R register b0 b15
X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register b15 Bits in XiR register b0
Write address
Bits in YjR register
i = 0 to 15 j = 0 to 15
Figure 21.2
Conversion Table when the XYC0 Bit is Set to 0
b15
b14
b13
b12
b11
b10
b15
b14
b13
b12
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
b9
b8
b7
b6
b5
b4
b3
b2
b1
X0R register X1R register X2R register X3R register X4R register X5R register X6R register X7R register X8R register X9R register X10R register X11R register X12R register X13R register X14R register X15R register
Y0R register Y1R register Y2R register Y3R register Y4R register Y5R register Y6R register Y7R register Y8R register Y9R register Y10R register Y11R register Y12R register Y13R register Y14R register Y15R register
Figure 21.3
X/Y Conversion
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b0
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
21. X/Y Conversion
When setting the XYC0 bit in the XYC register to 1 (data not converted) and reading the YjR register, the value written to the XiR register can be read. Figure 21.4 shows a conversion table when the XYC0 bit is set to 1.
X0R register, X1R register, X2R register, X3R register, X4R register, X5R register, X6R register, Write address Read address X7R register, X8R register, X9R register,
Y0R register Y1R register Y2R register Y3R register Y4R register Y5R register Y6R register Y7R register Y8R register Y9R register
X10R register, Y10R register X11R register, Y11R register X12R register, Y12R register X13R register, Y13R register X14R register, Y14R register X15R register, Y15R register b15 Bits in XiR register Bits in YjR register b0 i = 0 to 15 j = 0 to 15
Figure 21.4
Conversion Table when the XYC0 Bit is Set to 1
The XYC1 bit in the XYC register selects bit alignment written to the XiR register. When the XYC1 bit is set to 0 (bit alignment not converted) and writing to the XiR register, bit alignment is written as is. When the XYC1 bit is set to 1 (bit alignment converted) and writing to the XiR register, inverted bit alignment is written. Figure 21.5 shows a conversion when the XYC1 bit is set to 1.
b15 Write data
b0
b15 XiR register (i = 0 to 15)
b0
Figure 21.5
Conversion when the XYC1 Bit is Set to 1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
22. Intelligent I/O
The intelligent I/O is multifunctional I/O ports, which can be used for time measurement function (input capture), waveform generation function (output compare), clock synchronous serial communication, clock asynchronous serial communication (UART), or HDLC data processing. The intelligent I/O in M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has three groups. Time measurement function or waveform generation function can be selected per channel. Table 22.1 lists functions and channels of the intelligent I/O. Table 22.1
Base timer Two-phase pulse signal processing mode Time measurement function Prescaler function Gate function Waveform generation function Single-phase waveform output mode Phase-delayed waveform output mode Set-Reset (SR) waveform output mode Bit modulation PWM output mode Real-time port output mode Parallel real-time output mode Communication function Data length Clock synchronous mode Clock asynchronous mode HDLC data processing mode IEBus mode (optional)(3) 1 channel 8 bits Provided Not Provided Provided Not Provided 1 channel 8 bits Provided Provided Provided Not Provided Not Provided Not Provided Not Provided
Intelligent I/O Functions and Channels
Function Group 0 Not Provided Group 1(1) 1 base timer Provided 8 channels 2 channels 2 channels 8 channels Provided Provided Provided 8 channels(2) Provided Provided Provided Provided Provided Provided 1 channel Variable length Provided Not Provided Not Provided Provided Not Provided Group 2 1 base timer Not Provided
NOTES: 1. The time measurement function and the waveform generation function can use a total of eight channels per group. 2. 8 channels are available in the 144-pin package. 3 channels are available in 100-pin package. 3. Please contact a Renesas sales office for optional features.
Figure 22.1 shows a block diagram of time measurement and waveform generation functions in group 1. Figure 22.2 shows a block diagram of waveform generation function in group 2. Figures 22.3 to 22.14 show registers associated with the base timer, time measurement and waveform generation functions. (See figures 22.36, 22.37, and 22.55 for block diagrams of the communication function, and figures 22.38 to 22.46 and 22.56 to 22.60 for registers associated with the communication function.)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Overflow of bit 15 in the base timer Overflow of bit 9 in the base timer Request from INT pin BT1S BTS
0 1
BTRE
Reset signal by matching the base timer with the G1PO0 register
Base timer reset Reset Divider 2(n+1) DIV4 to DIV0
11 f1 Two phase 10 pulse input BCK1 and BCK0
fBT1
Base timer Transmit data signal from the communication function
INPC1_0
ISCLK1 / INPC1_1
ISRXD1 / INPC1_2
INPC1_3
DF1 and DF0 CTS1 and CTS0 00 Edge G1TM0, G1PO0 Digital Select registers(1) filter 10: fBT1 11: f1 00 Edge G1TM1, G1PO1 Digital Select registers(1) filter 10, 11 Clock input to ISCLK1 pin 00 Edge G1TM2, G1PO2 Digital Select registers(1) filter 10, 11 Receive data input to ISRXD1 pin 00 Edge G1TM3, G1PO3 Digital Select registers(1) filter 10, 11 00 Edge Select 10, 11 00 Edge Select 10, 11 00 Edge Select 10, 11 0 Gate function 00 Digital filter 1 GT Edge Select 10, 11 0 Gate function 1 GT Prescaler function Prescaler function G1TM6, G1PO6 registers(1) 0 1 PR G1TM5, G1PO5 registers(1) G1TM4, G1PO4 registers(1)
MOD2 to MOD0 000 to 010 OUTC1_0 / ISTXD1
PWM output
111 000 to 010
Ch1 generation clock OUTC1_1 / ISCLK1
111
MOD2 to MOD0 Clock synchorous mode serial clock OUTC1_2 ch2 generation clock
PWM output
OUTC1_3 ch3 generation clock OUTC1_4 PWM output OUTC1_5
INPC1_4
Digital filter
INPC1_5
Digital filter
INPC1_6
Digital filter
OUTC1_6
PWM output
INPC1_7
G1TM7, G1PO7 registers(1) 0 1 PR
OUTC1_7
Ch0 to ch7 interrupt request signal
BTRE: Bit in the G1POCR0 register BT1S: Bit in the BTSR register BCK1 and BCK0, DIV4 to DIV0: Bits in the G1BCR0 register BTS: Bit in the G1BCR1 register CTS1 and CTS0, DF1 and DF0, GT, PR: Bits in the G1TMCRj register (j = 0 to 7) MOD2 to MOD0: Bits in the G1POCRj register NOTE: 1. After a clock, which is selected in the G1BCR0 register, is supplied to the registers, each register value becomes the after reset value.
Figure 22.1
Time Measurement/Waveform Generation Function in Group 1 Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Request from group 1 Request from the communication function BT2S BTS 11 Reset
Request generated by matching the base timer with the G2PO0 register Transmit data signal from the communication function Base Timer Reset Serial clock signal from the communication function Real Time Port output value Base timer
fBT2 f1 Divider 2 (n+1) DIV4 to DIV0
BCK1 and BCK0
G2PO0 register
Bit modulation PWM
MOD2 to MOD0 000 to 010, 100 PWM
output
OUTC2_0 / ISTXD2 / IEOUT 111 000 to 010, 100 OUTC2_1 / ISCLK2 111 MOD2 to MOD0 OUTC2_2
G2PO1 register
Bit modulation PWM Bit modulation PWM PWM
output
G2PO2 register
Ch2 generation clock OUTC2_3
G2PO3 register
Bit modulation PWM
G2PO4 register
Bit modulation PWM
OUTC2_4 PWM
output
G2PO5 register
Bit modulation PWM
OUTC2_5
(Note 1)
G2PO6 register
Bit modulation PWM
OUTC2_6 PWM
output
G2PO7 register
Bit modulation PWM
OUTC2_7 Start bit detect function Waveform generation function interrupt request PO2jR
DIV4 to DIV0, BCK1 and BCK0: Bits in the G2BCR0 register BTS: Bit in the G2BCR1 register BT2S: Bit in the BTSR register MOD2 to MOD0: Bits in the G2POCRj register (j = 0 to 7) PO2jR: Bits in registers IIO3IR, IIO5IR to IIO11IR BT2R:Bit in the IIO8IR register
Communication function output control
NOTES: 1. In the100-pin package, these output function cannot be used. 2. After a clock, which is selected in the G2BCR0 register, is supplied to the registers, each register value becomes the after reset value.
Figure 22.2
Waveform Generation Function in Group 2 Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 1 Base Timer Register(1)
b15 b8 b7 b0
Symbol G1BT
Function
Address 0121h - 0120h
After Reset Undefined
Setting Range RW
While the base timer is counting: When read, the base timer value is returned (2). When write, the count continues from the value written. While the base timer is in reset state: When read, undefined value is returned. No value can be written.
0000h to FFFFh
RW
NOTES: 1. The base timer operates when its count source is selected using bits BCK1 and BCK0 in the G1BCR0 register. When both the BT1S bit in the BTSR register and the BTS bit in the G1BCR1 register are set to 0, the base timer is placed in a reset state and the count value remains 0000h. When either the BT1S bit or the BTS bit is set to 1, the count starts. 2. The G1BT register reflects the value of the base timer with a half fBT1 clock cycle delay.
Group 1 Base Timer Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G1BCR0
Bit Symbol BCK0 Count source select bits BCK1 Bit Name
Address 0122h
Function
b1 b0
After Reset 00h
RW RW
0 0: Clock stopped 0 1: Do not set to this value 1 0: Two-phase pulse signal input (1) 1 1: f1
RW
DIV0
DIV1 Count source divide ratio select bits
If setting value is n (n = 0 to 31), the count source is divided by 2(n + 1). No division if n = 31.
RW
RW
DIV2
DIV3
(n = 0) 0 0 0 0 0: Divide-by-2 (n = 1) 0 0 0 0 1: Divide-by-4 (n = 2) 0 0 0 1 0: Divide-by-6 : (n = 30) 1 1 1 1 0: Divide-by-62 (n = 31) 1 1 1 1 1: No division
b6 b5 b4 b3 b2
RW
RW
DIV4 Base timer interrupt generation timing select bit 0: When bit 15 changed from 1 to 0 1: When bit 14 changed from 1 to 0
RW
IT
RW
NOTE: 1. To set bits BCK1 and BCK0 to 10b (two-phase pulse signal input), set bits UD1 and UD0 in the G1BCR1 register to 10b (twophase pulse signal processing mode).
Figure 22.3
G1BT Register, G1BCR0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 1 Base Timer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol G1BCR1
Bit Symbol Bit Name
Address 0123h
Function
After Reset X000 000Xb
RW
- (b0)
Unimplemented. Write 0. Read as undefined value. Base timer reset source select bit 1 0: Base timer is not reset by matching the G1PO0 register 1: Base timer is reset by matching the G1PO0 register(1) 0: Base timer is not reset by applying "L" to the INT0 or INT1 pin 1: Base timer is reset by applying "L" to the INT0 or INT1 pin(2) Set to 0 0: Base timer reset 1: Base timer count starts
b6 b5
-
RST1
RW
RST2
Base timer reset source select bit 2
RW
- (b3)
BTS
Reserved bit
RW
Base timer start bit (3)
RW
UD0 Counter increment/ decrement control bits UD1
0 0: Counter increment mode 0 1: Counter increment/decrement mode 1 0: Two-phase pulse signal processing mode (4) 1 1: Do not set to this value
RW
RW
- (b7)
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. The base timer is reset at the second fBT1 clock cycle after the base timer matches the G1PO0 register. 2. The IPSA_0 bit in the IPSA register selects the input pin, either INT0 or INT1. 3. Use the BTSR register when multiple base timers start counting simultaneously. In this case, set the BTS bit to 0. 4. In two-phase pulse signal processing mode, the base timer is not reset if the counter is decremented at the second clock cycle after the base timer matches the G1PO0 register, even though the RST1 bit is set to 1.
Figure 22.4
G1BCR1 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 1 Time Measurement Control Register i (i = 0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G1TMCR0 to G1TMCR3 G1TMCR4 to G1TMCR7
Address 0118h, 0119h, 011Ah, 011Bh 011Ch, 011Dh, 011Eh, 011Fh
After Reset 00h 00h
Bit Symbol CTS0
Bit Name
b1 b0
Function
RW RW
Time measurement trigger select bits CTS1
0 0: No time measurement 0 1: Rising edge 1 0: Falling edge 1 1: Both edges
b3 b2
RW
DF0 Digital filter select bits DF1
0 0: No digital filter 0 1: Do not set to this value 1 0: Use digital filter (use fBT1 as sampling clock) 1 1: Use digital filter (use f1 as sampling clock) 0: Gate function not used 1: Gate function used 0: No trigger input is accepted by matching the base timer and the G1POk register (k = 4, 5) 1: One trigger input is accepted after matching the base timer and the G1POk register One trigger input is accepted after setting the GSC bit to 1 0: Prescaler function not used 1: Prescaler function used
RW
RW
GT
Gate function select bit (1)
RW
GOC
Gate release bit 1(1)( 2)
RW
GSC
Gate release bit 2(1)(2)
RW
PR
Prescaler function select bit (1)
RW
NOTES: 1. The gate function (bits GT, GOC, and GSC) and the prescaler function (PR bit) are available in registers G1TMCR6 and G1TMCR7 only. Set each bit 4 to 7 in registers G1TMCR0 to G1TMCR5 to 0. 2. Bits GOC and GSC are enabled only when the GT bit is set to 1.
Group 1 Time Measurement Prescaler Register i (i = 6, 7)
b7 b0
Symbol G1TPR6, G1TPR7
Address 0124h, 0125h
After Reset 00h
Function If the setting value is n, the time measurement is performed every time a trigger input is counted n+1 times(1)
Setting Range 00h to FFh
RW RW
NOTE: 1. After the PR bit in the G1TMCRi register is changed from 0 (prescaler function not used) to 1 (prescaler function used), the first time measurement may be performed when a trigger input is counted n times.
Figure 22.5
G1TMCR0 to G1TMCR7 Registers, G1TPR6 and G1TPR7 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 1 Time Measurement Register i (i = 0 to 7)
b15 b8 b7 b0
Symbol G1TM0 to G1TM2 G1TM3 to G1TM5 G1TM6, G1TM7
Address 0101h - 0100h, 0103h - 0102h, 0105h - 0104h 0107h - 0106h, 0109h - 0108h, 010Bh - 010Ah 010Dh - 010Ch, 010Fh - 010Eh
Function Setting Range
After Reset Undefined Undefined Undefined
RW RO
The base timer value is stored every time measurement is performed
-
Group 1 Waveform Generation Control Register i (i = 0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G1POCR0 G1POCR1 to G1POCR3 G1POCR4 to G1POCR7
Bit Symbol MOD0 Bit Name
Address 0110h 0111h, 0112h, 0113h 0114h, 0115h, 0116h, 0117h
Function
b2 b1 b0
After Reset 0000 X000b 0X00 X000b 0X00 X000b
RW RW
MOD1
Operating mode select bits
MOD2
0 0 0: Single waveform output mode 0 0 1: SR waveform output mode (1) 0 1 0: Phase-delayed waveform output mode 0 1 1: Do not set to this value 1 0 0: Do not set to this value 1 1 0: Do not set to this value (2) 1 1 1: Use communication function output (3)
RW
RW
- (b3)
IVL
Unimplemented. Write 0. Read as undefined value. Output level select bit (5) G1POi register value reload timing select bit Base timer reset timing select bit(4) Inverted output function select bit(5) 0: "L" output 1: "H" output 0: Reload when written 1: Reload when the base timer is reset 0: Base timer is reset when the bit 15 overflows 1: Base timer is reset when the bit 9 overflows (6) 0: Output not inverted 1: Output inverted
-
RW
RLD
RW
BTRE
RW
INV
RW
NOTES: 1. SR waveform output mode is enabled only in even channels. In SR waveform output mode, the setting for the corresponding odd channel (the channel followed by the even channel) is ignored. SR waveform can be output from even channels, and not from odd channels. 2. To perform the UART receive operation in group 1, set the G1POCR2 register to 0000 0110b. 3. To use the ISTXD1 pin, set bits MOD2 to MOD0 in the G1POCR0 register to 111b. To use the ISCLK1 pin as output, set bits MOD2 to MOD0 in the G1POCR1 register to 111b. Do not set bits MOD2 to MOD0 in registers G1POCR2 to G1POCR7 to 111b. 4. The BTRE bit is available only in the G1POCR0 register. Set the bit 6 in registers G1POCR1 to G1POCR7 to 0. 5. If the INV or IVL bit is written while outputting waveform, the value written takes effect immediately on the output waveform. 6. When the BTRE bit is set to 1, set bits BCK1 and BCK0 in the G1BCR0 register to 11b (f1), and bits UD1 and UD0 in the G1BCR1 register to 00b (counter increment mode).
Figure 22.6
G1TM0 to G1TM7 Registers, G1POCR0 to G1POCR7 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 1 Waveform Generation Register i (i = 0 to 7)
b15 b8 b7 b0
Symbol G1PO0 to G1PO2 G1PO3 to G1PO5 G1PO6, G1PO7
Address 0101h - 0100h, 0103h - 0102h, 0105h - 0104h 0107h - 0106h, 0109h - 0108h, 010Bh - 010Ah 010Dh - 010Ch, 010Fh - 010Eh
Function Setting Range
After Reset Undefined Undefined Undefined
RW
When the G1POi register is read, the value written is returned. When a value is written to the G1POi register: - If the RLD bit in the G1POCRi register is set to 0, the value written is immediately reloaded into the internal register and reflected in such as output waveform. - If the RLD bit in the G1POCRi register is set to 1, the value written is reloaded into the internal register when the base timer is reset.
0000h to FFFFh
RW
Figure 22.7
G1PO0 to G1PO7 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 1 Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G1FS
Bit Symbol FSC0 Bit Name
Address 0127h
Function
After Reset 00h
RW RW
Channel 0 time measurement/waveform generation function select bit Channel 1 time measurement/waveform generation function select bit Channel 2 time measurement/waveform generation function select bit Channel 3 time measurement/waveform generation function select bit Channel 4 time measurement/waveform generation function select bit Channel 5 time measurement/waveform generation function select bit Channel 6 time measurement/waveform generation function select bit Channel 7 time measurement/waveform generation function select bit
0: Waveform generation function selected 1: Time measurement function selected
FSC1
RW
FSC2
RW
FSC3
RW
FSC4
RW
FSC5
RW
FSC6
RW
FSC7
RW
Group 1 Function Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G1FE
Bit Symbol IFE0 Bit Name Channel 0 function enable bit Channel 1 function enable bit Channel 2 function enable bit Channel 3 function enable bit Channel 4 function enable bit Channel 5 function enable bit Channel 6 function enable bit Channel 7 function enable bit
Address 0126h
Function
After Reset 00h
RW RW
0: Channel i's function disabled (i = 0 to 7) 1: Channel i's function enabled
IFE1
RW
IFE2
RW
IFE3
RW
IFE4
RW
IFE5
RW
IFE6
RW
IFE7
RW
Figure 22.8
G1FS Register, G1FE Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 2 Base Timer Register(1)
b15 b8 b7 b0
Symbol G2BT
Function
Address 0161h - 0160h
After Reset Undefined
Setting Range RW
While the base timer is counting: When read, the base timer value is returned (2). When write, the count continues from the value written. While the base timer is in reset state: When read, undefined value is returned. No value can be written.
0000h to FFFFh
RW
NOTES: 1. The base timer operates when its count source is selected using bits BCK1 and BCK0 in the G2BCR0 register. When both the BT2S bit in the BTSR register and the BTS bit in the G2BCR1 register are set to 0, the base timer is placed in a reset state and the count value remains 0000h. When either the BT2S or the BTS bit is set to 1, the count starts. 2. The G2BT register reflects the value of the base timer with a half fBT2 clock cycle delay.
Group 2 Base Timer Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G2BCR0
Bit Symbol BCK0 Count source select bits BCK1 Bit Name
Address 0162h
Function
b1 b0
After Reset 00h
RW RW
0 0: Clock stopped 0 1: Do not set to this value 1 0: Do not set to this value 1 1: f1
RW
DIV0
DIV1 Count source divide ratio select bits
If setting value is n (n = 0 to 31), the count source is divided by 2(n + 1). No division if n = 31.
RW
RW
DIV2
DIV3
(n = 0) 0 0 0 0 0: Divide-by-2 (n = 1) 0 0 0 0 1: Divide-by-4 (n = 2) 0 0 0 1 0: Divide-by-6 : (n = 30) 1 1 1 1 0: Divide-by-62 (n = 31) 1 1 1 1 1: No division
b6 b5 b4 b3 b2
RW
RW
DIV4 Base timer interrupt generation timing select bit 0: When bit 15 is changed from 1 to 0 1: When bit 14 is changed from 1 to 0
RW
IT
RW
Figure 22.9
G2BT Register, G2BCR0 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 2 Base Timer Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol G2BCR1
Bit Symbol Bit Name
Address 0163h
Function
After Reset 00h
RW
RST0
Base timer reset source select bit 0
0: Base timer is not reset when the base timer in group 1 is reset. 1: Base timer is reset when the base timer in group 1 is reset. 0: Base timer is not reset by matching the G2PO0 register 1: Base timer is reset by matching the G2PO0 register(1) 0: Base timer is not reset by a reset request from the communication function 1: Base timer is reset by a reset request from the communication function Set to 0 0: Base timer reset 1: Base timer count starts Set to 0 0: Real-time port output mode 1: Parallel read-time port output mode
RW
RST1
Base timer reset source select bit 1
RW
RST2
Base timer reset source select bit 2
RW
- (b3)
Reserved bit
RW
BTS
- (b6-b5)
Base timer start bit (3)
RW
Reserved bits Parallel real-time port function select bit(2)
RW
PRP
RW
NOTES: 1. The base timer is reset at the second fBT1 clock cycle after the base timer matches the G2PO0 register. 2. The PRP bit is enabled when the RTP bit in the G2POCRi register is set to 1 (real-time port function used). 3. Use the BTSR register when multiple base timers start counting simultaneously. In this case, set the BTS bit to 0.
Figure 22.10
G2BCR1 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 2 Waveform Generation Control Register i (i = 0 to 7)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G2POCR0 to G2POCR3 G2POCR4 to G2POCR7
Address 0150h, 0151h, 0152h, 0153h 0154h, 0155h, 0156h, 0157h
After Reset 00h 00h
Bit Symbol MOD0
Bit Name
b2 b1 b0
Function
RW RW
MOD1
Operating mode select bits(3)
MOD2
0 0 0: Single waveform output mode 0 0 1: SR waveform output mode(1) 0 1 0: Phase-delayed waveform output mode 0 1 1: Do not set to this value 1 0 0: Bit modulation PWM output mode 1 0 1: Do not set to this value 1 1 0: Do not set to this value 1 1 1: Use communication function output (2) 0: Signal output when base timer matches the G2POi register is not used as a trigger 1: Signal output when base timer matches the G2POi register is used as a trigger 0: "L" output 1: "H" output 0: Reload when written 1: Reload when the base timer is reset 0: Not used 1: Used (real-time port output mode or parallel real-time port output mode) 0: Output not inverted 1: Output inverted
RW
RW
PRT
Parallel real-time port output trigger select bit(4)
RW
IVL
Output level select bit (6)
RW
RLD
G2POi register value reload timing select bit Real-time port function select bit(3)(4) Inverted output function select bit(5)(6)
RW
RTP
RW
INV
RW
NOTES: 1. SR waveform output mode is enabled only in even channels. In SR waveform output mode, the setting for the corresponding odd channel (the channel followed by the even channel) is ignored. SR waveform can be output from even channels, and not from odd channels. 2. To use the ISTXD2 pin or IEOUT pin as output, set bits MOD2 to MOD0 in the G2POCR0 register to 111b. To use the ISCLK2 pin as output, set bits MOD2 to MOD0 in the G2POCR1 register to 111b. Do not set bits MOD2 to MOD0 in registers G2POCR2 to G2POCR7 to 111b. 3. When the RTP bit is set to 1, set bits MOD2 to MOD0 to 000b. 4. Real-time port output and parallel real-time port output cannot be used in the same group. To use parallel real-time port output, set the RTP bit to 1 and the PRT bit to 1 in the channel used for parallel real-time port output. Also, set the PRP bit in the G2BCR1 register to 1. 5. When the RTP bit is set to 1, the INV bit setting is disabled. 6. If the INV or IVL bit is written while outputting waveform, the value written takes effect immediately on the output waveform.
Figure 22.11
G2POCR0 to G2POCR7 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 2 Waveform Generation Register i (i = 0 to 7)
b15 b8 b7 b0
Symbol G2PO0 to G2PO2 G2PO3 to G2PO5 G2PO6, G2PO7
Address 0141h - 0140h, 0143h - 0142h, 0145h - 0144h 0147h - 0146h, 0149h - 0148h, 014Bh - 014Ah 014Dh - 014Ch, 014Fh - 014Eh
Function Setting Range
After Reset Undefined Undefined Undefined
RW
When the G2POi register is read, the value written is returned. When a value is written to the G2POi register: - If the RLD bit in the G2POCRi register is set to 0, the value written is immediately reloaded into the internal register and reflected in such as output waveform. - If the RLD bit in the G2POCRi register is set to 1, the value written is reloaded into the internal register when the base timer is reset.
0000h to FFFFh
RW
Figure 22.12
G2PO0 to G2PO7 Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Group 2 Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G2RTP
Bit Symbol RTP0 Bit Name
Address 0167h
Function 0: "L" output 1: "H" output
After Reset 00h
RW RW
Channel 0 RTP output buffer
RTP1
Channel 1 RTP output buffer
RW
RTP2
Channel 2 RTP output buffer
RW
RTP3
Channel 3 RTP output buffer
RW
RTP4
Channel 4 RTP output buffer
RW
RTP5
Channel 5 RTP output buffer
RW
RTP6
Channel 6 RTP output buffer
RW
RTP7
Channel 7 RTP output buffer
RW
Group 2 Function Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G2FE
Bit Symbol IFE0 Bit Name Channel 0 function enable bit Channel 1 function enable bit Channel 2 function enable bit Channel 3 function enable bit Channel 4 function enable bit Channel 5 function enable bit Channel 6 function enable bit Channel 7 function enable bit
Address 0166h
Function
After Reset 00h
RW RW
0: Channel i's function disabled (i = 0 to 7) 1: Channel i's function enabled
IFE1
RW
IFE2
RW
IFE3
RW
IFE4
RW
IFE5
RW
IFE6
RW
IFE7
RW
Figure 22.13
G2RTP Register, G2FE Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O
Base Timer Start Register(1)(2)(3)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol BTSR
Bit Symbol
- (b0)
Address 0164h
Bit Name Reserved bit Set to 0 0: Base timer reset 1: Base timer count starts 0: Base timer reset 1: Base timer count starts Set to 0 Function
After Reset XXXX 0000b
RW RW
BT1S
Group 1 base timer start bit
RW
BT2S
- (b3) - (b7-b4)
Group 2 base timer start bit
RW
Reserved bit Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. To use the intelligent I/O, follow the procedure below in the initial configuration. (1) Set the G2BCR0 register to supply the clock to the group 2 base timer. (2) Set all the BTiS bits (i = 1, 2) to 0 (base timer reset). (3) Set the other registers associated with the intelligent I/O. The BTiS bits are used to start the base timers in group 1 and group 2 simultaneously. To start each base timer independently, set the BTiS bits to 0 and use the BTS bit in the GiBCR1 register. 2. To start the base timers in group 1 and group 2 simultaneously, set as follows. - Set bits BCK1 and BCK0, and bits DIV4 to DIV0 in the GiBCR0 register to the same value in group 1 and group 2. - If bits BCK1 and BCK0 or bits DIV4 to DIV0 are changed, set the BTiS bits to 1 twice using the following procedure. (1) Set the BTiS bits to 1 (base timer count starts). (2) Wait for one or more fBTi clock cycles, and then set the BTiS bits to 0 (base timer reset). (3) Wait another one or more fBTi clock cycles, and then set the BTiS bits to 1. 3. The BTSR register is enabled after setting the G2BCR0 register.
Figure 22.14
BTSR Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Base Timer)
22.1
Base Timer
The base timer, a 16-bit free running counter, is available in group 1 and group 2. Registers in group 1 and group 2 are initialized and written using the base timer clock (fBT) selected in the GiBCR0 register (i = 1, 2). The BTSR register is initialized and written using the base timer clock in group 2. Ensure to select the base timer clock in the G2BCR0 register to initialize the BTSR register; otherwise the BTSR register value remains undefined and the base timer in group 1 may start counting unintentionally. The base timer counts an internally generated count source continuously. Tables 22.2 and 22.3 list specifications of the base timer. Figure 22.15 shows a block diagram of the base timer. Figure 22.16 shows a base timer operation example in counter increment mode. Figure 22.17 shows a base timer operation example in count increment/decrement mode. Table 22.2 Base Timer Specifications (Group 1)
Item Count source (fBT1) Specification * f1 divided by 2(n+1) * Two-phase pulse input divided by 2(n+1) n: determined by bits DIV4 to DIV0 in the G1BCR0 register (n = 0 to 31); no division when n = 31 * Counter increments * Counter both increments and decrements * Two-phase pulse signal processing * When the base timers in groups 1 and 2 start counting independently: Set the BTS bit in the G1BCR1 register to 1 (base timer count starts) *When the base timers in groups 1 and 2 start counting simultaneously: Set bits BT2S and BT1S in the BTSR register to 11b (base timer count starts) Base timer count stops when both of the following conditions are met: * The BT1S bit in the BTSR register is set to 0 (base timer reset) * The BTS bit in the G1BCR1 register to 0 (base timer reset) * The base timer value matches the G1PO0 register value(1) * Bit 15 of the base timer overflows * Bit 9 of the base timer overflows * A low-level ("L") signal is input to the INT0 or INT1 pin 0000h When bit 9, 14, or 15 of the base timer is changed from 1 to 0 The BT1R bit in the IIO4IR register becomes 1 (interrupt requested) when the interrupt request is generated. * Count value is returned when reading the G1BT register while the base timer is counting * Undefined value is returned when reading the G1BT register while the base timer is in reset * When a value is written while the base timer is counting, the count continues from the value written * No value can be written while base timer is in reset state Counter increment/decrement mode * The base timer starts incrementing when the BTS bit is set to 1. When the count reaches FFFFh, the base timer decrements. * If the RST1 bit in the G1BCR1 register is set to 1 (base timer is reset by matching the G1PO0 register), the base timer decrements at the third clock cycle after the base timer value matches the G1PO0 register. Then, the base timer increments again when the count reaches 0000h. Two-phase pulse processing mode * Count two-phase pulse signals from pins P8_0 and P8_1, or pins P7_6 and P7_7. Pins are selectable using the IPSA_0 bit in the IPSA register.
Count operation
Count start condition
Count stop condition
Base timer reset condition
Value when the base timer is in reset state Interrupt request generation timing Read from base timer
Write to base timer
Selectable function
NOTE: 1. When bits RST2 and RST1 in the G1BCR1 register are set to 01b (base timer is reset by matching the G1PO0 register), the setting range of the G1PO0 register must be 0001h to FFFDh.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.3 Base Timer Specifications (Group 2)
Item Count source (fBT2) Specification
22. Intelligent I/O (Base Timer)
* f1 divided by 2(n+1) n: determined by bits DIV4 to DIV0 in the G2BCR0 register (n = 0 to 31); no division when n = 31 * Counter increments * When the base timers in groups 1 and 2 start counting independently: Set the BTS bit in the G2BCR1 register to 1 (base timer count starts) * When the base timers in groups 1 and 2 start counting simultaneously: Set bits BT2S and BT1S in the BTSR register to 11b (base timer count starts) Base timer count stops when both of the following conditions are met: * The BT2S bit in the BTSR register is set to 0 (base timer reset) * The BTS bit in the G2BCR1 register to 0 (base timer reset) * The base timer value matches the G2PO0 register value(1) * Bit 15 of the base timer overflows * When the base timer in group 1 is reset * Reset request from the communication function 0000h When bit 14 or 15 of the base timer is changed from 1 to 0 The BT2R bit in the IIO8IR register becomes 1 (interrupt requested) when the interrupt request is generated. * Count value is returned when reading the G2BT register while the base timer is counting * Undefined value is returned when reading the G2BT register while the base timer is in reset state * When a value is written while the base timer is counting, the count continues from the value written * No value can be written while base timer is in reset
Count operation Count start condition
Count stop condition
Base timer reset condition
Value when the base timer is in reset state Interrupt request generation timing Read from base timer
Write to base timer
NOTE: 1. When bits RST2 and RST1 in the G2BCR1 register are set to 01b (base timer is reset by matching the G2PO0 register), the setting range of the G2PO0 register must be 0001h to FFFDh.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Base Timer)
(1) Group 1
fBT1 BCK1 and BCK0 f1 Two phase pulse input BT1S BTS Reset signal by matching the base timer with the G1PO0 register "L" is applied to the INT0 or INT1 pin RST1 Base timer reset 11 10 Divider 2(n+1) (Note 1) 0 Base Timer
b9 b14 b15
Overflow signal 1 0 BTRE IT Base timer interrupt request
1
RST2
(2) Group 2
fBT2 BCK1 and BCK0 f1 11 Divider 2(n+1) (Note 1) Base Timer
b0 to b13 b14 b15
Overflow signal 0 1 IT Base timer interrupt request
BT2S BTS RST0 Reset signal from group 1 base timer Reset signal by matching the base timer with the G2PO0 register Request from communication function i = 1, 2 BCK1 and BCK0, IT: Bits in the GiBCR0 register RST1, RST2, BTS: Bits in the GiBCR1 register RST0: Bit in the G2BCR1 register BTRE: Bit in the G1POCR0 register BT1S, BT2S: Bits in the BTSR register NOTE: 1. The divider is reset when both the BTiS and BTS bits are set to 0. RST1 Base timer reset
RST2
Figure 22.15
Base Timer Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Base Timer)
(1) When the IT bit in the GiBCR0 register is set to 0 (base timer interrupt request occurs when bit 15 is changed from 1 to 0)
FFFFh
Contents of the counter
8000h
0000h Status of bit 15 1 0 1 0 Set to 0 by a program
BTiR bit in the IIOkIR register
(2) When the IT bit in the GiBCR0 register is set to 1 (base timer interrupt request occurs when bit 14 is changed from 1 to 0)
FFFFh
C000h Contents of the counter
8000h
4000h
0000h Status of bit 14 1 0 1 0 Set to 0 by a program When i = 1, k = 4 and when i = 2, k = 8 The above applies under the following conditions: - Group1: G1BCR1 register; the RST1 bit is set to 0 (base timer is not reset by matching the G2PO0 register) bits UD1 to UD0 are set to 00b (counter increment mode) - Group2: Bits RST2 to RST0 in the G2BCR1 register are set to 000b (base timer is not reset)
BTiR bit in the IIOkIR register
Figure 22.16
Base Timer Operation in Counter Increment Mode (Group 1 and 2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Base Timer)
(1) When the IT bit in the G1BCR0 register is set to 0 (base timer interrupt request occurs when bit 15 is changed from 1 to 0)
FFFFh
Contents of the counter
8000h
0000h Status of bit 15 1 0 1 0 Set to 0 by a program
BT1R bit in the IIO4IR register
The above applies under the following conditions: - G1BCR1 register: the RST1 bit is set to 0 (Base timer is not reset by matching the base timer and the G1PO0 register) bits UD1 and UD0 are set to 01b (counter increment/decrement mode)
(2) When the IT bit in the G1BCR0 register is set to 1 (base timer interrupt request occurs when bit 14 is changed from 1 to 0)
FFFFh C000h Contents of the counter 8000h 4000h 0000h Status of bit 14 1 0 1 0 Set to 0 by a program The above applies under the following conditions: - G1BCR1 register: the RST1 bit is set to 0 (Base timer is not reset by matching the base timer and the G1PO0 register) bits UD1 and UD0 are set to 01b (counter increment/decrement mode)
BT1R bit in the IIO4IR register
(3) When the RST1 bit in the G1BCR1 register is set to 1 (Base timer is reset by matching the base timer and the G1PO0 register)
8002h 8000h Contents of the counter
0000h The above applies under the following conditions: - The G1PO0 register is set to 8000h - Bits UD1 and UD0 in the G1BCR1 register are set to 01b (counter increment/decrement mode)
Figure 22.17
Base Timer Operation in Count Increment/Decrement Mode (Group 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Base Timer)
Input waveform
P8_0 (P7_6)(2) (A phase) P8_1 (P7_7)(2) (B phase)
"H" "L" "H" "L" Timer increments at all edges Timer decrements at all edges
(1) When the base timer is reset while count value is incremented
P8_0 (P7_6)(2) (A phase) P8_1 (P7_7)(2) (B phase) "H" "L" "H" "L"
Min. 1 s Min. 1 s
Input waveform
fBT1 [When the 2(n+1) divider selects no division] INT1 (Z Phase) "H" "L" m m+1 0 Becomes 0 in this timing (Note1) The base timer starts counting 1 Becomes 1 in this timing 2
Count value
(2) When the base timer is reset while count value is decremented
P8_0 (P7_6)(2) (A phase) Input waveform P8_1 (P7_7)(2) (B phase) fBT1 [When the 2(n+1) divider selects no division] INT1 (Z Phase) "H" "L" m m-1 0 Becomes 0 in this timing (Note1) The base timer starts counting FFFFh FFFEh "H" "L" "H" "L"
Min. 1 s Min. 1 s
Count value
Becomes FFFFh in this timing
NOTES: 1. The width requires 1.5 or more fBT1 clock cycles. 2. The IPSA_0 bit in the IPSA register determines two-phase pulse input pins, whether P8_0 and P8_1 or P7_6 and P7_7.
Figure 22.18
Base Timer Operation in Two-Phase Pulse Signal Processing Mode (Group 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
22.2
Time Measurement Function (Input Capture)
When the external trigger is input, the base timer value is stored into the G1TMi register (i = 0 to 7). The time measurement function is available in group 1. Table 22.4 shows specifications of the time measurement function. Table 22.5 lists pin settings for the time measurement function. Figure 22.19 shows register settings. Figure 22.20 shows an example of time measurement function operation. Table 22.4 Time Measurement Function Specifications
Item Measurement channel INPC1_ i pin (i = 0 to 7) Trigger input polarity Measurement start condition Group 1: Channels 0 to 7 Trigger input Selectable among rising edge, falling edge, or both edges Time measurement starts when all of the following conditions are met: * Base timer count starts * Set the FSCi bit in the G1FS register to 1 (time measurement function selected) * Set the IFEi bit in the G1FE register to 1 (channel i's function enabled) Time measurement stops when any of the following conditions is met: * Set the IFEi bit to 0 (channel i's function disabled) * Base timer count stops (function in all channels disabled) * Without prescaler: every time a valid edge is input * With prescaler (channels 6 and 7): every (G1TPRj register value + 1) times a valid edge is input (j = 6, 7) Specification
Measurement stop condition
Time measurement timing
Interrupt request generation timing At the time measurement timing The TM1iR bit in the IIOkIR register (k = 0 to 4, 8 to 10) becomes 1 (interrupt requested) when an interrupt request is generated. (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Digital filter function The digital filter samples a trigger input signal level using f1 or fBT1 and passes the pulse that have matched its signal level three times * Prescaler function (channels 6 and 7) Time measurement is performed every (G1TPRj register value + 1) times a trigger is input * Gate function (channels 6 and 7) After a time measurement is performed by the first trigger input, the subsequent trigger inputs are all ignored. Thereafter, one trigger input is accepted when either of the following conditions is met: - Base timer value matches the G1POn register value (n = 4, 5) - Set the GSC bit in the G1TMCRj register to 1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.5
Port P7_0 P7_1 P7_3 P7_4 P7_5 P7_6 P7_7 P8_1 P11_0(1) P11_1(1) P11_2(1) P11_3(1) P14_0(1) P14_1(1) P14_2(1) P14_3(1)
22. Intelligent I/O (Time Measurement Function)
Pin Settings for Time Measurement Function
Bit Setting Function INPC1_6 INPC1_7 INPC1_0 INPC1_1 INPC1_2 INPC1_3 INPC1_4 INPC1_5 INPC1_0 INPC1_1 INPC1_2 INPC1_3 INPC1_4 INPC1_5 INPC1_6 INPC1_7 IPS1 = 1 IPS1 = 0 IPS Register PD7, PD8, PD11, PD14 Registers PD7_0 = 0 PD7_1 = 0 PD7_3 = 0 PD7_4 = 0 PD7_5 = 0 PD7_6 = 0 PD7_7 = 0 PD8_1 = 0 PD11_0 = 0 PD11_1 = 0 PD11_2 = 0 PD11_3 = 0 PD14_0 = 0 PD14_1 = 0 PD14_2 = 0 PD14_3 = 0 PS1, PS2, PS5, PS8 Registers PS1_0 = 0 PS1_1 = 0 PS1_3 = 0 PS1_4 = 0 PS1_5 = 0 PS1_6 = 0 PS1_7 = 0 PS2_1 = 0 PS5_0 = 0 PS5_1 = 0 PS5_2 = 0 PS5_3 = 0 PS8_0 = 0 PS8_1 = 0 PS8_2 = 0 PS8_3 = 0
NOTE: 1. This port is provided in the 144-pin package only.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 343 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
Start
I flag = 0 Pin settings for time measurement IIOkIE register: TM1iE bit = 0 G2BCR0 register = 01111111b BTSR register = 00h G2BCR0 register = 00h G1BCR0 register: bits BCK1 and BCK0 = 11b bits DIV4 to DIV0 IT bit G1BCR1 register: bits RST2 and RST1 BTS bit = 0 bits UD1 and UD0 G1TMCRi register: bits CTS1 and CTS0 bits DF1 and DF0 bits GT, GOC, and GSC = 000b PR bit = 0 G1FS register: FSCi bit = 1 G1FE register: IFEi bit = 1
Interrupt disabled
Time measuremet interrupt request disabled
Select f1 as count source Count source divide ratio select bits Base timer interrupt generation timing select bit
Base timer reset source select bits Base timer reset Counter increment/decrement control bits
Time measurement trigger select bits Digital filter select bits Gate function not used Prescaler function not used Time measurement function selected Channel i's function enabled
When using gate or prescaler function, refer to the figures Register Settings for gate/prescaler function
Wait time (2 or more fBT1 clock cycles) < When interrupt is used > IIOkIR register = 00h(1) IIOkIE register: IRLT bit = 1 IIOkIE register: TM1iE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 I flag = 1 Interrupt not requested Interrupt request is used for interrupt Time measuremet interrupt request enabled Interrupt priority level select bit Interrupt not requested Interrupt enabled Do not set at the same time. Set the TM1iE bit to 1 after setting the IRLT bit to 1.
G1BCR1 register: BTS bit = 1
Base timer count starts
End
i = 0 to 7; k = 0 to 4, 8 to 10 NOTE: 1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated in the same register (Interrupt does not occur).
Figure 22.19
Register Settings for Time Measurement Function
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 344 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
(1) When digital filter function is not used (Bits DF1 and DF0 in the G1TMCRi register are set to 00b)
Input to the INPC1_i pin "H" "L" FFFFh Base timer 1 (Note 1)
0000h Count source of base timer Base timer value Read value from the G1BT register Internal trigger signal "H" "L"
m+1 m+7 m-1 m m+1 m+2 m+3 m+4 m+5 m+6 m+7 m+8 m+9 m+10 m+11 m+12 m+13 FFFF
m
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+8
m+9
m+10 m+11 m+12 m+13
FFFF
G1TMi register TM1iR bit 1 0
Set to 0 by a program
Max. of 1.5 clock cycles delay
(2) When digital filter function is used (Bits DF1 and DF0 in the G1TMCRi register are set to 10b (fBT1 is selected as sampling clock))
An input signal which does not match its level three times is ignored "H" "L"
Input to the INPC1_i pin Count source of base timer Base timer value Internal trigger signal G1TMi register TM1iR bit
m
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+8
m+9
m+10 m+11 m+12 m+13
FFFF
"H" "L"
m+10
1 0
Set to 0 by a program
i = 0 to 7 The TM1iR bit: bit in registers IIO0IR to IIO4IR and IIO8IR to IIO10IR The above applies under the following conditions: - G1TMCRi register: bits CTS1 and CTS0 are set to 01b (rising edge is selected for time measurement trigger) the PR bit is set to 0 (prescaler function is not used) the GT bit is set to 0 (gate function is not used) - G1BCR1 register: bits RST2 and RST1 are set to 00b (base timer is not reset) bits UD1 and UD0 are set to 00b (counter increment mode) NOTE: 1. The width of pulse input to INPC1_i pin requires 1.5 or more fBT1 clock cycles.
Trigger signal is delayed for max. 4.5 clock cycles due to the digital filter
Figure 22.20
Time Measurement Function Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
22.2.1
Prescaler Function
With the prescaler function, a time measurement is performed every (G1TPRj register value + 1) times a trigger is input. The prescaler function is available in channel 6 and channel 7 in group 1. Figure 22.21 shows register settings. Figure 22.22 shows an example of prescaler function operation.
Start Refer to the figure Register Settings for Time Measurement Function G1TMCRj register: bits CTS1 and CTS0 bits DF1 and DF0 bits GT, GOC, and GSC = 000b PR bit = 1 G1TPRj register = n G1FS register: FSCj bit = 1 G1FE register: IFEj bit = 1 Refer to the figure Register Settings for Time Measurement Function End
Time measurement trigger select bits Digital filter select bits Gate function not used Prescaler function used If the setting value is n (n = 00h to FFh), the base timer value is stored to the G1TMj register every time a trigger input is counted n+1 times (1) Selects time measurement function Channel j's function enabled
j = 6, 7 NOTE: 1. After the PR bit in the G1TMCRj register is changed from 0 (prescaler function not used) to 1 (prescaler function used), the first time measurement may be performed when a trigger input is counted n times.
Figure 22.21
Register Settings for Prescaler Function
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
Input to the INPC1_i pin
"H" "L" FFFFh
Base timer 1
0000h Count source of base timer Base timer value Read value from the G1BT register Internal trigger signal Prescaler(1) G1TMi register TM1iR bit in the IIOkIR register 1 0 "H" "L"
0 2 m+1 1 0 2 m+12 m-1 m m+1 m+2 m+3 m+4 m+5 m+6 m+7 m+8 m+9 m+10 m+11 m+12 m+13 FFFF
m
m+1
m+2
m+3
m+4
m+5
m+6
m+7
m+8
m+9
m+10 m+11 m+12 m+13
FFFF
Set to 0 by a program
When i = 6, k = 10 and when i = 7, k = 4 The above applies under the following conditions: - The G1TPRi register is set to 02h - G1TMCRi register; bits CTS1 and CTS0 are set to 01b (rising edge is selected for time measurement trigger) the PR bit is set to 1 (prescaler function used) NOTE: 1. This applies to the 2nd or later prescaler cycle after the PR bit is set to 1.
Figure 22.22
Prescaler Function Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
22.2.2
Gate Function
With the gate function, trigger inputs are ignored for a specific period of time. After a time measurement is performed by the first trigger input, the subsequent trigger inputs are all ignored. Thereafter, one trigger input is accepted every time either of the following conditions is met: * Base timer value matches the G1POk register value (k = 4, 5) (Waveform generation function is used). The G1PO4 register is used to control the gate function in channel 6. The G1PO5 register is used to control the gate function in channel 7. * Set the GSC bit in the G1TMCRj register to 1. (j = 6, 7) The gate function is available in channel 6 and channel 7. Figure 22.23 shows register settings. Figure 22.24 shows an example of gate function operation.
Start Refer to the figure Register Settings for Time Measurement Function G1TMCRj register: bits CTS1 and CTS0 bits DF1 and DF0 GT bit = 1 GOC bit GSC bit = 0 PR bit = 0 Time measurement trigger select bits Digital filter select bits Gate function used Gate release bit 1 Gate release bit 2 Prescaler function not used
When the GOC bit in the G1TMCRj register is set to 1 (Gate function is disabled by matching the base timer and the G1POq register) G1POCRq register = 00h G1POq register = n G1FS register: FSCq bit = 0 G1FE register: IFEq bit = 1 Initialize G1POCRq register Set the timing to disable gate function (n = 0000h to FFFFh) Select waveform generation function Channel q's function enabled
G1FS register: FSCj bit = 1 G1FE register: IFEj bit = 1 Refer to the figure Register Settings for Time Measurement Function End
Select time measurement function Channel j's function enabled
When j=6, q=4 and when j=7, q=5
Figure 22.23
Register Settings for Gate Function
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Time Measurement Function)
This trigger input is ignored due to the gate function Input to the INPC1_i pin "H" "L" FFFFh Base timer 1
0000h Count source of base timer Base timer value Read value from the G1BT register Internal trigger signal IFEi bit in the G1FE register Gate control signal G1TMi register TM1iR bit in the IIOkIR register 1 0 "H" "L" "H" "L" "H" "L"
m-8 m+3 m-9 m-8 m-7 m-6 m-5 m-4 m-3 m-2 m-1
Match m m+1 m+2 m+3 m+4 FFFF
m-10
m-9
m-8
m-7
m-6
m-5
m-4
m-3
m-2
m-1
m
m+1
m+2
m+3
m+4
FFFF
Set to 0 by a program
When i = 6, k = 10 and q = 4 When i = 7, k = 4 and q = 5 m: Setting value of the G1POq register (m = 0000h to FFFFh) The above applies under the following conditions: - G1TMCRi register: bits CTS1 and CTS0 are set to 01b (rising edge is selected for time measurement trigger) the GT bit is set to 1 (gate function used) the GOC bit is set to 1 (gate function is disabled by matching the base timer and the G1POq register)
Figure 22.24
Gate Function Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3
Waveform Generation Function (Output Compare)
Waveform generation function outputs a pulse when the base timer value matches the GiPOj register (i = 1, 2; j = 0 to 7). Group 1 and group 2 have waveform generation function. The waveform generation function has the following six modes: * Single-phase waveform output mode (Group 1 and group 2) * Phase-delayed waveform output mode (Group 1 and group 2) * Set/reset (SR) waveform output mode (Group 1 and group 2) * Bit modulation PWM output mode (Group 2) * Real-time port output mode (Group 2) * Parallel real-time port output mode (Group 2) Table 22.6 lists pin settings for the waveform generating function. Figures 22.25 and 22.26 show register settings.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
Table 22.6
Port P6_4 P7_0(3) P7_0(3) P7_1(3) P7_1(3) P7_3 P7_4 P7_5 P7_6 P7_7 P8_1 P9_2 P11_0(2) P11_1(2) P11_2(2) P11_3(2) P13_0(2) P13_1(2) P13_2(2) P13_3(2) P13_4(2) P13_5(2) P13_6(2) P13_7(2) P14_0(2) P14_1(2) P14_2(2) P14_3(2)
Pin Settings for Waveform Generation Function
Bit Setting Function OUTC2_1 OUTC1_6 OUTC2_0 OUTC1_7 OUTC2_2 OUTC1_0 OUTC1_1 OUTC1_2 OUTC1_3 OUTC1_4 OUTC1_5 OUTC2_0 OUTC1_0 OUTC1_1 OUTC1_2 OUTC1_3 OUTC2_4 OUTC2_5 OUTC2_6 OUTC2_3 OUTC2_0 OUTC2_2 OUTC2_1 OUTC2_7 OUTC1_4 OUTC1_5 OUTC1_6 OUTC1_7 PSE1 Register PSD1 Register PSC, PSC2 Registers - PSC_0 = 1 PSC_0 = 1 PSC_1 = 1 PSC_1 = 1 PSC_3 = 1 PSC_4 = 1 PSC_5 = 0 PSC_6 = 0 - PSC2_1 = 1 - - - - - - - - - - - - - - - - - PSL0 to PSL3, PSL5, PSL7 Registers PSL0_4 = 1 PSL1_0 = 0 PSL1_0 = 0 PSL1_1 = 0 PSL1_1 = 0 PSL1_3 = 0 PSL1_4 = 0 PSL1_5 = 1 PSL1_6 = 0 PSL1_7 = 1 PSL2_1 = 1 PSL3_2 = 1 PSL5_0 = 0 PSL5_1 = 0 PSL5_2 = 0 PSL5_3 = 0 PSL7_0 = 0 PSL7_1 = 0 PSL7_2 = 0 PSL7_3 = 0 PSL7_4 = 0 PSL7_5 = 0 PSL7_6 = 0 PSL7_7 = 0 - - - - PS0 to PS3, PS5, PS7, PS8 Registers(1)(4) PS0_4 = 1 PS1_0 = 1 PS1_0 = 1 PS1_1 = 1 PS1_1 = 1 PS1_3 = 1 PS1_4 = 1 PS1_5 = 1 PS1_6 = 1 PS1_7 = 1 PS2_1 = 1 PS3_2 = 1 PS5_0 = 1 PS5_1 = 1 PS5_2 = 1 PS5_3 = 1 PS7_0 = 1 PS7_1 = 1 PS7_2 = 1 PS7_3 = 1 PS7_4 = 1 PS7_5 = 1 PS7_6 = 1 PS7_7 = 1 PS8_0 = 1 PS8_1 = 1 PS8_2 = 1 PS8_3 = 1
- PSE1_0 = 0 - PSE1_1 = 0 - - - - PSE1_6 = 0 - - - - - - - - - - - - - - - - - - -
- PSD1_0 = 1 PSD1_0 = 0 PSD1_1 = 1 PSD1_1 = 0 - PSD1_4 = 0 - PSD1_6 = 1 PSD1_7 = 0 PSD2_1 = 0 - - - - - - - - - - - - - - - - -
NOTES: 1. Set registers PS0 to PS3, PS5, PS7, and PS8 after setting the other registers. 2. This port is provided in the 144-pin package only. 3. P7_0 and P7_1 are N-channel open drain output ports. 4. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
Start
I flag = 0 IIOkIE register: PO1jE bit = 0 G2BCR0 register = 01111111b BTSR register = 00h G2BCR0 register = 00h G1BCR0 register: bits BCK1 and BCK0 G1BCR0 register: bits DIV4 to DIV0 G1BCR0 register: IT bit G1BCR1 register: bits RST2 and RST1 G1BCR1 register: BTS bit = 0 G1BCR1 register: bits UD1 and UD0 G1POCRj register: bits MOD2 and MOD0 IVL bit RLD bit INV bit G1POj register G1FS register: FSCj bit = 0 G1FE register: IFEj bit = 1
Interrupt disabled Waveform generation function interrupt disabled
Reset the BTSR register
Count source select bits Count source divide ratio select bits Base timer interrupt generation timing select bit Base timer reset source select bits Base timer reset Counter increment/decrement control bits Operating mode select bits Output level select bit G1POj register value reload timing select bit Inverted output function select bit Set output timing Waveform generation function selected Channel j's function enabled
Wait time (2 or more fBT1 clock cycles) < When interrupt is used > IIOkIR register = 00h(1) IIOkIE register: IRLT bit = 1 IIOkIE register: PO1jE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 Interrupt not requested Interrupt request is used for interrupt Waveform generation function interrupt request enabled Interrupt priority level select bit Interrupt not requested Do not set at the same time. Set the PO1jE bit to 1 after setting the IRLT bit to 1.
G1BCR1 register: BTS bit = 1 Pin setting for waveform generation I flag = 1 End
Base timer count starts
Interrupt enabled
j = 0 to 7; k = 0 to 4, 8 to 10 NOTE: 1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated in the same register (Interrupt does not occur).
Figure 22.25
Register Settings for Waveform Generation Function (Group 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
Start initial setting
I flag = 0 IIOkIE register: PO2jE bit = 0 G2BCR0 register = 01111111b BTSR register = 00h G2BCR0 register = 00h G2BCR0 register: bits BCK1 and BCK0 G2BCR0 register: bits DIV4 to DIV0 G2BCR0 register: IT bit G2BCR1 register: bits RST2 to RST0 BTS bit = 0 PRP bit G2POCRj register: bits MOD2 to MOD0 PRT bit IVL bit RLD bit RTP bit INV bit G2POj register < When using real-time port > G2RTP register: RTPj bit
Interrupt disabled Waveform generation function interrupt disabled
Reset the BTSR register
Count source select bits Count source divide ratio select bits Base timer interrupt generation timing select bit Base timer reset source select bits Base timer reset Parallel real-time port function select bit Operating mode select bits Parallel real-time port output trigger select bit Output level select bit G2POj register value reload timing select bit Real-time port function select bit Inverted output function select bit Set output timing
Select real-time port output level
G2FE: IFEj bit = 1 Wait time (2 or more fBT1 clock cycles) < When interrupt is used > IIOkIR register = 00h(1) IIOkIE register: IRLT bit = 1 IIOkIE register: PO2jE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0
Channel j's function enabled
Interrupt not requested Interrupt request is used for interrupt Waveform generation function interrupt request enabled Interrupt priority level select bit Interrupt not requested Do not set at the same time. Set the PO2jE bit to 1 after setting the IRLT bit to 1.
G2BCR1 register: BTS bit = 1 Pin setting for waveform generation I flag = 1
Base timer count starts
Interrupt enabled
End j = 0 to 7; k = 3, 5 to 11 NOTE: 1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated in the same register (Interrupt does not occur).
Figure 22.26
Register Settings for Waveform Generation Function (Group 2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.1
Single-Phase Waveform Output Mode (Group 1 and Group 2)
The OUTCi_j pin outputs "H" when the base timer value matches the GiPOj register value (i = 1, 2; j = 0 to 7), and outputs "L" when the base timer is reset. Table 22.7 lists specifications of single-phase waveform output mode. Figure 22.27 shows an example of single-phase waveform output mode operation. Table 22.7 Single-Phase Waveform Output Mode Specifications
Item Waveform generation channel OUTCi_ j pin Output waveform(1) Group 1 and 2: channels 0 to 7 Pulse output * Base timer is not reset: -The INV bit in the GiPOCRj register is set to 0 (output not inverted) -Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode) Cycle: "L" width: "H" width: 65536 fBTi m fBTi 65536 - m fBTi Specification
m: setting value of the GiPOj register: 0000h to FFFFh * Base timer is reset when base timer value matches the GiPO0 register value: -The INV bit in the GiPOCRj register is set to 0 (output not inverted) -Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode) Cycle: "L" width: "H" width: p+2 fBTi m fBTi p+2-m fBTi
m: setting value of the GiPOj register (0000h to FFFFh) p: setting value of the GiPO0 register (0001h to FFFDh) If m p + 2, the output level is fixed to "L" Waveform output start condition Waveform output stop condition Set both the BTS bit in the GiBCR1 register and the IFEj bit in the GiFE register to 1 Set either the BTS or IFEj bit to 0
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer value matches the GiPOj register value. The POijR bit in the IIOkIR register (k = 0 to 11) becomes 1 (interrupt requested) when an interrupt request is generated. (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Initial value set function: Set the initial output level when waveform output is started (determined by the IVL bit in the GiPOCRj register) * Inverted output function: Output the inverted waveform level (determined by the INV bit in the GiPOCRj register)
NOTE: 1. When the INV bit in the GiPOCRj register is set to 1 (output inverted), the "L" width and the "H" width are inversed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
(1) When the base timer is not reset
FFFFh
Base timer i m
0000h Count source of base timer
Match
Base timer value Read value from the GiBT register
0000
0001
0002 0002 m fBTi
m m
m+1
m+2 m+2
FFFE FFFF 0000
0001
0002
0003 0003
0000
0001
m+1
FFFE FFFF 0000 65536 - m fBTi
0001
0002
OUTCi_ j pin
"H" "L" 1 0
Set to 0 by a program
POijR bit in registers IIO0IR to IIO11IR
i = 1, 2; j = 0 to 7 m: Setting value of the GiPOj register (0000h to FFFFh) The above applies under the following conditions: - Group 1: In the G1BCR1 register, bits RST2 and RST1 are set to 00b and bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: In the G2BCR1 register, bits RST2 to RST0 are set to 000b (Base timer is not reset by matching the G2PO0 register) - In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted)
(2) When the base timer is reset by matching the GiPO0 register
p+1
Base timer i m
0000h Count source of base timer
Match Reset m+1 m m fBTi m+2 m+2 p p p+2-m fBTi p+1 0000 0001 0002 0003 0003
Base timer value Read value from the GiBT register
0000
0001
0002 0002
m
0000
0001
m+1
p+1
0000
0001
0002
OUTCi_j pin POijR bit in the IIOkIR register
"H" "L" 1 0
Set to 0 by a program
i = 1, 2; j = 1 to 7; k = 0 to 5, 7 to 11 m: Setting value of the GiPOj register (0000h to FFFFh); p: Setting value of the GiPO0 register (0001h to FFFDh) The above applies under the following conditions: - Group 1: In the G1BCR1 register, bits RST2 and RST1 are set to 01b, and bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: In the G2BCR1 register, bits RST2 to RST0 are set to 010b (Base timer is reset by matching the G2PO0 register) - In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted) -mFigure 22.27
Single-Phase Waveform Output Mode Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.2
Phase-Delayed Waveform Output Mode (Group 1 and Group 2)
Output level from the OUTCi_j pin is inverted every time the base timer value matches the GiPOj register value (i = 1, 2; j = 0 to 7). Table 22.8 lists specifications of phase-delayed waveform output mode. Figure 22.28 shows an example of phase-delayed waveform output mode operation. Table 22.8 Phase-Delayed Waveform Output Mode Specifications
Item Waveform generation channel OUTCi_ j pin Output waveform Group 1 and 2: channels 0 to 7 Pulse output * Base timer is not reset: -Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode) Cycle: "H" and "L" widths: 65536 x 2 fBTi 65536 fBTi Specification
* Base timer is reset when base timer value matches the GiPO0 register value: -Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode) Cycle: "H" and "L" widths: 2 (p + 2) fBTi p+2 fBTi
p: setting value of the GiPO0 register (0001h to FFFDh) If GiPOq register value (q = 1 to 7) (0000h to FFFFh) p + 2, the output level is not inverted Waveform output start condition Waveform output stop condition Set both the BTS bit in the GiBCR1 register and the IFEj bit in the GiFE register to 1 Set either the BTS or IFEj bit to 0
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer value matches the GiPOj register value. The POijR bit in the IIOkIR register (k = 0 to 11) becomes 1 (interrupt requested) when an interrupt request is generated. (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Initial value set function: Set the initial output level when waveform output is started (determined by the IVL bit in the GiPOCRj register) * Inverted output function: Output the inverted waveform level (determined by the INV bit in the GiPOCRj register)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
(1) When the base timer is not reset
FFFFh Base timer i m 0000h Count source of base timer
Match Match m+1 m m+2 m+2 FFFF 0000 FFFF 0000 65536 fBTi m m m+1 m+2 m+2 FFFF 0000 FFFF 0000 65536 fBTi Match m m m+1 m+1
Base timer value Read value from the GiBT register
m
m+1
m+1
OUTCi_ j pin POijR bit in registers IIO0IR to IIO11IR
"H" "L" 1 0
Set to 0 by a program
i = 1, 2; j = 0 to 7
m: Setting value of the GiPOj register (0000h to FFFFh)
The above applies under the following conditions: - Group 1: G1BCR1 register; bits RST2 and RST1 are set to 00b (Base timer is not reset by matching the G1PO0 register) bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: Bits RST2 to RST0 in the G2BCR1 register are set to 000b (Base timer is not reset by matching the G2PO0 register) - In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted)
(2) When the base timer is reset by matching the GiPO0 register
p+1 Base timer i m 0000h Count source of base timer
Match Reset m+1 m m+1 p p p+1 0000 0000 Match m m m+1 m+1 p p p+1 Reset 0000 0000 Match m m m+1 m+1
Base timer value Read value from the GiBT register
m
p+1
p+1
p+2 fBTi
p+2 fBTi
OUTCi_j pin POijR bit in the IIOkIR register
"H" "L" 1 0
Set to 0 by a program
i = 1, 2; j = 1 to 7; k = 0 to 5, 7 to 11 m: Setting value of the GiPOj register (0000h to FFFFh); p: Setting value of the GiPO0 register (0001h to FFFDh) The above applies under the following conditions: - Group 1: G1BCR1 register; bits RST2 and RST1 are set to 01b (Base timer is reset by matching the G1PO0 register) bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: Bits RST2 to RST0 in the G2BCR1 register are set to 010b (Base timer is reset by matching the G2PO0 register) - In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted) -mFigure 22.28
Phase-Delayed Waveform Output Mode Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.3
Set/Reset (SR) Waveform Output Mode (Group 1 and Group 2)
The OUTCi_j pin outputs "H" when the base timer value matches the GiPOj register value (i = 1, 2; j = 0, 2, 4, 6), and outputs "L" when the base timer value matches the GiPOk register value (k = j + 1) or when the base timer is reset. Table 22.9 lists specifications of SR waveform output mode. Figure 22.29 shows an example of SR waveform output mode operation. Table 22.9 SR Waveform Output Mode Specifications
Item Waveform generation OUTCi_j pin Output waveform(1)(2) channel(1) Pulse output * Base timer is not reset: -The INV bit in the GiPOCRj register is set to 0 (output not inverted) -Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode) (1) m < n "H" width: (2) m n "H" width: 65536 - m fBTi "L" width : m fBTi n-m fBTi "L" width : 65536 - n + m fBTi Specification Group 1 and 2: channels 0, 2, 4, 6
m: setting value of the GiPOj register (0000h to FFFFh) n: setting value of the GiPOk register (0000h to FFFFh) * Base timer is reset when base timer value matches the GiPO0 register value(1): -The INV bit in the GiPOCRj register is set to 0 (output not inverted) -Bits UD1 and UD0 in G1BCR1 register are set to 00b (counter increment mode) (1) m < n < p + 2 "H" width: n-m fBTi p+2-m fBTi "L" width : p+2-n+m fBTi m fBTi
(2) m < p + 2 n "H" width: "L" width :
(3) m p + 2, the output level is fixed to "L" m: setting value of the GiPOq register (q = 2, 4, 6) (0000h to FFFFh) n: setting value of the GiPOk register (0000h to FFFFh) p: setting value of the GiPO0 register (0001h to FFFDh) Waveform output start condition Waveform output stop condition Set both the BTS bit in the GiBCR1 register and the IFEj bit in the GiFE register to 1 Set either the BTS or IFEj bit to 0
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer value matches the GiPOj register value. The POirR bit in the IIOsIR register becomes 1 (interrupt requested) when an interrupt request is generated. (r = 0 to 7; s = 0 to 11) (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Initial value set function: Set the initial output level when waveform output is started (determined by the IVL bit in the GiPOCRj register) * Inverted output function: Output the inverted waveform level (determined by the INV bit in the GiPOCRj register)
NOTES: 1. If the base timer is reset when the base timer value matches the GiPO0 register, the SR waveform generation function in the channel 0 can not be used. 2. When the INV bit in the GiPOCRj register is set to 1 (output inverted), the "L" width and the "H" width are inversed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
(1) When the base timer is not reset
FFFFh Base timer i n m 0000h Count source of base timer
Match Match m+1 m m+2 m+2 n-m fBTi n n n+1 n+2 n+2 FFFF 0000 FFFF 0000 65536 - n + m fBTi Match m m m+1 m+2 m+2
Base timer value Read value from the GiBT register
m-1 m-1
m
m+1
n+1
m+1
OUTCi_j pin POijR bit in the IIOqIR register (q = 1 to 3, 6, 7, 9 to 11) POikR bit in the IIOqIR register (q = 0, 3 to 5, 8 to 10)
"H" "L" 1 0 1 0
Set to 0 by a program Set to 0 by a program
i = 1, 2; j = 0, 2, 4, 6; k = j + 1 m: Setting value of the GiPOj register (0000h to FFFFh), n: Setting value of the GiPOk register (0000h to FFFFh) The above applies under the following conditions: - Group 1: In the G1BCR1 register, bits RST2 and RST1 bit are set to 00b and bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: Bits RST2 to RST0 in the G2BCR1 register are set to 000b (base timer is not reset by matching the G2PO0 register) - In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted) -m(2) When the base timer is reset by matching the GiPO0 register
p+1 Base timer i n m 0000h Count source of base timer
Match Match m+1 m m+2 m+2 n-m fBTi n n n+1 n+1 p p p+1 Reset 0000 0000 Match m m m+1 m+2 m+2
Base timer value Read value from the GiBT register
m-1 m-1
m
m+1
p+1
m+1
OUTCi_j pin POijR bit in the IIOqIR register (q = 1, 2, 7, 9 to 11) POikR bit in the IIOqIR register (q = 0, 3, 4, 8 to 10)
"H" "L" 1 0 1 0
P+2-n+m fBTi
Set to 0 by a program
Set to 0 by a program
i = 1, 2; j = 2, 4, 6; k = j + 1 m: Setting value of the GiPOj register (0000h to FFFFh), n: Setting value of the GiPOk register (0000h to FFFFh) p: Setting value of the GiPO0 register (0001h to FFFDh) The above applies under the following conditions: - Group 1: In the G1BCR1 register, bits RST2 and RST1 are set to 01b and bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: Bits RST2 to RST0 in the G2BCR1 register are set to 010b (base timer is reset by matching the G2PO0 register) - In the GiPOCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted) -mFigure 22.29
SR Waveform Output Mode Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.4
Bit Modulation PWM Output Mode (Group 2)
In bit modulation PWM output mode, 16-bit PWM duty ratio can be achieved with a collection of 6-bit PWM pulses. A series of 1024 pulses whose "L" widths are specified with 6-bit PWM, is repeatedly output. The six high-order bits in the G2POi register (i = 0 to 7) determine the base "L" width. The ten low-order bits determine the number of pulses (modulated pulses) whose "L" widths are extended by one fBT2 clock cycle. Table 22.10 lists specifications of bit modulation PWM output mode. Table 22.11 lists the number of modulated pulses and their locations. Figure 22.30 shows an example of bit modulation PWM output mode operation. Table 22.10 Specifications of Bit Modulation PWM Output Mode
Item Waveform generation channels OUTC2_i pin Output waveform(2)(3) Group 2: channels 0 to Pulse output PWM cycle: Repeat cycle: "L" width: Average "L" width: 64 fBT2 65536 fBT2 n+1 fBT2 1 fBT2 (=t) (= 64 fBT2 x 1024 ) n fBT2 ) : for (1024 - m) pulses 7(1) Specification
: for m pulses, x (n + m 1024
n: setting value of the six high-order bits in the G2POi register (00h to 3Fh) m: setting value of the ten low-order bits in the G2POi register (000h to 3FFh) Waveform output start condition Waveform output stop condition Set both the BTS bit in the G2BCR1 register and the IFEi bit in the G2FE register to 1 Set either the BTS or IFEi bit to 0
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer value matches the G2POi register value. The PO2iR bit in the IIOkIR register (k = 3, 5 to 11) becomes 1 (interrupt requested) when an interrupt request is generated. (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Initial value set function: Set the initial output level when waveform output is started (determined by the IVL bit in the G2POCRi register) * Inverted output function: Output the inverted waveform level (determined by the INV bit in the G2POCRi register)
NOTES: 1. Channels 0 to 7 are provided in the 144-pin package. Channels 0 to 2 are provided in the 100-pin package. 2. Set bits RST2 to RST0 in the G2BCR1 register to 000b to use bit modulation PWM mode. 3. When the INV bit in the G2POCRi register is set to 1 (output inverted), the "L" width and the "H" width are inversed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.11
22. Intelligent I/O (Waveform Generation Function)
Number of Modulated Pulses and Locations
Location none 512t 256t, 768t 128t, 384t, 640t, 896t 64t, 192t, 320t, 448t, 576t, 704t, 832t, 960t ... 1t, 3t, 5t, 7t, ... 1019t, 1021t, 1023t 0 1 2 4 8 ... 512
Ten low-order bits in the G2POi register Number of Pulses 00 0000 0000b 00 0000 0001b 00 0000 0010b 00 0000 0100b 00 0000 1000b ... 10 0000 0000b
Base width n = 0 to 63 (3Fh) b15 G2POi register
Number of modulated pulses m = 0 to 1023 (3FFh) b0
b10 b9
Repeat cycle
6 low-order bits in the base timer
3Fh n 00h
n 1t 2t 3t 511t 512t 513t 514t 1022t 1023t 1024t
OUTC2_i pin
"L" width of m out of 1024 pulses is extended by one fBT2 clock cycle
6 low-order bits in the base timer
3Fh n 00h
fBT2
Minimum resolution bit width
Internal signal
OUTC2_i pin
n inverse
n+1 inverse
"L" level
"L" level
PO2iR bit
i = 0 to 7 PO2iR bit: Bit in the register IIO3IR to IIO11IR The above applies under the following conditions: - In the G2POCRj register, the IVL bit is set to 0 ("L" output) and the INV bit is set to 0 (output not inverted) -m=1 Set to 0 by a program Set to 0 by a program
Figure 22.30
Bit Modulation PWM Output Mode Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.5
Real-Time Port Output Mode (Group 2)
The OUTC2_i pin (i = 0 to 7) outputs the value of the RTPi bit in the G2RTP register when the base timer value matches the G2POi register. To use real-time output mode, set the RTP bit in the G2POCRi register to 1 and the PRT bit to 0 in the channel used for this mode. Also, set the PRP bit in the G2BCR1 register to 0. Table 22.12 lists specifications of real-time port output mode. Figure 22.31 shows a block diagram. Figure 22.32 shows an example of real-time port output mode operation. Table 22.12 Specifications of Real-Time Port Output Mode
Item Waveform generation channels OUTC2_i pin Waveform output start condition Waveform output stop condition Group 2: channels 0 to Real-time port output Set both the BTS bit in the G2BCR1 register and the IFEi bit in the G2FE register to 1 Set either the BTS or IFEi bit to 0 7(1) Specification
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer value matches the G2POi register value. The PO2iR bit in the IIOkIR register (k = 3, 5 to 11) becomes 1 (interrupt requested) when an interrupt request is generated. (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Initial value set function: Set the initial output level when waveform output is started (determined by the IVL bit in the G2POCRi register)
NOTE: 1. Channels 0 to 7 are provided in the 144-pin package. Channels 0 to 2 are provided in the 100-pin package.
Base timer G2RTP register RTP0 G2PO0 register IVL bit in the G2POCR0
Real-time port output
S DQ R
OUTC2_0
RTP6 G2PO6 register
IVL bit in the G2POCR6
S DQ R
OUTC2_6
RTP7 G2PO7 register
IVL bit in the G2POCR7
S DQ R
OUTC2_7
Figure 22.31
Real-Time Port Output Function Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
(1) When the base timer is not reset
FFFFh Base timer 2 n m 0000h Count source of base timer
Match Match m+1 m m 1 65536 + n - m fBT2 m+1 FFFF 0000 FFFF 0000 n 0 1 n n n+1 n+1 FFFF 0000 FFFF 0000
Base timer value Read value from the G2BT register G2POi register RTPi bit in the G2RTP register
m
OUTC2_i pin PO2iR bit in the IIOkIR register
"H" "L" 1 0
Set to 0 by a program
i = 0 to 7; k = 3, 5 to 11 m, n: Setting value of the G2POj register (0000h to FFFFh) The above applies under the following conditions: - Bits RST2 to RST0 in the G2BCR1 register are set to 000b (base timer is not reset by matching the G2PO0 register) - In the G2POCRj register, the IVL bit is set to 0 ("L" output) and the RLD bit is set to 1 (reload when the base timer is reset)
(2) When the base timer is reset by matching the G2PO0 register
p+1 Base timer 2 m 0000h Count source of base timer
Match Reset m+1 m m 1 p+2+n-m fBT2 m+1 p p p+1 0000 0000 n 0 1 Match n n n+1 n+1 p p p+1 Reset 0000 0000
n
Base timer value Read value from the G2BT register G2POi register RTPi bit in the G2RTP register
m
p+1
p+1
OUTC2_i pin PO2iR bit in the IIOkIR register
"H" "L" 1 0
Set to 0 by a program
i = 1 to 7; k = 3, 5, 7 to 11 m, n: Setting value of the G2POi register (0000h to FFFFh); p: Setting value of the G2PO0 register (0001h to FFFDh) The above applies under the following conditions: - Bits RST2 to RST0 in the G2BCR1 register are set to 010b (base timer is reset by matching the G2PO0 register) - In the G2POCRi register, the IVL bit is set to 0 ("L" output) and the RLD bit is set to 1 (reload when the base timer is reset) - m< nFigure 22.32
Real-Time Port Output Mode Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.6
Parallel Real-Time Port Output Mode (Group 2)
In parallel real-time port output mode, all of the channels which the RTP bit in the G2POCRi register (i = 0 to 7) is set to 1, perform the parallel real-time port output. The value set in the G2RTP register is output from the OUTC2_i pin in these channels, when the base timer value matches any of the G2POi register which the RTP bit is set to 1. Real-time port output and parallel real-time port output cannot be used in the same group. To use parallel real-time port output, set the RTP bit to 1 and the PRT bit to 1 in the channel used for parallel real-time port output. Also, set the PRP bit in the G2BCR1 register to 1. Table 22.13 lists specifications of parallel real-time port output mode. Figure 22.33 shows a block diagram. Figure 22.34 shows an example of parallel real-time port output mode operation. Table 22.13 Specifications of parallel real-time port output mode
Item Waveform generation channels OUTC2_i pin Waveform output start condition Waveform output stop condition Group 2: channels 0 to Real-time port output Set both the BTS bit in the G2BCR1 register and the IFEi bit in the G2FE register to 1 Set either the BTS or IFEi bit to 0 7(1) Specification
Interrupt request generation timing An interrupt request is generated at the second clock cycle after the base timer value matches the G2POi register value. The PO2iR bit in the IIOkIR register (k = 3, 5 to 11) becomes 1 (interrupt requested) when an interrupt request is generated. (See Figure 11.18 IIO0IR to IIO11IR Registers) Selectable function * Initial value set function: Set the initial output level when waveform output is started (determined by the IVL bit in the G2POCRi register)
NOTE: 1. Channels 0 to 7 are provided in the 144-pin package. Channels 0 to 2 are provided in the 100-pin package.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
Base timer
G2RTP register IVL bit in the G2POCR0 RTP0
S DQ R
Real-time port output
OUTC2_0
G2PO0 register G2PO1 register G2PO2 register G2PO3 register G2PO4 register RTP3 G2PO5 register G2PO6 register G2PO7 register RTP5 RTP2 RTP1
IVL bit in the G2POCR1
S DQ R
OUTC2_1
IVL bit in the G2POCR2
S DQ R
OUTC2_2
IVL bit in the G2POCR3
S DQ R
OUTC2_3
IVL bit in the G2POCR4 RTP4 IVL bit in the G2POCR5
S DQ R
OUTC2_4
S DQ R
OUTC2_5
IVL bit in the G2POCR6 RTP6 IVL bit in the G2POCR7 RTP7
S DQ R
OUTC2_6
S DQ R
OUTC2_7
Figure 22.33
Parallel Real-Time Port Output Function Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
FFFFh p Base timer 2 n m 0000h Count source of base timer
Match Match m+1 m m+1 n n n+1 n+1 Match p p p+1 p+1 FFFF 0000 FFFF 0000
Base timer value Read value from the G2BT register G2RTP register "H" "L" "H" "L" "H" "L" "H" "L" 1 0 1 0 1 0 X8h
m
X1h
X3h
X6h
XCh
OUTC2_0 pin
OUTC2_1 pin
OUTC2_2 pin
OUTC2_3 pin
PO20R bit
Set to 0 by a program
PO21R bit
Set to 0 by a program
PO22R bit
m: Setting value of the G2PO0 register (0000h to FFFFh) n: Setting value of the G2PO1 register (0000h to FFFFh) p: Setting value of the G2PO2 register (0000h to FFFFh) PO20R, PO21R, and PO22R: Bits in registers IIO5IR to IIO7IR The above applies under the following conditions: - The IVL bit in the G2POCRi (i = 0 to 3) register is set to 0 ("L" output) - Bits RST2 to RST0 in the G2BCR1 register are set to 000b (base timer is not reset by matching the G2PO0 register) -mFigure 22.34
Parallel Real-Time Port Output Mode Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Waveform Generation Function)
22.3.7
GiPOj Register Value Reload Timing Select Function (i = 1, 2; j = 0 to 7)
The RLD bit in the GiPOCRj register determines whether the GiPOj register value is reloaded to the internal register when the value is written, or when the base timer is reset. Figure 22.35 shows an operation example.
(1) When GiPOj register value is reloaded to the internal register at the base timer reset (RLD bit in the GiPOCRj register = 1)
FFFFh Base timer i n m 0000h Count source of base timer
Match Match m+1 m m+1 n n FFFF 0000 FFFF 0000 n n n+1 n+1
Base timer value Read value from the GiBT register GiPOj register
m
m 65536 + n - m fBTi
n
OUTCi_ j pin
"H" "L"
Set to 0 by a program
POijR bit in the IIO0IR to 1 IIO11IR register 0
(2) When GiPOj register value is reloaded to the internal register when written (RLD bit in the GiPOCRj register = 0)
FFFFh Base timer i n m 0000h Count source of base timer
Match Match m+1 m m+1 n n n+1 n+1 FFFF 0000 FFFF 0000 Match m m m+1 m+1 Match n n n+1 n+1
Base timer value Read value from the GiBT register GiPOj register
m
m n-m fBTi
n
m 65536 - n + m fBTi
n
OUTCi_ j pin
"H" "L"
Set to 0 by a program
POijR bit in the IIO0IR to 1 IIO11IR register 0
i = 1, 2; j = 0 to 7; m: Setting value of the GiPOj register (0000h to FFFFh); n: Setting value of the GiPO0 register (0000h to FFFFh) The above applies under the following conditions: - Group 1: G1BCR1 register; bits RST2 and RST1 are set to 00b (base timer is not reset by matching the G1PO0 register) bits UD1 and UD0 are set to 00b (counter increment mode) - Group 2: Bits RST2 and RST0 in the G2BCR1 register are set to 000b (base timer is not reset by matching the G2PO0 register) - GiPOCRj register: bits MOD2 to MOD0 are set to 010b (phase-delayed waveform output mode), the IVL bit is set to 0 ("L" output), and the INV bit is set to 0 (output not inverted) -mFigure 22.35
GiPOj Register Value Reload Timing Select Function Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
22.4
Group 0 and Group 1 Communication Function
In the group 0 communication function, clock synchronous mode or HDLC data processing mode is available. In the group 1 communication function, clock synchronous mode, clock asynchronous (UART) mode, or HDLC data processing mode is available. Figure 22.36 shows a block diagram of group 0 communication function. Figure 22.37 shows a block diagram of group 1 communication function. Figures 22.38 to 22.46 show registers associated with the communication function.
Transmission
G0TB Transmit shift register Latch Bit insert circuit CRC calculation circuit TXSL 0 1
Polarity invert Shift register G0TO
Transmit data output from ISTXD0 pin
Clock input to ISCLK0 pin
CCS1 and CCS0 f101 f2n10 f811 0 1 CKDIR
Clock Control
Transmission control circuit
Serial clock output from ISCLK0 pin Transmit interrupt request (SIO0TR) HDLC data transmit interrupt request (G0TOR)
Reception
G0RB Receive data input to ISRXD0 pin Polarity invert RXSL 0 1 G0DR Shift register G0RI Shift register Bit delete verifying Receive shift register CRC calculation circuit (SIO0RR) Receive complete interrupt request HDLC data receive Interrupt request (G0RIR)
Comparator G1CMPi G1CMPi G1CMPi G0CMPi
Reception control circuit
G1MSKi G0MSKj
i = 0 to 3
j = 0, 1
CCS1 and CCS0: bits in the CCS register CKDIR: bit in the G0MR register TXSL, RXSL: bits in the G0EMR register SIO0TR, G0TOR: bits in the IIO1IR register SIO0RR, G0RIR: bits in the IIO0IR register
Figure 22.36
Group 0 Communication Function Block Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 368 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Transmission
Stop bit generation circuit G1TB Transmit shift register Start bit generation circuit Latch Bit insert circuit Polarity invert 1 Shift register
Transmit data output from ISTXD1
TXSL 0 CRC circulation circuit
G1TO Serial clock output from ISCLK1 pin Transmit interrupt request (SIO1TR) HDLC transmit interrupt request (G1TOR)
ch1 generation clock ch2 generation clock ch3 generation clock Clock input to ISCLK1 pin
Clock selector
00 f101 f2n10 f811
CCS3 and CCS2
0 1 CKDIR
Clock control
Transmission control circuit
Reception
G1RB Receive data input to ISRXD1 Polarity invert 0 1 RXSL Start bit detection Stop bit verifying Bit delete verifying Receive shift register CRC circulation circuit
G1DR Shift register G1RI Shift register
Comparator G1CMPi G1CMPi G1CMPi G1CMPi
Reception control circuit
Receive interrupt request (SIO1RR) HDLC receive interrupt request (G1RIR)
G1MSKi G1MSKj
i = 0 to 3
j = 0,1
CCS3 and CCS2: bits in the CCS register CKDIR: bit in the G1MR register TXSL, RXSL: bits in the G1EMR register SIO1TR, G1TOR: bits in the IIO3IR register SIO1RR, G1RIR: bits in the IIO2IR register NOTE: 1. After a clock, which is selected in the G1BCR0 register, is supplied to the registers, each register value becomes the after reset value.
Figure 22.37
Group 1 Communication Function Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Communication Clock Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CCS
Bit Symbol CCS0 Group 0 clock select bits CCS1
(1)
Address 00F6h
Bit Name
b1 b0
After Reset XXXX 0000b
Function RW RW
0 0 1 1
0 : Do not set to this value 1 : f1 0 : f2n(2) 1 : f8
RW
CCS2 Group 1 clock select bits CCS3
- (b7-b4)
(1)
b3 b2
0 0 : Clock generated with a waveform generation function 0 1 : f1 1 0 : f2n(2) 1 1 : f8
RW
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. Set the selected clock frequency to 5MHz or lower in the clock synchronous mode. 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
Figure 22.38
CCS Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group 0 SI/O Communication Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol G0MR
Bit Symbol GMD0 Communication mode select bits GMD1 Bit Name
Address 00EDh
Function
b1 b0
After Reset 00h
RW RW
0 1 : Clock synchronous mode 1 1 : HDLC data processing mode Do not set to values other than the above.
RW
CKDIR
- (b5-b3)
Clock select bit
0 : Internal clock 1 : External clock Set to 0 0 : LSB first 1 : MSB first 0 : No data in the G0TB register (TI=1) 1 : Transmit operation is completed (TXEPT=1)
RW
Reserved bits
RW
UFORM
Bit order select bit Transmit interrupt source select bit
RW
IRS
RW
Group 1 SI/O Communication Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G1MR
Bit Symbol GMD0 Communication mode select bits GMD1 Bit Name
Address 012Dh
Function
b1 b0
After Reset 00h
RW RW
0 0 1 1
0 1 0 1
: UART mode : Clock synchronous mode : Do not set to this value : HDLC data processing mode
RW
CKDIR
Clock select bit Stop bit length select bit Parity select bit
0 : Internal clock 1 : External clock 0 : 1 stop bit 1 : 2 stop bits 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : LSB first 1 : MSB first 0 : No data in the G0TB register (TI=1) 1 : Transmit operation is completed (TXEPT=1)
RW
STPS
RW
PRY
RW
PRYE
Parity enable bit
RW
UFORM
Bit order select bit Transmit interrupt source select bit
RW
IRS
RW
Figure 22.39
G0MR and G1MR Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i SI/O Communication Control Register (i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G0CR G1CR
Bit Symbol TI Bit Name GiTB register empty flag
Address 00EFh 012Fh
Function 0 : Data in the GiTB register 1 : No data in the GiTB register 0 : Data in the transmit shift register (during transmission) 1 : No data in the transmit shift register (transmit completed) 0 : No data in the GiRB register 1 : Data in the GiRB register
After Reset 0000 X011b 0000 X011b
RW RO
TXEPT
Transmit shift register empty flag
RO
RI
- (b3)
Receive complete flag Unimplemented. Write 0. Read as undefined value. Transmit enable bit
RO
-
TE
0 : Transmit operation disabled 1 : Transmit operation enabled 0 : Receive operation disabled 1 : Receive operation enabled 0 : Not inverted 1 : Inverted(1) 0 : Not inverted 1 : Inverted(1)
RW
RE
Receive enable bit ISRXD input polarity invert bit ISTXD output polarity invert bit
RW
IPOL
RW
OPOL
RW
NOTE: 1. Set these bits to 1 when using UART mode.
Figure 22.40
G0CR, G1CR Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 372 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i SI/O Expansion Mode Register (i=0, 1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol G0EMR G1EMR
Bit Symbol
- (b0)
Address 00FCh 013Ch
Bit Name Reserved bit Set to 0 0 : Set to 0000h 1 : Set to FFFFh 0 : CRC is not initialized 1 : CRC is initialized(2) Set to 0 0 : ISRXD0 pin 1 : GiRI register 0 : ISTXD0 pin 1 : GiTO register
b7 b6
After Reset 00h 00h
Function RW RW
CRCV
CRC initial value select bit
RW
ACRC
- (b3)
CRC initialize bit
RW
Reserved bit
RW
RXSL
Receive source select bit
RW
TXSL
Transmit destination select bit
RW
CRC0 CRC generation polynomial select bits CRC1
0 0 : X8+X4+X+1 0 1 : Do not set to this value 1 0 : X16+X15+X2+1 1 1 : X16+X12+X5+1
RW
RW
NOTES: 1. Set to 00h except HDLC data processing mode. 2. CRC is initialized when the GiDR register matches the GiCMP3 register.
Group i SI/O Expansion Transmit Control Register (i=0, 1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
00
0000
Symbol G0ETC G1ETC
Bit Symbol
- (b3-b0)
Address 00FFh 013Fh
Bit Name Reserved bits Set to 0 0 : Not used 1 : Used Set to 0 0 : "0" is not inserted 1 : "0" is inserted Function
After Reset 0000 0XXXb 0000 0XXXb
RW RW
TCRCE
- (b6-b5)
Transmit CRC enable bit
RW
Reserved bits Transmit bit stuffing "0" insert select bit
RW
TBSF1
RW
NOTE: 1. Set to 00h except HDLC data processing mode.
Figure 22.41
G0EMR, G1EMR, G0ETC, G1ETC Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i SI/O Expansion Receive Control Register (i=0,1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol G0ERC G1ERC
Bit Symbol Bit Name
Address 00FDh 013Dh
Function
After Reset 00h 00h
RW
CMP0E
Data compare function 0 select bit
0 : The GiDR register (receive data register) is not compared with the GiCMP0 register 1 : The GiDR register is compared with the GiCMP0 register 0 : The GiDR register (receive data register) is not compared with the GiCMP1 register 1 : The GiDR register is compared with the GiCMP1 register 0 : The GiDR register (receive data register) is not compared with the GiCMP2 register 1 : The GiDR register is compared with the GiCMP2 register 0 : The GiDR register (receive data register) is not compared with the GiCMP3 register 1 : The GiDR register is compared with the GiCMP3 register (2) 0 : Not used 1 : Used 0 : Receive shift operation disabled 1 : Receive shift operation enabled Set to 0 0 : "0" is not deleted 1 : "0" is deleted
RW
CMP1E
Data compare function 1 select bit
RW
CMP2E
Data compare function 2 select bit
RW
CMP3E
Data compare function 3 select bit
RW
RCRCE
Receive CRC enable bit Receive shift operation enable bit Reserved bit Receive bit stuffing "0" delete select bit
RW
RSHTE
- (b6)
RW
RW
RBSF1
RW
NOTES: 1. The GiERC register is used in HDLC data processing mode. Set the GiERC register to 0010 0000b in clock synchronous mode, set it to 00h in UART mode. 2. When the ACRC bit in the GiEMR register is set to 1 (CRC initialized), set the CMP3E bit to 1.
Figure 22.42
G0ERC, G1ERC Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i SI/O Special Communication Interrupt Determination Register (i=0,1)(1)( 2)
b7 b6 b5 b4 b3 b2 b1 b0
0000
Symbol G0IRF G1IRF
Bit Symbol
- (b3-b0)
Address 00FEh 013Eh
Bit Name Reserved bits Set to 0 Function
After Reset 0000 XXXXb 0000 XXXXb
RW RW
IRF0
Interrupt source determination flag 0
0 : The GiDR register (receive data register) does not match the GiCMP0 register 1 : The GiDR register matches the GiCMP0 register 0 : The GiDR register (receive data register) does not match the G0CMP1 register 1 : The GiDR register matches the GiCMP1 register 0 : The GiDR register (receive data register) does not match the GiCMP2 register 1 : The GiDR register matches the GiCMP2 register 0 : The GiDR register (receive data register) does not match the GiCMP3 register 1 : The GiDR register matches the GiCMP3 register
RW
IRF1
Interrupt source determination flag 1
RW
IRF2
Interrupt source determination flag 2
RW
IRF3
Interrupt source determination flag 3
RW
NOTES: 1. Set to 00b except in HDLC data processing mode. 2. The SRTiR bit in the IIO4IR register is set to 1, if any of bits IRF3 to IRF0 is set to 1.
Figure 22.43
G0IRF and G1IRF Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i Data Comparison Register j (i=0,1; j=0 to 3)(1)
b7 b0
Symbol G0CMP0 to G0CMP3 G1CMP0 to G1CMP3
Function Data to be compared
Address 00F0h, 00F1h, 00F2h, 00F3h 0130h, 0131h, 0132h, 0133h
After Reset Undefined Undefined
Setting Range 00h to FFh RW RW
NOTE: 1. Set the GiMSK0 register to use the GiCMP0 register. Set the GiMSK1 register to use the GiCMP1 register.
Group i Data Mask Register j (i=0,1; j=0,1)
b7 b0
Symbol G0MSK0, G0MSK1 G1MSK0, G1MSK1
Function Masked data for received data Write 1 to the bit which is not compared
Address 00F4h, 00F5h 0134h, 0135h
After Reset Undefined Undefined
Setting Range 00h to FFh RW RW
Group i Transmit CRC Code Register (i=0,1)
b15 b8 b7 b0
Symbol G0TCRC, G1TCRC
Address 00FBh-00FAh, 013Bh-013Ah
Function
After Reset 0000h
RW RO
Result of the transmit CRC calculation (1)(2)
NOTES: 1. This register becomes the initial value selected by the CRCV bit in the GiEMR register when the TE bit in the GiCR register is set to 0 (transmit operation disabled). 2. Transmit CRC calculation is performed when each one bit of data is transmitted while the TCRCE bit in the GiETC register is set to 1 (used).
Group i Receive CRC Code Register (i=0,1)
b15 b8 b7 b0
Symbol G0RCRC, G1RCRC
Address 00F9h-00F8h, 0139h-0138h
Function
After Reset Undefined
RW RO
Result of the receive CRC calculation (1)(2)(3)
NOTES: 1. This register becomes the initial value selected by the CRCV bit in the GiEMR register when the RCRCE bit in the GiERC register is set to 0 (not used). If the ACRC bit in the GiEMRj (j = 0 to 3) register is set to 1 (initialized), this register is initialized when the received data is matched the data in the GiCMPj register. 2. This register is initialized before receive operation starts. 3. Receive CRC calculation is performed when each one bit of data is received while the RCRCE bit in the GiERC register is set to 1 (used).
Figure 22.44
G0CMP0 to G0CMP3, G1CMP0 to G1CMP3 Registers, G0MSK0 and G0MSK1 Registers, G1MSK0 and G1MSK1 Registers, G0TCRC and G1TCRC Registers, G0RCRC and G1RCRC Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i Transmit Buffer (Receive Data) Register (i=0,1)
b7 b0
Symbol G0TB, G0DR G1TB, G1DR
Address 00EAh 012Ah
Function
After Reset Undefined Undefined
RW
GiTB The transmit data is set in the GiTB register by writing to this address. Set data to be transmitted. GiDR The receive data in the GiDR register is returned by reading this address. In HDLC data processing mode, the value set in the GiRI register is shifted to the GiDR register by bits.
RW
Figure 22.45
G0TB, G1TB Registers, G0DR, G1DR Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Group i SI/O Receive Buffer Register i (i=0, 1)
b15 b8 b7 b0
Symbol G0RB G1RB
Address 00E9h - 00E8h 0129h - 0128h
Bit Name
After Reset XXX0 XXXX XXXX XXXXb X000 XXXX XXXX XXXXb
Function RW RW
Bit Symbol
- (b7-b0) - (b11-b8)
OER
-
Unimplemented. Write 0. Read as undefined value. Overrun error flag(2)
Received data
-
0 : No overrun error 1 : Overrun error detected 0 : No framing error 1 : Framing error detected 0 : No parity error 1 : Parity error detected
RO
FER
Framing error flag(1)(2)
RO
PER
Parity error flag(1)(2) Unimplemented. Write 0. Read as undefined value.
RO
- (b15)
-
NOTES: 1. Nothing is implemented in bits FER and PER in the G0RB register. A read from these bits returns undefined value. 2. Each error flag is updated when the data is transferred from the receive shift register to the GiRB register every time a receive operation is completed.
Group i Receive Input Register (i=0,1)
b7 b0
Symbol G0RI, G1RI
Function
Address 00ECh, 012Ch
After Reset Undefined
Setting Range 00h to FFh RW WO
Write data to be set to a receive data generation circuit
Group i Transmit Output Register (i=0,1)
b7 b0
Symbol G0TO, G1TO
Address 00EEh, 012Eh
Function
After Reset Undefined
RW RO
Read data output from a transmit data generation circuit
Figure 22.46
G0RB, G1RB Registers, G0RI, G1RI Registers, G0TO, G1TO Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
22.4.1
Clock Synchronous Mode (Groups 0 and 1)
Full-duplex clock synchronous serial communication is allowed in this mode. f8, f2n, or external clock can be selected as the group 0 serial clock. f8, f2n, the clock generated in channel 3, or external clock can be selected as the group 1 serial clock. Table 22.14 lists specifications of groups 0 and 1 clock synchronous mode. Table 22.15 and 22.16 list clock settings. Table 22.17 lists pin settings. Figures 22.47 to 22.49 show register setting. Figure 22.50 shows an example of a transmit and receive operation. Table 22.14
Item Data format Serial clock Data length: 8 bits long Refer to the Tables 22.15 and 22.16
Clock Synchronous Mode Specifications (Groups 0 and 1)
Specification
Transmit and receive Select serial clock and set registers GiMR and GiERC (i = 0, 1). Then wait for one or more start condition serial clock cycles before all of the following conditions are met to start the transmit/receive operation. *The TE bit in the GiCR register is set to 1 (transmit operation enabled) *The TI bit in the GiCR register is set to 0 (data in the GiTB register) *The RE bit in the GiCR register is set to 1 (receive operation enabled) If transmit-only operation is performed, the RE bit setting is not required. Interrupt request generation timing Transmit interrupt (The IRS bit in the GiMR register selects one of the following) *When IRS is set to 0 (no data in the GiTB register): When data is transferred from the GiTB register to the transmit shift register (transmit operation started) *When IRS is set to 1 (transmit operation completed): When data transmit operation from the transmit shift register is completed The SIOiTR bit in IIO1IR or IIO3IR register becomes 1 (interrupt requested) when a transmit interrupt request is generated (Refer to Figure 11.18). Receive interrupt *When data is transferred from the receive shift register to the GiRB register (receive operation completed) The SIOiRR bit in IIO1IR or IIO2IR register becomes 1 (interrupt requested) when a receive interrupt request is generated (Refer to Figure 11.18). * Overrun error Overrun error occurs when the 7th bit of the next data is received before reading the GiRB register. If an overrun error occurs, a read from the GiRB register returns an undefined value. The OER bit is updated when the data is transferred from the receive shift register to the GiRB register every time a receive operation is completed. * LSB first or MSB first Data is transmitted and received from either bit 0 or bit 7. * ISTXDi and ISRXDi I/O polarity invert The level output from the ISTXDi pin and the level applied to the ISRXDi pin are inverted.
Error detection
Selectable function
Table 22.15
Clock Settings (Group 0)
G0MR Register CKDIR Bit 0 0 1 CCS Register Bits CCS1 and CCS0 11b 10b -
Serial Clock f8 f2(1) Input to ISCLK0 pin
NOTE: 1. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.16 Clock Settings (Group 1)
G1MR Register CKDIR Bit 0 0 0 1
22. Intelligent I/O (Group 0 and 1 Communication Function)
Serial Clock(3) fBT1 2(n+2) f8 f2n(2) Input to ISCLK1 pin (NOTE 1)
CCS Register Bits CCS3 and CCS2 00b 11b 10b -
n: Setting value of the G1PO0 register (0001h to FFFDh) NOTES: 1. The serial clock is generated in phase-delayed waveform output mode of the channel 3. The baud rate is set using the function, which is to reset a base timer when the value in the G1PO0 register matches the value of a base timer. 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15). 3. The serial clock is set to fBT1 divided by six or lower frequency. Additionally, meet the timing requirements, which are shown on Tables 27.25 and 27.48 Intelligent I/O communication function (Groups 0 and 1) in the chapter 27. Electrical Characteristics.
Table 22.17
Pin Settings in Clock Synchronous Mode (Groups 0 and 1)
Bit Setting G1POCR0 G1POCR1 Registers(2) PSL1, PSL5, PSL9 Registers - - - PSL1_7=0 - PSL5_0=0 - PSL5_1=0 - PSL9_0=0 - PSL9_1=0 -
Port
Function
PD7, PD8, IPS PD11,PD15 Register Registers - IPS1=0 - IPS1=0 - IPS0=0 - IPS0=0 - IPS1=1 - IPS1=1 - IPS0=1 - IPS0=1 - PD7_4=0 - PD7_5=0 - PD7_7=0 - PD8_0=0 - PD11_1=0 - PD11_2=0 - PD15_1=0 - PD15_2=0 - - - - - - - - - - - - - -
PSD1 Register
PSC Register
PS1, PS2, PS5, PS9 Registers(1) PS1_3=1 PS1_4=0 PS1_4=1 PS1_5=0 PS1_6=1 PS1_7=0 PS1_7=1 PS2_0=0 PS5_0=1 PS5_1=0 PS5_1=1 PS5_2=0 PS9_0=1 PS9_1=0 PS9_1=1 -
P7_3 P7_4 P7_5 P7_6 P7_7 P8_0
ISTXD1 Output(3) G1POCR0 ISCLK1 Input ISCLK1 Output ISRXD1 Input ISCLK0 Input ISCLK0 Output ISRXD0 Input - G1POCR1 - - - - - G1POCR1 - - - - -
PSC_3=1 PSL1_3=0 - - - - - - - - - - - - -
PSD1_4=0 PSC_4=1 PSL1_4=0 PSD1_6=0 PSC_6=0 PSL1_6=0
ISTXD0 Output(3) -
P11_0 ISTXD1 Output(3) G1POCR0 P11_1 ISCLK1 Input ISCLK1 Output P11_2 ISRXD1 Input P15_0 ISTXD0 Output(3) P15_1 ISCLK0 Input ISCLK0 Output P15_2 ISRXD0 Input
NOTES: 1. Set registers PS1, PS2, PS5, and PS9 after setting the other registers. 2. Set bits MOD2 to MOD0 in the corresponding register to 111b (use communication function output). 3. After an operating mode is selected in the GiMR register and the pin function is set in the Function Select Registers, the ISTXDi pin outputs an "H" signal when the OPOL bit is set to 0 (No ISTXD output polarity invert) or the ISTXDi pin outputs an "L" signal when the OPOL bit is set to 1 (ISTXD output polarity invert) until a transmit operation starts.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Start Initial Setting
I flag = 0 IIO1IE register: SIO0TE bit = 0 IIO0IE register: SIO0RE bit = 0 IPS register: IPS0 bit CCS register: bits CCS1 and CCS0 G0CR register: TE bit = 0 RE bit = 0 IPOL bit OPOL bit G0MR register: bits GMD1 and GMD0 = 01b CKDIR bit bits 5 to 3 = 000b UFORM bit IRS bit G0ERC register = 00100000b Wait time (1 serial clock cycle ) IIOkIR register = 00h(1) IIOkIE register: IRLT bit = 1 IIO1IE register: SIO0TE bit = 1 IIO0IE register: SIO0RE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in Function Select Registers I flag = 1 G0CR register: TE bit = 1 RE bit = 1
Interrupt disabled Group 0 transmit interrupt disabled Group 0 receive interrupt disabled Group 0 input pin select bit Group 0 clock select bits Transmit operation disabled Receive operation disabled ISRXD input polarity invert bit ISTXD output polarity invert bit
Clock synchronous mode Clock select bit Bit order select bit Transmit interrupt source select bit
Interrupt not requested Interrupt request is used for interrupt Group 0 transmit interrupt enabled Group 0 receive interrupt enabled Interrupt priority level select bit Interrupt not requested Do not set at the same time. Set bits SIO0TE and SIO0RE to 1 after setting the IRLT bit to 1.
Interrupt enabled Transmit operation enabled Receive operation enabled
End initial setting
Transmit/receive operation starts by writing data to the G0TB register. Read the G0RB register after the receive operation is completed.
k = 0,1 NOTE: 1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated in the same register (Interrupt does not occur).
Figure 22.47
Register Settings in Group 0 Clock Synchronous Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Start initial setting
I flag = 0 IIO3IE register: SIO1TE bit = 0 IIO2IE register: SIO1RE bit = 0 IPS register: IPS1 bit G2BCR0 register = 01111111b BTSR register = 00h G2BCR0 register = 00h G1BCR0 register = 01111111b G1BCR1 register = 00000010b G1POCR0 register = 00000111b G1POCR1 register = 00000111b G1POCR3 register = 00000010b G1PO0 register = n G1PO3 register = 0001h G1FS register = 00000000b G1FE register = 00001011b G1BCR1 register: BTS bit = 1 Wait time (1 serial clock cycle) CCS register: bits CCS3 and CCS2 = 00b
Interrupt disabled Group 1 transmit interrupt disabled Group 1 receive interrupt disabled Group 1 input pin select bit
Initialize BTSR register
Clock is provided to each register in group 1 to initialize it Use to generate serial clock Use communication function output Use communication function output Set to phase-delayed waveform output mode n = 0001h to FFFDh Baud rate = fBT1 2( n + 2)
Base timer count starts
Clock generated with waveform generation function
Continuing to Register Settings in Group 1 Clock Synchonous Mode (2/2)
Figure 22.48
Register Settings in Group 1 Clock Synchronous Mode (1/2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Continued from to Register Settings in Group 1 Clock Synchonous Mode (1/2 ) G1CR register: TE bit = 0 RE bit = 0 IPOL bit OPOL bit G1MR register: bits GMD1 and GMD0 = 01b CKDIR bit bits 5 to 3 = 000b UFORM bit IRS bit G1ERC register = 00100000b < When count source in base timer is changed > G1BCR1 register = 00000010b G1BCR0 register: bits BCK1 and BCK0 = 11b bits DIV4 to DIV0 IT bit = 0 G1BCR1 register: BTS bit = 1 Base timer reset Transmit operation disabled Receive operation disabled ISRXD input polarity invert bit ISTXD output polarity invert bit
Clock synchronous mode Clock select bit Bit order select bit Transmit interrupt source select bit
Select f1 as count source Count source divide ratio select bits
Base timer count starts
Wait time (1 serial clock cycle) IIOkIR register = 00h(1) IIOkIE register: IRLT bit = 1 IIO3IE register: SIO1TE bit = 1 IIO2IE register: SIO1RE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in Function Select Registers I flag = 1 G1CR register: TE bit = 1 RE bit = 1 Interrupt enabled Transmit operation enabled Receive operation enabled Interrupt not requested Interrupt request is used for interrupt Group 1 transmit interrupt enabled Group 1 receive interrupt enabled Interrupt priority level select bit Interrupt not requested
Do not set at the same time. Set bits SIO1TE and SIO1RE to 1 after setting the IRLT bit to 1.
End initial setting
Transmit/receive operation starts by writing data to the G1TB Register. Read the G1RB register after the receive operation is completed.
k = 2, 3 NOTE: 1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated in the same register (Interrupt does not occur).
Figure 22.49
Register Settings in Group 1 Clock Synchronous Mode (2/2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
(1) When f8, f2n or External Clock is Selected as the Serial Clock (Groups 0 and 1)
Write to the GiTB register 1 0 "H" "L" Bit 0 1 0 1 0 Bit 0 1 0 Set to 0 by a program Bit 1 Bit 2 Bit 6 Set to 0 by a program Set to 0 by a program Bit 7 Bit 1 Bit 2 Bit 6 Bit 7
TE Bit in the GiCR register Serial clock Output from ISTXDi pin (Transmit data) SIOiTR bit in the IIOjIR register(1) SIOiTR bit in the IIOjIR register (2) Input to ISRXDi pin (Receive data) SIOiRR bit in the IIOkIR register i = 0, 1; j = 1, 3; k = 0, 2
The above applies under the following conditions: - Bits CCS1 and CCS0 or bits CCS3 and CCS2 in the CCS register are set to 10b or 11b - The UFORM bit in the GiMR register is set to 0 (LSB first) - Bits IPOL and OPOL in the GiCR register are set to 0 (not inverted) NOTES: 1. This applies when IRS bit in the GiMR register is set to 0 (No data in the GiTB register). 2. This applies when IRS bit in the GiMR register is set to 1 (Transmit operation completed).
(2) When the Serial Clock is Generated in Channel 3 Phase-Delayed Waveform Output Mode (Group 1)
Write to the G1TB register n+2 The base timer is reset by the channel 0 waveform generation function
Base Timer
m
Output from ISCLK1 pin "H" (Serial clock in the channel 3 generation "L" function) Output from ISTXD1 pin (Transmit data) SIO1TR bit in the IIO3IR register(1) 1 0 Set to 0 by a program Input to ISRXD1 pin (Receive data) SIO1RR bit in the IIO2IR register 1 0 Set to 0 by a program Bit 0 Bit 1 Bit 2 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 6 Bit 7
n: Setting value of the G1PO0 register m: Setting value of the G1PO3 register
The above applies under the following conditions: - In the G1MR register, the CKDIR bit is set to 0 (internal clock), the UFORM bit is set to 0 (LSB first) - Bits CCS3 and CCS2 in the CCS register are set to 00b (Clock generated with waveform generation function) - Bits IPOL and OPOL in the G1CR register are set to 0 (not inverted) NOTE: 1. This applies when the IRS bit in the G1MR register is set to 0 (No data in the G1TB register).
Figure 22.50
Transmit and Receive Operation in Clock Synchronous Mode (Groups 0 and 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
22.4.2
Clock Asynchronous (UART) Mode (Group 1)
Table 22.18 lists specifications of UART mode. Table 22.19 lists pin settings. Figures 22.51 and 22.52 show register settings. Figure 22.53 shows an example of a transmit operation. Figure 22.54 shows an example of a receive operation. Table 22.18
Item Data format
UART Mode Specifications
Specification * Data length: 8 bits long * Start bit: 1 bit long * Parity bit: selectable among odd, even, or none * Stop bit: selectable from 1 bit or 2 bits long fBT1 2(n + 2) n: Setting value of the G1PO0 register (0006h to FFFDh) * The CKDIR bit in the G1MR register is set to 0 (internal clock) * Bits CCS3 and CCS2 in the CCS register is set to 00b (Clock generated with waveform generation function) The internal transmit clock is generated in phase-delayed waveform output mode of the channel 3. The internal receive clock is generated by performing both the time measurement and phasedelayed waveform output in the channel 2.
Baud rate
Transmit start condition
Set registers associated with the waveform generation function and the G1MR register. Then wait for one or more internal transmit clock cycles before all of the following conditions are met to start the transmit operation. *The TE bit in the G1CR register is set to 1 (transmit operation enabled) *The TI bit in the G1CR register is 0 (data in the G1TB register) Set registers associated with the waveform generation function and the G1MR register. Then wait for one or more internal receive clock cycles before all of the following conditions are met to start the receive operation. *The RE bit in the G1CR register is set to 1 (receive operation enabled) *Detecting the start bit ("L" level) Transmit interrupt (The IRS bit in the G1MR register selects one of the following): *When the IRS bit is set to 0 (no data in the GiTB register): When data is transferred from the G1TB register to the transmit shift register (transmit operation started) *When the IRS bit is set to 1 (transmit operation completed): When the final stop bit is output from the transmit shift register The SIO1TR bit in the IIO3IR register becomes 1 (interrupt requested) when a transmit interrupt request is generated (Refer to Figure 11.18). Receive interrupt: *When data is transferred from the receive shift register to the G1RB register (receive operation completed) The SIO1RR bit in the IIO2IR register becomes 1 (interrupt requested) when a receive interrupt request is generated (Refer to Figure 11.18). * Overrun error Overrun error occurs when the preceding bit of the final stop bit of the next data (the first stop bit when selecting 2 stop bits) is received before reading the G1RB register. If an overrun error occurs, a read from the G1RB register returns an undefined value. * Framing error Framing error occurs when the number of the stop bits set by the STPS bit in the G1MR register is not detected. * Parity error Parity error occurs when parity is enabled and the received data does not have the correct even or odd parity set by the PRY bit in the G1MR register. Each error flag is updated when the data is transferred from the receive shift register to the G1RB register every time a receive operation is completed. * LSB first or MSB first Data is transmitted or received from either bit 0 or bit 7.
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Table 22.19 Pin Settings in UART Mode (Group 1)
Port P7_3 P7_5 P11_0 P11_2 Function G1POCR0 Register(2) - IPS1=0 - IPS1=1 Bit Setting IPS Register PD7, PD11 Registers - PD7_5=0 - PD11_2=0 - - - PSC Register PSC_3=1 PSL1, PSL5 Registers PSL1_3=0 - PSL5_0=0 - PS1, PS5 Registers(1) PS1_3=1 PS1_5=0 PS5_0=1 PS5_2=0
ISTXD1 output G1POCR0 ISRXD1 input ISRXD1 input - - ISTXD1 output G1POCR0
NOTES: 1. Set registers PS1 and PS5 after setting the other registers. 2. Set bits MOD2 to MOD0 in the G1POCR0 register to 111b (use communication function output).
Start Initial Setting
I flag = 0 IIO3IE register: SIO1TE bit = 0 IIO2IE register: SIO1RE bit = 0 IPS register: IPS1 bit
Interrupt disabled Group 1 transmit interrupt disabled Group 1 receive interrupt disabled Group 1 input pin select bit
G2BCR0 register = 01111111b BTSR register = 00h G2BCR0 register = 00h G1BCR0 register = 01111111b G1BCR1 register = 00000010b G1TMCR2 register = 00000011b G1POCR0 register = 00000111b G1POCR2 register = 00000110b G1POCR3 register = 00000010b G1PO0 register = n G1PO3 register = 0001h G1FS register = 00000100b G1FE register = 00001101b G1BCR1 register: BTS bit = 1 CCS register: bits CCS3 and CCS2 = 00b
Initialize BTSR register
Clock is provided in group 1 to initialize it Use to generate internal transmit/receive clock Both edges for time measurement trigger Use communication function output Use for receive operation in UART mode Phase-delayed waveform output mode n = 0006h to FFFDh Baud rate = fBT1 2(n + 2)
Channel 0, 3: Select waveform generation function Channel 2: Select time measurement function Channel 0, 2, and 3 functions enabled Base timer count starts
Clock generated with a waveform generation function
Continuing to Register Settings in Group 1 UART Mode (2/2)
Figure 22.51
Register Settings in Group 1 UART Mode (1/2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Continued from Register Settings in Group 1 UART Mode (1/2)
G1CR register: TE bit = 0 RE bit = 0 IPOL bit = 1 OPOL bit = 1 G1MR register: bits GMD1 and GMD0 = 00b CKDIR bit = 0 STPS bit PRY bit PRYE bit UFORM bit IRS bit G1ERC register = 00h < When count source of base timer is changed > G1BCR1 register = 00000010b G1BCR0 register: bits BCK1 and BCK0 = 11b bits DIV4 to DIV0 IT bit = 0 G1BCR1 register: BTS bit = 1
Transmit operation disabled Receive operation disabled ISRXD input polarity invert bit ISTXD output polarity invert bit
UART mode Internal clock Stop bit length select bit Parity select bit Parity enable bit Bit order select bit Transmit interrupt source select bit
Base timer reset
Select f1 as count source Count source divide ratio select bits
Base timer count starts
Wait time (1 internal transmit/receive clock cycle) IIOkIR register = 00h(1) IIOkIE register: IRLT bit = 1 IIOkIE register: SIO1TE bit = 1 SIO1RE bit = 1 IIOkIC register: bits ILVL2 to ILVL0 IR bit = 0 Pin settings in Function Select Registers I flag = 1 G1CR register: TE bit = 1 RE bit = 1 Interrupt enabled Transmit operation enabled Receive operation enabled Interrupt not requested Interrupt request is used for interrupt Group 1 transmit interrupt enabled Group 1 receive interrupt enabled Interrupt priority level select bits Interrupt not requested
Do not set at the same time. Set bits SIO1TE and SIO1RE to 1 after setting the IRLT bit to 1.
End Initial Setting
Transmit operation starts by writing data to the G1TB Register. Receive operation starts when a start bit ("L" level) is detected. Read the G1RB register when the receive operation is completed. k = 2, 3 NOTE: 1. Set all the interrupt request flags to 0. If any of these flags remains 1, the IR bit in the IIOkIC register does not become 1 when an interrupt request is generated in the same register (Interrupt does not occur).
Figure 22.52
Register Settings in Group 1 UART Mode (2/2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Internal transmit clock ISTXD1 pin TI bit in the G1CR register TXEPT bit in the G1CR register SIO1TR bit in the IIO3IR register "H" "L" 1 0 1 0 1 0 Set to 0 by a program Set data in the G1TB register Set data in the G1TB register
ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP
The above applies under the following conditions: - The STPS bit in the G1MR register is set to 0 (1 stop bit) - The PRYE bit in the G1MR register is set to 0 (parity disabled) - The UFORM bit in the G1MR register is set to 0 (LSB first) - The INV bit in registers G1POCR0 to G1POCR7 is set to 0 (output not inverted) - The IRS bit in the G1MR register is set to 0 (no data in the G1TB register)
Figure 22.53
Transmit Operation in Group 1 UART Mode
n+1
Base timer 1
0000h ISRXD1 pin
Start Bit (ST)
D0
Internal receive clock
Synchronization
2 (n + 2) fBT1 ISRXD1 pin "H" "L"
ST D0 D1 D2 D3
Cycle
D4
D5
D6
D7
SP
ST
D0
D1
D2
Internal receive clock 1 0 1 0 SIO1RR bit: The bit in the IIO2IR register RI bit: The bit in the G1CR register Set to 0 by a program Read the G1RB register
The RI bit
The SIO1RR bit
The above applies under the following conditions: - The STPS bit in the G1MR register is set to 0 (1 stop bit) - The PRYE bit in the G1MR register is set to 0 (parity disabled) - The UFORM bit in the G1MR register is set to 0 (LSB first) - The INV bit in registers G1POCR0 to G1POCR7 is set to 0 (output not inverted)
Figure 22.54
Receive Operation in Group 1 UART Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 0 and 1 Communication Function)
22.4.3
HDLC Data Processing Mode (Group 0 and Group 1)
In HDLC data processing mode, bit stuffing, flag sequence detection, abort sequence detection and CRC calculation are available for HDLC data processing. In this mode, the MCU is unable to input or output data in noreturn-to-zero-invert (NRZI) format (No pin is used). f1, f8 or f2n can be selected as the group 0 transfer clock. f1, f8, f2n or the clock generated in the channel 0 or 1 can be selected as the group 1 transfer clock. To generate HDLC frame data, write source data to the GiTB register (i=0,1). The data conversion result is stored into the GiTO register. If data is in the GiTO register, the conversion is stopped. The conversion is resumed by reading the GiTO register. The HDLC data processing is performed even no data in the GiTB register. A CRC value is calculated every time one bit is converted. To generate source data, write HDLC frame data to the GiRI register. The data in the GiRI register is transferred to the shift register. HDLC data processing starts when the value in the shift register matches the value in the GiCMP3 register (7Eh). The data conversion result is stored into the GiRB register. Tables 22.20 and 22.21 list specifications of the HDLC data processing mode. Tables 22.22 and 22.23 list clock settings. Table 22.24 lists register settings. Table 22.20
Item Input data format Output data format Transfer clock I/O method 8-bit data fixed See Tables 22.22 and 22.23 * When HDLC frame data is generated from source data: A value set in the GiTB register (i=0,1) is converted with HDLC data processing and transferred to the GiTO register. * When source data is generated from HDLC frame data: A value set in the GiRI register is converted with HDLC data processing and transferred to the GiRB register. When HDLC frame data is generated, a "0" is inserted after five continuous "1's". When source data is generated, a "0" is deleted after five continuous "1's". Write the flag sequence "7Eh" to the GiCMP3 register. When the GiDR register matches the GiCMP3 register, a special communication function interrupt is generated. (The SRTiR bit in the IIO4IR register becomes 1.)
Specifications of the HDLC Data Processing Mode (1/2)
Specification 8-bit data fixed, bit alignment is optional
Bit stuffing Flag sequence detection
Abort sequence detection Write the abort sequence "FEh" to the GiCMPj register (j = 0, 1) and the masked data "01h" to the GiMSKj register. When the GiDR register and the GiCMPj register are compared and all the non-masked bits are matched, a special communication function interrupt is generated. (The SRTiR bit in the IIO4IR register becomes 1.) CRC Bits CRC1 and CRC0 are set to 11b (X16+X12+X5+1) The CRCV bit is set to 1 (set to FFFFh) * When HDLC frame data is generated: CRC calculation result is stored into the GiTCRC register. The TCRCE bit in the GiETC register is set to 1 (transmit CRC used). Initialization: The CRC calculation result is initialized when the TE bit in the GiCR register is set to 0 (transmit disabled). * When source data is generated: CRC calculation result is stored into the GiRCRC register. The RCRCE bit in the GiERC register is set to 1 (receive CRC used). Initialization: The CRC calculation result is initialized when the GiDR register matches the GiCMP3 register by comparing the flag sequence "7Eh" (The ACRC bit in the GiEMR register is set to 1 (CRC is initialized)). The following conditions are required to start HDLC frame data generation: * The TE bit in the GiCR register is set to 1 (transmit operation enabled) * Data is written to the GiTB register The following conditions are required to start source data generation: * The RE bit in the GiCR register is set to 1 (receive operation enabled) * Data is written to the GiRI register
Data processing start condition
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.21
22. Intelligent I/O (Group 0 and 1 Communication Function)
Specifications of the HDLC Data Processing Mode (2/2)
Specification When HDLC frame data is generated: * The IRS bit in the GiMR register selects one of the following: - When the IRS bit is set to 0 (no data in the GiTB register) When data is transferred from the GiTB register to the transmit shift register (transmit operation started). - When the IRS bit is set to 1 (transmit operation completed) When data transfer from the transmit shift register to the GiTO register is completed. When one of the above occurs, the GiTOR bit in the IIO1IR or IIO3IR register becomes 1 (interrupt requested) (Refer to Figure 11.18). * When data, which is already converted to HDLC frame data, is transferred from the transmit shift register of the GiTO register to the transmit buffer, the GiTOR bit becomes 1. When source data is generated: * When data is transferred from the GiRI register to the GiRB register (receive operation completed), the GiRIR bit in the IIO0IR or IIO2IR register becomes 1 (interrupt requested). * When receive data is transferred from the receive buffer in the GiRI register to the receive shift register, the GiRIR bit becomes 1. * When the GiTB register is compared to the GiCMPj register (j = 0 to 3), the SRTiR bit in the IIO4IR register becomes 1 (interrupt requested).
Item Interrupt request generation timing
Table 22.22
Clock Settings in HDLC Data Processing Mode (Group 0)
CCS Register CCS0 Bit 1 1 0 CCS1 Bit 0 1 1
Transfer Clock(1) f1 f8 f2n(2)
NOTES: 1. The transfer clock is generated when the RSHTE bit in the G0ERC register is set to 1 (receive shift operation enabled) while source data is generated. 2. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Table 22.23
Clock Setting in HDLC Data Processing Mode (Group 1)
CCS Register CCS2 Bit 0 1 1 0 CCS3 Bit 0 0 1 1
Transfer Clock(1) fBT1 m+2 f1 f8 f2n(3) (NOTE 2)
m: Setting value of the G1PO0 register (0001h to FFFDh) NOTES: 1. The transfer clock is generated when the RSHTE bit in the G1ERC register is set to 1(receive shift operation enabled) while source data is generated. 2. The transfer clock is generated in single-phase waveform output mode of the channel 1. 3. Bits CNT3 to CNT0 in the TCSPR register select no division (n=0) or divide-by-2n (n=1 to 15).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.24
Register CCS G1BCR0(1)
22. Intelligent I/O (Group 0 and 1 Communication Function)
Register Settings in HDLC Data Processing Mode (Groups 0 and 1)
Bit CCS1 and CCS0 CCS3 and CCS2 BCK1 and BCK0 DIV4 to DIV0 IT - - - - - FSC1 and FSC0 IFE1 and IFE0 GMD1 and GMD0 CKDIR UFORM IRS TE TXEPT TI RE Function Select transfer clock. Select transfer clock. Select count source. Select count source divide ratio. Select the base timer interrupt generation timing. Set to 0001 0010b. Set to 0000 0000b. Set to 0000 0000b. Set baud rate. Set the timing of the rising edge of the transfer clock. Timing of the falling edge ("H" width of the transfer clock) is fixed. Setting value of the G1PO1 register setting value of the G1PO0 register Set to 00b. Set to 11b. Set to 11b. Set to 0. Set to 0. Select a transmit interrupt source. Set to 1 to enable a transmit operation (HDLC frame data generation from source data). Transmit shift register empty flag GiTB register empty flag Set to 1 to enable a receive operation (source data generation from HDLC frame data). Receive completion flag Set to 1111 0110b. Set to 1 (CRC calculation is performed when HDLC frame data is generated from source data). Set to 1 ("0" is inserted when HDLC frame data is generated). Select whether or not the GiDR register and GiCMPj register (j = 0 to 2) are compared. Set to 1. Set to 1 (CRC calculation is performed when source data is generated from HDLC frame data). When source data is generated, set to 1. Set to 1 ("0" is deleted when source data is generated). Select an interrupt source. Write FEh to detect an abort sequence. Set data to be compared. Write 7Eh. Write 01h to detect an abort sequence. The CRC code, which is calculated when generating HDLC frame data from source data, can be read. The CRC code, which is calculated when generating source data from HDLC frame data, can be read. Used to generate HDLC frame data. Write source data. Used to generate HDLC frame data. HDLC frame data, which is generated from source data, can be read. Used to generate source data. Write HDLC frame data. Used to generate source data. Source data, which is generated from HDLC frame data, can be read.
G1BCR1(1) G1POCR0(1) G1POCR1(1) G1PO0(1) G1PO1(1) G1FS(1) G1FE(1) GiMR
GiCR
GiEMR GiETC GiERC
RI - TCRCE TBSF1 CMP2E to CMP0E CMP3E RCRCE RSHTE RBSF1 IRF3 to IRF0 - - - - - - - - - -
GiIRF GiCMP0 and GiCMP1 GiCMP2 GiCMP3 GiMSK0 and GiMSK1 GiTCRC GiRCRC G1TB GiTO GiRI G1RB
i = 0,1 NOTE: 1. These register settings are required when bits CCS3 and CCS2 in the CCS register are set to 00b (clock generated with the waveform generation function).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
22.5
Group 2 Communication Function
In the group 2 communication function, variable data length clock synchronous serial communication is available. Figure 22.55 shows block diagram of group 2 communication function. Figures 22.56 to 22.60 show registers associated with the communication function.
The signal output when G2POi register (i = 0 to 7) matches a base timer G2TB register Channel 2 generation clock ISCLK2
Clock selecter
Bit counter
Transmit shift register
Output control function OPOL Polarity invert
Serial clock output from ISCLK2 pin Transfer data output from ISTXD2 / IEOUT pin
Transmit parity calculation Byte counter ACK calculation
Latch
Receive parity calculation
Arbitration lost detection
DF IEIN/ ISRXD2 Digital filter 0 1
IPOL Polarity invert Receive register
IE, serial interface interrupt control
IE transmit interrupt request (IE0R to IE2R) IE receive interrupt request (IE0R to IE2R) Clock synchronous mode transmit interrupt request (SIO2TR) Clock synchronous mode receive interrupt request (SIO2RR)
G2RB register
ID detection All "F" detection Address detect function
Statement length detect function
The signal output when G2PO6 or G2PO7 register matches a base timer
Start bit detection function
IE start bit interrupt request (IE0R to IE2R)
OPOL, IPOL: Bits in the G2CR register DF: Bit in the IECR register IE0R to IE2R: Bits in registers IIO7IR and IIO8IR SIO2TR : Bit in the IIO6IR register SIO2RR: Bit in the IIO5IR register NOTE: 1. After a clock, which is selected in the G2BCR0 register, is supplied to the registers, each register value becomes the after reset value.
Figure 22.55 Group 2 Communication Function Block Diagram
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22. Intelligent I/O (Group 2 Communication Function)
Group 2 SI/O Transmit Buffer Register
b15 b8 b7 b0
Symbol G2TB
Bit Symbol Bit Name Transmit buffer
Address 016Dh - 016Ch
Function Transmit Data
b10 b9 b8
After Reset Undefined
RW WO
- (b7-b0)
SZ0
SZ1
Data length select bits
SZ2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0:8 1:1 0:2 1:3 0:4 1:5 0:6 1:7
bits long bits long bits long bits long bits long bits long bits long bits long
RW
RW
RW
- (b12-b11)
A
Unimplemented. Write 0. Read as undefined value. ACK function select bit 0 : Adds no ACK bit 1 : Adds the ACK bit after last transmit bit 0 : Adds the parity bit after the transmit data 1 : Carries over a parity to the following transmit data(1) 0 : No parity 1 : Parity (even parity only)
-
RW
PC
Parity calculation continuing bit
RW
P
Parity function select bit
RW
NOTE: 1. Set the P bit to 0 before setting the PC bit to 1.
Group 2 SI/O Receive Buffer Register
b15 b8 b7 b0
Symbol G2RB
Bit Symbol Bit Name Receive buffer
Address 016Fh - 016Eh
Function Receive data
After Reset Undefined
RW RO
- (b7-b0) - (b11-b8)
OER
Unimplemented. Write 0. Read as undefined value. Overrun error flag(1) Unimplemented. Write 0. Read as undefined value. 0 : No overrun error 1 : Overrun error detected
-
RO
- (b15-b13)
-
NOTE: 1. The OER bit becomes 0 when bits GMD1 and GMD0 in the G2MR register are set to 00b (communication unit is reset) or the RE bit in the G2CR register is set to 0 (receive operation disabled).
Figure 22.56
G2TB, G2RB Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
Group 2 SI/O Communication Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G2MR
Bit Symbol GMD0 Communication mode select bits GMD1 Bit Name
Address 016Ah
Function
b1 b0
After Reset 00XX X000b
RW RW
0 0 : Communication unit is reset (The OER bit becomes 0) (1) 0 1 : Clock synchronous mode (2) 1 0 : IE mode(2) 1 1 : Do not set to this value 0 : Internal clock 1 : External clock
RW
CKDIR
Clock select bit Unimplemented. Write 0. Read as undefined value. Bit order select bit
RW
- (b5-b3)
UFORM
-
0 : LSB first 1 : MSB first 0 : No data in the G2TB register (TI = 1) 1 : Transmit operation completed (TXEPT = 1)
RW
IRS
Transmit interrupt source select bit
RW
NOTES: 1. When changing mode, set bits GMD1 and GMD0 to 00b (communication unit is reset) and wait for one or more fBT2 clock cycles before setting to different mode. 2. Set bits GMD1 and GMD0 to 01b (clock synchronous mode) or 10b (IE mode) while fBT2 is stopped.
Figure 22.57
G2MR Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
Group 2 SI/O Communication Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol G2CR
Bit Symbol TE Bit Name
Address 016Bh
Function 0 : Transmit operation disabled 1 : Transmit operation enabled
After Reset 0000 X000b
RW RW
Transmit operation enable bit
TXEPT
Transmit shift register empty flag
0 : Data is in the transmit shift register (during transmit operation) 1 : No data is in the transmit shift register (transmit operation is completed) 0 : Data is in the G2TB register 1 : No data is in the G2TB register
RO
TI
G2TB register empty flag Unimplemented. Write 0. Read as undefined value. Receive operation enable bit(1)
RO
- (b3)
RE
-
0 : Receive operation disabled 1 : Receive operation enabled 0 : No data is in the G2RB register 1 : Data is in the G2RB register 0 : Not inverted 1 : Inverted 0 : Not inverted 1 : Inverted
RW
RI
Receive complete flag
RO
OPOL
ISTXD output polarity invert bit
RW
IPOL
ISRXD input polarity invert bit (1)
RW
NOTE: 1. The group 2 base timer may be reset when the RE or IPOL bit setting is changed. To avoid resetting, set the RST2 bit in the G2BCR1 register to 0 (base timer is not reset by a reset request from the communication function).
Figure 22.58
G2CR Register
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
Group 2 IEBus Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IECR
Bit Symbol IEB Bit Name IEBus enable bit(1)
Address 0172h
Function 0 : IEBus disabled(2) 1 : IEBus enabled 0 : Transmit operation completed 1 : Transmit operation started 0 : Idle state 1 : Busy state (start condition detected)
After Reset 00XX X000b
RW RW
IETS
IEBus transmit operation start request bit IEBus busy flag Unimplemented. Write 0. Read as undefined value. Digital filter select bit
RW
IEBBS
RO
- (b5-b3)
DF
-
0 : No digital filter 1 : Digital filter 0 : Mode 1 1 : Mode 2
RW
IEM
IEBus mode select bit
RW
NOTES: 1. Change the IEB bit setting while fBT2 is stopped. 2. When the IEB bit is set to 0, maintain the value for one or more fBT2 clock cycles. Set bits BCK1 and BCK0 in the G2BCR0 register to 00b (clock stop) when the IEB bit is set back to 1.
Group 2 IEBus Address Register
b15 b8 b7 b0
Symbol IEAR
Address 0171h - 0170h
Function
After Reset Undefined
RW RW
Address data
Address data Unimplemented. Write 0. Read as undefined value.
RW
-
Figure 22.59
IECR and IEAR Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
Group 2 IEBus Transmit Interrupt Source Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IETIF
Bit Symbol Bit Name
Address 0173h
Function
After Reset XXX0 0000b
RW
IETNF
Normal complete flag(1)
0 : Transmit operation is completed in error 1 : Transmit operation is successfully completed 0 : No error detected 1 : Error detected 0 : No error detected 1 : Error detected 0 : No error detected 1 : Error detected 0 : No error detected 1 : Error detected
RW
IEACK
ACK error flag(1) Maximum transfer byte error flag(1) Timing error flag(1)
RW
IETMB
RW
IETT
RW
IEABL
Arbitration lost flag(1) Unimplemented. Write 0. Read as undefined value.
RW
- (b7-b5)
-
NOTE: 1. This bit can be set to 0 by a program, but cannot be set to 1. When the IEB bit in the IECR register is set to 0 (IEBus disabled), bits IETNF, IEACK, IETMB, IETT, and IEABL become 0.
Group 2 IEBus Receive Interrupt Source Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IERIF
Bit Symbol Bit Name
Address 0174h
Function
After Reset XXX0 0000b
RW
IERNF
Normal completed flag(1)
0 : Receive operation is completed in error 1 : Receive operation is successfully completed 0 : No error detected 1 : Error detected 0 : No error detected 1 : Error detected 0 : No error detected 1 : Error detected 0 : No error detected 1 : Error detected
RW
IEPAR
Parity error flag(1)
RW
IERMB
Max. transfer byte error flag (1)
RW
IERT
Timing error flag(1) Other source receive completed flag(1) Unimplemented. Write 0. Read as undefined value.
RW
IERETC
RW
- (b7-b5)
-
NOTE: 1. This bit can be set to 0 by a program, but cannot be set to 1. When the IEB bit in the IECR register is set to 0 (IEBus disabled), bits IETNF, IEACK, IETMB, IETT, and IEABL become 0.
Figure 22.60
IETIF and IERIF Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
22.5.1
Variable Data Length Clock Synchronous Mode (Group 2)
In variable data length clock synchronous mode, full-duplex clock synchronous serial communication is allowed. Transmit data can be selected from 1 to 8 bits long. Continuous transmit/receive operations enable to communicate more than 9 bit-long data. Table 22.25 lists specifications of the group 2 variable data length clock synchronous mode. Table 22.26 lists register settings. Table 22.27 lists pin settings. Figure 22.61 shows an example of a transmit and receive operation. Table 22.25
Data format Serial clock(1)
Variable Data Length Clock Synchronous Mode Specifications (Group 2)
Specification Data length: variable When the CKDIR bit in the G2MR register is set to 0 (internal clock): fBT2 2(n + 2) n: setting value of the G2PO0 register (0001h to FFFDh)
Item
The G2PO0 register determines a baud rate and the serial clock is generated in phase-delayed waveform output mode of the channel 2. When the CKDIR bit is set to 1 (external clock): The serial clock is input from the ISCLK2 pin. Transmit start condition Transmit operation starts when all of the following conditions are met: * Set the TE bit in the G2CR register to 1 (transmit operation enabled) * Data is written to the G2TB register Receive operation starts when all of the following conditions are met: * Set the TE bit in the G2CR register to 1 (transmit operation enabled) * Data is written to the G2TB register * Set the RE bit in the G2CR register to 1 (receive operation enabled) Transmit interrupt (The IRS bit in the G2MR register selects one of the following): * The IRS bit is set to 0 (no data in the G2TB register): When data is transferred from the G2TB register to the transmit shift register (transmit operation started). * The IRS bit is set to 1 (transmit operation completed): When data transmit operation from the transmit shift register is completed. When the transmit interrupt request is generated, the SIO2TR bit in the IIO6IR register becomes 1 (interrupt requested) (See Figure 11.18). Receive interrupt: * When data is transferred from the receive shift register to the G2RB register (receive operation completed) When the receive interrupt request is generated, the SIO2RR bit in the IIO5IR register becomes 1 (interrupt requested) (See Figure 11.18). Overrun error Overrun error occurs when the jth stop bit of the next data (data length: j bits (j = 1 to 8)) is received before reading the G2RB register. If an overrun error occurs, a read from the G2RB register returns an undefined value. * LSB first or MSB first (Selectable only in 8-bits mode) Data is transmitted and received from either bit 0 or bit 7. Select LSB first except 8-bits mode. * ISTXD2 and ISRXD2 I/O polarity invert ISTXD2 pin output level and ISRXD2 pin input level are inverted
Receive start condition
Interrupt request generation timing
Error detection
Selectable function
NOTE: 1. The serial clock must be fBT2 divided by six or lower frequency when the internal clock is selected, and the serial clock must be fBT2 divided by 20 or lower frequency when the external clock is selected. Additionally, meet the conditions shown on Tables 27.26 and 27.49 Intelligent I/O communication function (Group 2) in the chapter 27. Electrical Characteristics.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 22.26
Register G2BCR0
22. Intelligent I/O (Group 2 Communication Function)
Register Settings in Variable Data Length Clock Synchronous Mode (Group 2)
Bit BCK1 and BCK0 DIV4 to DIV0 IT Set to 11b Select count source divide ratio Set to 0 Set to 0001 0010b Set to 0000 0111b Set to 0000 0111b Set to 0000 0010b Set the value to compare for waveform generation Serial clock frequency: fBT2 2 x (setting value + 2) Function
G2BCR1 G2POCR0 G2POCR1 G2POCR2 G2PO0
- - - - -
G2PO2 G2FE G2MR
- IFE2 to IFE0 GMD1 and GMD0 CKDIR UFORM IRS
Set the value less than the setting value of the G2PO0 register Set to 111b Set to 01b Select either internal or external clock Select either LSB first or MSB first Select the transmit interrupt source Set to 1 when a transmit/receive operation is enabled Transmit shift register empty flag G2TB register empty flag Set to 1 when a receive operation is enabled Receive complete flag ISTXD2 output polarity invert (Set to 0 in normal use) ISRXD2 input polarity invert (Set to 0 in normal use) Write data length and transmit data Received data and an error flag are stored
G2CR
TE TXEPT TI RE RI OPOL IPOL
G2TB G2RB
- -
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
22. Intelligent I/O (Group 2 Communication Function)
Table 22.27 Pin Settings in Variable Data Length Clock Synchronous Mode (Group 2)
Bit Setting Port Function G2POCR0 G2POCR1 Registers(4) - IPS Register IPS6 = 0 - - PD6, PD7, PD9, PD13 Registers(2) PD6_4 = 0 - - - - - - - - PSD1 Register - - - - - - - - - PSC Register - PSL0, PSL1, PSL3, PSL7 Registers PS0, PS1 PS3, PS7 Registers(2)(3) PS0_4 = 0
P6_4
ISCLK2 Input
ISCLK2 Output G2POCR1 P7_0(1) ISTXD2 Output G2POCR0 P7_1(1) ISRXD2 Input P9_1 P9_2 ISRXD2 Input - -
PSL0_4 = 1 PS0_4 = 1 - - PS1_1 = 0 PS3_1 = 0
PSD1_0 = 0 PSC_0 = 1 PSL1_0 = 0 PS1_0 = 1
IPS5 and PD7_1 = 0 IPS4 = 00b IPS5 and PD9_1 = 0 IPS4 = 01b - - - -
ISTXD2 Output G2POCR0 - -
PSL3_2 = 1 PS3_2 = 1 PSL7_4 = 0 PS7_4 = 1 - - PS7_5 = 0 PS7_6 = 0
P13_4 ISTXD2 Output G2POCR0 P13_5 ISRXD2 Input P13_6 ISCLK2 Input
IPS5 and PD13_5 = 0 - IPS4 =10b IPS6 = 1 - PD13_6 = 0 - - -
ISCLK2 Output G2POCR1
PSL7_6 = 0 PS7_6 = 0
NOTES: 1. The P7_0 and P7_1 are the N-channel open drain output ports. 2. Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 3. Set registers PS0, PS1, PS3, and PS7 after setting the other registers. 4. Set bits MOD2 to MOD0 in the corresponding register to 111b (use communication function output).
Write data to the G2TB register (8-bit data)
Write data to the G2TB register (4-bit data)
Serial clock generated with the channel 2 waveform generation function ISCLK2 ISTXD2 ISRXD2
"H" "L" "H" "L" "H" "L" "H" "L" b0 b0 b1 b1 b2 b2 b6 b6 b7 b7 b0 (b8) b0 (b8) b1 (b9) b1 (b9) b2 b3 (b10) (b11) b2 b3 (b10) (b11)
Transfer to the G2RB register
Transfer to the G2RB register
Figure 22.61 Transmit/Receive Operation in Variable Clock Synchronous Mode (Group 2)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23. CAN Module
NOTE Only CAN0 can be used in the M32C/87A. CAN Module is not available in the M32C/87B.
CAN (Controller Area Network) module included in the M32C/87 Group is a Full CAN module, supporting CAN Specification 2.0 Part B. Two channels, CAN0 and CAN1, can be used. Table 23.1 lists CAN module specifications of the CAN0 and CAN1 channels. Table 23.1
Protocol Message slots Acceptance filter Baud rate(1)
CAN Module Specifications for CAN0 and CAN1
Item CAN Specification 2.0 Part B 16 slots Global mask: 1 (for the CANi message slots 0 to 13 (i = 0,1)) Local mask: 2 (for CANi message slots 14 and 15 respectively) 1 Baud rate = ---Max 1 Mbps Tq x number of Tq per bit BRP + 1 Tq (time quantum) = CAN clock Number of Tq per bit = SS + PTS + PBS1 + PBS2 BRP: Setting value of registers C0BRP and C1BRP; 1 to 255 SS: Synchronization Segment; 1Tq PTS: Propagation Time Segment; 1 to 8Tq PBS1: Phase Buffer Segment 1; 2 to 8Tq PBS2: Phase Buffer Segment 2; 2 to 8Tq Specification
Remote frame automatic answering function Time stamp function
Message slot which receives a remote frame transmits a data frame automatically The time stamp function is used with a 16-bit counter. Count source can be selected from the CAN bus bit clock divided by 1, 2, 3, or 4 1 CAN bus bit clock= CAN bit time CAN bit time = Tq x number of Tq per bit The BasicCAN function can be used with the CANi message slots 14 and 15 A transmit request is aborted Frame transmitted by the CAN module is received by the same CAN module The CAN module is forcibly placed in an error active state by an error counter reset The CAN module does not retransmit data even if arbitration lost or transmit error causes a transmit failure The CAN module communicates internally to check on a CAN module state
BasicCAN mode Transmit abort function Loopback function Forcible error active transition function Single-shot transmit function Self-test function
NOTE: 1. Use an oscillator with maximum 1.58% oscillator tolerance.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
Figure 23.1 shows a block diagram of the CAN module for CAN0 and CAN1. Figure 23.2 shows CANi message slot buffer (i = 0, 1) and CANi message slot (message slot) j (j = 0 to 15). Table 23.2 lists pin settings of the CAN module. The CPU cannot access the message slot directly. Allocate necessary message slot j to the CANi message slot buffer 0 or 1 and access the message slot j via the allocated address. The CiSBS register selects the message slot j to be allocated. The message slot buffer and message slot consist of 16 bytes shown in Figure 23.2.
CAN0
0 CAN clock f1 fCAN 1 PM25
Internal data bus
Baud rate prescaler
CAN0OUT Self-test control CAN0IN Acceptance filter CAN protocol controller CAN interrupt control circuit Message slots 0 to 15 Interrupt request
Message slot buffers 0, 1
CAN1
0 CAN clock f1 fCAN 1 PM25
Internal data bus
Baud rate prescaler
CAN1OUT Self-test control CAN1IN Acceptance filter CAN protocol controller CAN interrupt control circuit Message slots 0 to 15 Interrupt request
Message slot buffers 0, 1
PM25: Bit in the PM2 register
Figure 23.1
CAN Module Block Diagram for CAN0 and CAN1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi message slot 0 CANi message slot 1 CANi message slot 2 CANi message slot 3 CANi message slot 4 CANi message slot 5 CANi message slot 6 CANi message slot 7 CANi message slot 8 CANi message slot 9 CANi message slot 10 CANi message slot 11 CANi message slot 12 CANi message slot 13 CANi message slot 14 CANi message slot 15 Internal data bus CiSBS b7 to b4 CiSBS b3 to b0 CAN0 CANi message slot buffer 0 (16 bytes) CANi message slot buffer 1 (16 bytes) 01E0h 01EFh 01F0h 01FFh CAN1 0260h 026Fh 0270h 027Fh
CANi message slot buffer 0
CANi message slot buffer 0 standard ID0 (CiSLOT0_0) CANi message slot buffer 0 standard ID1 (CiSLOT0_1) CANi message slot buffer 0 extended ID0 (CiSLOT0_2) CANi message slot buffer 0 extended ID1 (CiSLOT0_3) CANi message slot buffer 0 extended ID2 (CiSLOT0_4) CANi message slot buffer 0 data length code (CiSLOT0_5) CANi message slot buffer 0 data 0 (CiSLOT0_6) CANi message slot buffer 0 data 1 (CiSLOT0_7) CANi message slot buffer 0 data 2 (CiSLOT0_8) CANi message slot buffer 0 data 3 (CiSLOT0_9) CANi message slot buffer 0 data 4 (CiSLOT0_10) CANi message slot buffer 0 data 5 (CiSLOT0_11) CANi message slot buffer 0 data 6 (CiSLOT0_12) CANi message slot buffer 0 data 7 (CiSLOT0_13) CANi message slot buffer 0 time stamp high-ordered (CiSLOT0_14) CANi message slot buffer 0 time stamp low-ordered (CiSLOT0_15)
CANi message slot j
CANi message slot 0 standardID0 CANi message slot 0 standardID1 CANi message slot 0 extendedID0 CANi message slot 0 extendedID1 CANi message slot 0 extendedID2 CANi message slot 0 data length code CAN protocol controller CANi message slot 0 data0 CANi message slot 0 data1 CANi message slot 0 data2 CANi message slot 0 data3 CANi message slot 0 data4 CANi message slot 0 data5 CANi message slot 0 data6 CANi message slot 0 data7 CANi message slot 0 time stamp high-ordered CANi message slot 0 time stamp low-ordered CANi message slot 15 time stamp low-ordered
CANi message slot buffer 1
CANi message slot buffer 1 standard ID0 (CiSLOT1_0) CANi message slot buffer 1 standard ID1 (CiSLOT1_1) CANi message slot buffer 1 extended ID0 (CiSLOT1_2) CANi message slot buffer 1 extended ID1 (CiSLOT1_3) CANi message slot buffer 1 extended ID2 (CiSLOT1_4) CANi message slot buffer 1 data length code (CiSLOT1_5) CANi message slot buffer 1 data 0 (CiSLOT1_6) CANi message slot buffer 1 data 1 (CiSLOT1_7) CANi message slot buffer 1 data 2 (CiSLOT1_8) CANi message slot buffer 1 data 3 (CiSLOT1_9) CANi message slot buffer 1 data 4 (CiSLOT1_10) CANi message slot buffer 1 data 5 (CiSLOT1_11) CANi message slot buffer 1 data 6 (CiSLOT1_12) CANi message slot buffer 1 data 7 (CiSLOT1_13) CANi message slot buffer 1 time stamp high-ordered (CiSLOT1_14) CANi message slot buffer 1 time stamp low-ordered (CiSLOT1_15)
i = 0, 1 j = 0 to 15
Figure 23.2
Message Slots and Message Slot Buffers for CAN0 and CAN1
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 23.2
Port P7_6 P7_7 P8_2 P8_3 P9_5 P9_6
23. CAN Module
Pin Settings(1)
Bit and Setting Function CAN0OUT CAN0IN CAN0OUT CAN1OUT CAN0IN CAN1IN CAN1OUT - PD7_7 = 0 - - PD8_3 = 0 PD8_3 = 0 - PD7 to PD9 Registers(2) PSC, PSC2, PSL1 to PSL3 PSC3 Registers Registers PSC_6 = 1 - PSC2_2 = 0 PSC2_2 = 1 - - - PSC3_6 = 1 PSL1_6 = 0 - PSL2_2 = 1 PSL2_2 = 1 - - PSL3_5 = 0 - PS1 to PS3 Registers(2) PS1_6 = 1 PS1_7 = 0 PS2_2 = 1 PS2_2 = 1 - - PS3_5 = 0 PS3_6 = 1 - IPS3 = 0 - - IPS3 = 1 IPSA_3 = 1 IPSA_3 = 0 - IPS, IPSA Registers
CAN1IN / CAN1WU PD9_5 = 0
NOTES: 1. Set the registers from the left column sequentially. 2. Set the PD9 or PS3 register immediately after setting the PRC2 bit in the PRCR register to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1
CAN-Associated Registers
Figures 23.3 to 23.19, 23.21 to 23.27, and 23.30 to 23.36 show the CAN-associated registers. Refer to 23.2 CAN Clock and CPU Clock for details.
23.1.1
CANi Control Register 0 (CiCTLR0 Register) (i = 0, 1)
CANi Control Register 0 (i = 0, 1)
b15 b8 b7 b0
Symbol C0CTLR0 C1CTLR0
Bit Symbol RESET0 Bit Name CAN reset bit 0 (2)
Address 0201h - 0200h 0281h - 0280h
Function 0: CAN module is out of reset 1: CAN module is reset 0: Loop back function disabled 1: Loop back function enabled
After Reset(1) XXXX 0000 XX01 0X01b XXXX 0000 XX01 0X01b
RW RW
0
LOOPBACK
Loop back mode select bit Unimplemented. Write 0. Read as undefined value. BasicCAN mode select bit
RW
- (b2)
BASICCAN
-
0: BasicCAN mode function disabled 1: BasicCAN mode function enabled 0: CAN module is out of reset 1: CAN module is reset Set to 0
RW
RESET1
CAN reset bit 1 (2)
RW
- (b5) - (b7-b6)
TSPRE0
Reserved bit Unimplemented. Write 0. Read as undefined value.
RW
-
b9 b8
Time stamp prescaler select bits TSPRE1
0 0: CAN bus bit clock 0 1: CAN bus bit clock divided by 2 selected 1 0: CAN bus bit clock divided by 3 selected 1 1: CAN bus bit clock divided by 4 selected 0: Nothing occurs 1: The CiTSR register becomes 0000h, then this bit is automatically set back to 0 0: Nothing occurs 1: Registers CiTEC and CiREC become 00h, then this bit is automatically set back to 0
RW
RW
TSRESET
Time stamp counter reset bit
RW
ECRESET
Error counter reset bit Unimplemented. Write 0. Read as undefined value.
RW
- (b15-b12)
-
NOTES: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set both the RESET1 and RESET0 bits to the same value simultaneously.
Figure 23.3
C0CTLR0 and C1CTLR0 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.1.1 RESET1 and RESET0 Bits
When both the RESET1 and RESET0 bits are set to 1 (CAN module is reset), the CAN module is immediately reset regardless of ongoing CAN communication. After both the RESET1 and RESET0 bits are set to 1 and the CAN module reset is completed, the CiTSR register (i = 0, 1) becomes 0000h. Also, registers CiTEC and CiREC become 00h and both the STATE_ERRPAS and STATE_BUSOFF bits in the CiSTR register become 0. When both the RESET1 and RESET0 bits are changed from 1 to 0, the CiTSR register starts counting and the CAN module is permitted to communicate after 11 consecutive recessive bits have been detected. NOTES: 1. Set the same value to both the RESET1 and RESET0 bits simultaneously. 2. Ensure that the STATE_RESET bit in the CiSTR register becomes 1 (CAN module is in reset) after both the RESET1 and RESET0 bits are set to 1. 3. The CANiOUT pin outputs a high-level ("H") signal as soon as both the RESET1 and RESET0 bits are set to 1. CAN bus error may occur by setting both the RESET1 and RESET0 bits to 1 while the CAN frame is being transmitted. 4. To select pins CANiIN and CANiOUT for CAN communication, set registers PS1, PS2, PS3, PSL1, PSL2, PSL3, PSC, PSC2, PSC3, IPS, IPSA, PD7, PD8, and PD9 while the STATE_RESET bit is 1 (CAN module is in reset).
23.1.1.2 LOOPBACK Bit
When the LOOPBACK bit is set to 1 (loopback function enabled) and the receive message slot has the identifier (ID) and frame format matched with a transmitted frame, the transmitted frame is stored to the receive message slot. NOTES: 1. No ACK for the transmitted frame is returned. 2. Change the LOOPBACK bit setting while the STATE_RESET bit is 1 (CAN module is in reset).
23.1.1.3 BASICCAN Bit
When the BASICCAN bit is set to 1, the message slots 14 and 15 enter BasicCAN mode. In BasicCAN mode, the message slots 14 and 15 are configured as double buffered. Acceptance filtering permits the receive frames having the matching IDs to be stored into the message slots 14 and 15 alternately. Both data frame and remote frame can be received. Use the following procedure to enter BasicCAN mode. (1) Set the BASICCAN bit to 1. (2) Set the same ID to the message slots 14 and 15. (3) Set the same values in registers CiLMAR0 to CiLMAR4 and CiLMBR0 to CiLMBR4. (4) Set the same value to bits IDE14 and IDE15 in the CiIDR register. (5) Set registers CiMCTL14 and CiMCTL15 to receive a data frame. NOTES: 1. Change the BASICCAN bit setting while the STATE_RESET bit is 1 (CAN module is in reset). 2. The message slot 14 is the first slot to become active after both the RESET1 and RESET0 bits are set to 0. 3. The message slots 0 to 13 are not affected by entering BasicCAN mode.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.1.4
TSPRE1 and TSPRE0 Bits
Bits TSPRE1 and TSPRE0 determine the count source of the time stamp counter. NOTE: 1. Change bits TSPRE1 and TSPRE0 setting while the STATE_RESET bit is 1 (CAN module is in reset).
23.1.1.5
TSRESET Bit
When the TSRESET bit is set to 1 (count reset), the CiTSR register becomes 0000h. The TSRESET bit is automatically set back to 0 after the CiTSR register becomes 0000h.
23.1.1.6
ECRESET Bit
When the ECRESET bit is set to 1, registers CiTEC and CiREC become 00h and the CAN module are forcibly placed in an error active state. The ECRESET bit is automatically set back to 0 after the CAN module enters an error active state. NOTES: 1. Once entering an error active state, the CAN module is permitted to communicate after 11 consecutive recessive bits have been detected on the CAN bus. 2. Set the ECRESET bit to 1 while the CAN module is in a bus-off or bus-idle state. Do not set the ECRESET bit to 1 while the CAN module is transmitting or receiving.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.2
CANi Control Register 1 (CiCTLR1 Register) (i = 0, 1)
CANi Control Register 1 (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol C0CTLR1 C1CTLR1
Bit Symbol Bit Name
Address 0241h 0251h
Function
After Reset(1) X000 00XXb X000 00XXb
RW
- (b1-b0) - (b2)
BANKSEL
Unimplemented. Write 0. Read as undefined value. Reserved bit Set to 0 0: Message slot control register and single-shot register selected 1: Mask register selected Set to 0 0: Output 3 types of interrupt via OR gate 1: Output 3 types of interrupt individually
-
RW
CANi bank switch bit
RW
- (b5-b4)
INTSEL
Reserved bits
RW
CANi interrupt mode select bit
RW
- (b7)
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1.The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.4
C0CTLR1 and C1CTLR1 Registers
23.1.2.1
BANKSEL Bit
The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 0220h to 023Fh. The BANKSEL bit in the C1CTLR1 register selects the registers allocated to addresses 02A0h to 02BFh. Registers CiSSCTLR, CiSSSTR, and CiMCTL0 to CiMCTL15 can be accessed by setting the BANKSEL bit to 0. Registers CiGMR0 to CiGMR4, CiLMAR0 to CiLMAR4, and CiLMBR0 to CiLMBR4 can be accessed by setting the BANKSEL bit to 1.
23.1.2.2
INTSEL Bit
The INTSEL bit determines whether three types of interrupts (CANi transmit interrupt, CANi receive interrupt and CANi error interrupt) are output via OR gate or output individually. Refer to 23.4 CAN Interrupts for details. NOTE: 1. Change the INTSEL bit setting when the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.3
CANi Sleep Control Register (CiSLPR Register) (i = 0, 1)
CANi Sleep Control Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLPR C1SLPR
Bit Symbol SLEEP - (b7-b1) Bit Name Sleep mode control bit
Address 0242h 0252h
Function 0: Sleep mode entered 1: Sleep mode exited(1)
After Reset XXXX XXX0b XXXX XXX0b
RW RW
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. Perform the initialization for the CAN module after CAN sleep mode is exited. While the CAN0 module is in sleep mode, no SFR associated with CAN0 (allocated in addresses 01E0h to 0245h) can be accessed, except for the C0SLPR register. While the CAN1 module is in sleep mode, no SFR associated with CAN1 (allocated in addresses 0250h to 02BFh) can be accessed, except for the C1SLPR register.
Figure 23.5
C0SLPR and C1SLPR Registers
23.1.3.1
SLEEP Bit
When the SLEEP bit is set to 0, the clock is not supplied to the CAN module and the CAN module enters sleep mode. When the SLEEP bit is set to 1, the clock is supplied to the CAN module and the CAN module exits sleep mode. NOTE: 1. Enter sleep mode after the STATE_RESET bit in the CiSTR register becomes 1 (CAN module is in reset).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.4
CANi Status Register (CiSTR Register) (i = 0, 1)
CANi Status Register (i = 0, 1)
b15 b8 b7 b0
Symbol C0STR C1STR
Bit Symbol MBOX0 Bit Name
Address 0203h - 0202h 0283h - 0282h
Function
b3 b2 b1 b0
After Reset(1) X000 0X01 0000 0000b X000 0X01 0000 0000b
RW RO
MBOX1 Active slot determinate bits MBOX2
MBOX3
0 0 0 0: Message slot 0 0 0 0 1: Message slot 1 0 0 1 0: Message slot 2 0 0 1 1: Message slot 3 . . . . . . . . 1 1 0 0: Message slot 12 1 1 0 1: Message slot 13 1 1 1 0: Message slot 14 1 1 1 1: Message slot 15
b5 b4
RO
RO
RO
TRMSUCC Transmit/Receive complete state flag RECSUCC
RO
0 0: Hasn't yet transmitted nor received 0 1: Transmit operation completed 1 0: Receive operation completed
RO
TRMSTATE
Transmit state flag
0: Not transmitting 1: While transmitting 0: Not receiving 1: While receiving 0: CAN module is not in reset 1: CAN module is in reset 0: Not in Loop back mode 1: Loop back mode
RO
RECSTATE
Receive state flag
RO
STATE_RESET
CAN reset state flag
RO
STATE_LOOPBACK Loop back state flag - (b10) STATE_BASICCAN
RO
Unimplemented. Write 0. Read as undefined value. BasicCAN state flag 0: Not in BasicCAN mode 1: BasicCAN mode 0: No error occurred 1: Error occurred 0: Not in error passive state 1: In Error passive state 0: Not in bus-off state 1: Bus-off state
-
RO
STATE_BUSERROR CAN bus error state flag
RO
STATE_ERRPAS
Error passive state flag
RO
STATE_BUSOFF - (b15)
Bus-off state flag
RO
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.6
C0STR and C1STR Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.4.1
MBOX3 to MBOX0 Bits
When a transmit operation is completed or a received data is stored, bits MBOX3 to MBOX0 indicate the memory slot number which is used for the operation.
23.1.4.2
TRMSUCC Bit
The TRMSUCC bit becomes 1 when a transmit operation is successfully completed. The TRMSUCC bit becomes 0 when a receive operation is successfully completed.
23.1.4.3
RECSUCC Bit
The RECSUCC bit becomes 1 when a receive operation is successfully completed (regardless of whether a receive message has been stored in the message slot). When a message transmitted in loopback mode is received, the TRMSUCC bit becomes 1 and the RECSUCC bit becomes 0. The RECSUCC bit becomes 0 when a transmit operation is successfully completed.
23.1.4.4
TRMSTATE Bit
The TRMSTATE bit becomes 1 when the CAN module is operating as a transmit node. The TRMSTATE bit becomes 0 when the CAN module is in a bus-idle state or starts operating as a receive node.
23.1.4.5
RECSTATE Bit
The RECSTATE bit becomes 1 when the CAN module is operating as a receive node. The RECSTATE bit becomes 0 when the CAN module is in a bus-idle state or starts operating as a transmit node.
23.1.4.6
STATE_RESET Bit
After both the RESET1 and RESET0 bits are set to 1 (CAN module is reset), the STATE_RESET bit becomes 1 as soon as the CAN module reset is completed. The STATE_RESET bit becomes 0 when both the RESET1 and RESET0 bits are set to 0 (CAN module is out of reset).
23.1.4.7
STATE_LOOPBACK Bit
The STATE_ LOOPBACK bit is 1 while the CAN module is operating in loopback mode. The STATE_LOOPBACK bit becomes 1 when the LOOPBACK bit in the CiCTLR0 register is set to 1 (loop back function enabled). The STATE_LOOPBACK bit becomes 0 when the LOOPBACK bit is set to 0 (loop back function disabled).
23.1.4.8
STATE_BASICCAN Bit
The STATE_BASICCAN bit is 1 while the CAN module is operating in BasicCAN mode. Refer to 23.1.1.3 BASICCAN Bit for information about BasicCAN mode. The STATE_BASICCAN bit becomes 0 when the BASICCAN bit is set to 0 (BasicCAN mode function disabled). The STATE_BASICCAN bit becomes 1 when the BASICCAN bit is set to 1 (BasicCAN mode function enabled) and registers CiMCTL14 and CiMCTL15 are set to receive a data frame.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.4.9
STATE_BUSERROR Bit
The STATE_BUSERROR bit becomes 1 when a CAN communication error is detected. The STATE_BUSERROR bit becomes 0 when transmit and receive operations are successfully completed (regardless of whether a receive message has been stored in the message slot). NOTE: 1. When the STATE_BUSERROR bit is 1, the STATE_BUSERROR bit remains unchanged even if both the RESET1 and RESET0 bits are set to 1 (CAN module is reset).
23.1.4.10 STATE_ERRPAS Bit
The STATE_ERRPAS bit becomes 1 when the value of the CiTEC or CiREC register (i = 0, 1) exceeds 127 which results in the CAN module to be placed in an error-passive state. The STATE_ERRPAS bit becomes 0 when the CAN module exits an error-passive state to enter another error state. The STATE_ERRPAS bit becomes 0 when both the RESET1 and RESET0 bits are set to 1 (CAN module is reset).
23.1.4.11 STATE_BUSOFF Bit
The STATE_BUSOFF bit becomes 1 when the value of the CiTEC register exceeds 255 which results in the CAN module to be placed in a bus-off state. The STATE_BUSOFF bit becomes 0 when the CAN module exits a bus-off state to enter an error-active state. The STATE_BUSOFF bit becomes 0 when both the RESET1 and RESET0 bits are set to 1 (CAN module is reset).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.5
CANi Extended ID Register (CiIDR Register) (i = 0, 1)
CANi Extended ID Register(1) (i = 0,1)
b15 b8 b7 b0
Symbol C0IDR C1IDR
Bit Symbol IDE15 Bit Name Extended ID15 (message slot 15) Extended ID14 (message slot 14) Extended ID13 (message slot 13) Extended ID12 (message slot 12) Extended ID11 (message slot 11) Extended ID10 (message slot 10) Extended ID9 (message slot 9) Extended ID8 (message slot 8) Extended ID7 (message slot 7) Extended ID6 (message slot 6) Extended ID5 (message slot 5) Extended ID4 (message slot 4) Extended ID3 (message slot 3) Extended ID2 (message slot 2) Extended ID1 (message slot 1) Extended ID0 (message slot 0)
Address 0205h - 0204h 0285h - 0284h
Function
After Reset(2) 0000h 0000h
RW RW
Determine whether the corresponding message slot is the standard format or extended format 0: Standard format 1: Extended format
IDE14
RW
IDE13
RW
IDE12
RW
IDE11
RW
IDE10
RW
IDE9
RW
IDE8
RW
IDE7
RW
IDE6
RW
IDE5
RW
IDE4
RW
IDE3
RW
IDE2
RW
IDE1
RW
IDE0
RW
NOTES: 1. Change the CiIDR register while the CiMCTLj register (j = 0 to 15) of the corresponding message slot to the bit to be changed, is set to 00h. 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.7
C0IDR and C1IDR Registers
Bits in the CiIDR register determine a frame format used in the message slot corresponding to the individual bit. The standard format is selected when the bit is set to 0. The extended format is selected when the bit is set to 1.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 413 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.6
CANi Configuration Register (CiCONR Register) (i = 0, 1)
CANi Configuration Register (i = 0, 1)(1)
b15 b8 b7 b0
Symbol C0CONR C1CONR
Bit Symbol - (b3-b0) SAM Bit Name
Address 0207h - 0206h 0287h - 0286h
Function
After Reset(2) 0000 0000 0000 XXXXb 0000 0000 0000 XXXXb
RW -
Unimplemented. Write 0. Read as undefined value. Sampling count 0: Sample once 1: Sample three times
b7 b6 b5
RW
PTS0
PTS1
Propagation time segment
PTS2
0 0 0: 1Tq 0 0 1: 2Tq 0 1 0: 3Tq 0 1 1: 4Tq 1 0 0: 5Tq 1 0 1: 6Tq 1 1 0: 7Tq 1 1 1: 8Tq
RW
RW
RW
PBS10
b10 b9 b8
PBS11
Phase buffer segment 1
PBS12
0 0 0: Do not set to this value 0 0 1: 2Tq 0 1 0: 3Tq 0 1 1: 4Tq 1 0 0: 5Tq 1 0 1: 6Tq 1 1 0: 7Tq 1 1 1: 8Tq 0 0 0: Do not set to this value 0 0 1: 2Tq 0 1 0: 3Tq 0 1 1: 4Tq 1 0 0: 5Tq 1 0 1: 6Tq 1 1 0: 7Tq 1 1 1: 8Tq
RW
RW
RW
PBS20
b13 b12 b11
RW
PBS21
Phase buffer segment 2
RW
PBS22
RW
SJW0 Resynchronization jump width SJW1
b15 b14
0 0: 1Tq 0 1: 2Tq 1 0: 3Tq 1 1: 4Tq
RW
RW
NOTES: 1. Set the CiCONR register while the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.8
C0CONR and C1CONR Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.6.1
SAM Bit
The SAM bit determines the number of sampling points to be taken per bit. When the SAM bit is set to 0, only one sample is taken per bit at the end of the Phase Buffer Segment 1 (PBS1) to determine the value of the bit. When the SAM bit is set to 1, three samples per bit are taken; one time quantum and two time quanta before the end of PBS1, and at the end of PBS1. The value detected twice or more becomes the value of the sampled bit.
23.1.6.2
PTS2 to PTS0 Bits
Bits PTS2 to PTS0 determine the number of Tq for PTS.
23.1.6.3
PBS12 to PBS10 Bits
Bits PBS12 to PBS10 determine the number of Tq for PBS1. Set bits PBS12 to PBS10 to other than 000b.
23.1.6.4
PBS22 to PBS20 Bits
Bits PBS22 to PBS20 determine the number of Tq for PBS2. Set bits PBS22 to PBS20 to other than 000b.
23.1.6.5
Table 23.3
Baud Rate 1 Mbps
SJW1 and SJW0 Bits
Bit Timing when CAN Clock = 30 MHz
BRP 1 1 1 2 2 2 Tq (ns) 66.7 66.7 66.7 100 100 100 100 100 100 133.3 133.3 133.3 166.7 166.7 166.7 200 200 200 Number of Tq Per Bit 15 15 15 10 10 10 20 20 20 15 15 15 12 12 12 10 10 10 PTS + PBS1 12 11 10 7 6 5 16 15 14 12 11 10 9 8 7 7 6 5 PBS2 2 3 4 2 3 4 3 4 5 2 3 4 2 3 4 2 3 4 Sampling Point 87% 80% 73% 80% 70% 60% 85% 80% 75% 87% 80% 73% 83% 75% 67% 80% 70% 60%
Bits SJW1 and SJW0 determine the number of Tq for SJW.
500 Kbps
2 2 2 3 3 3 4 4 4 5 5 5
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.7
CANi Baud Rate Prescaler (CiBRP Register) (i = 0, 1)
CANi Baud Rate Prescaler (i = 0, 1)(1)
b7 b0
Symbol C0BRP C1BRP
Function
Address 0217h 0297h
After Reset(2) 0000 0001b 0000 0001b
Setting Range 01h to FFh(3) RW RW
If the setting value is n, the CAN clock is divided by n+1.
NOTES: 1. Set the CiBRP register while the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module. 3. Do not set the CiBRP register to 00h (divide-by-1).
Figure 23.9
C0BRP and C1BRP Registers
The CiBRP register determines a Tq of the CAN bit time. BRP + 1 CAN clock 1 Tq x number of Tq per bit Tq: Time quantum BRP: Setting value of the CiBRP register (1 to 255)
Tq =
Baud rate =
Number of Tq per bit = SS + PTS + PBS1 + PBS2 The CAN bit time is comprised of the following four segments. (1) SS: Synchronization Segment This segment is used to monitor the falling edge of a bit in order to synchronize the various CAN modules. (2) PTS: Propagation Time Segment This segment is used to compensate for the physical delay times within the CAN network. The physical delay times within the network is twice the sum of the signal propagation delay on the CAN bus, the input comparator delay, and the output driver delay. (3) PBS1: Phase Buffer Segment 1 This segment is used to compensate for the edge phase error caused by the frequency error. If the falling edge of a bit comes in later than expected, PBS1 is lengthened by up to the resynchronization jump width. (4) PBS2: Phase Buffer Segment 2 This segment has the same functionality to PBS1. If the falling edge of a bit comes in sooner than expected, PBS2 is shortened by up to the resynchronization jump width.
* SJW: Resynchronization Jump Width
This is the amount of lengthening or shortening of the phase buffer segments to compensate for the phase error. Figure 23.10 shows a bit timing diagram.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 416 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CAN Bit Time
SS PTS PBS1 SJW Setting range of each segment CAN bit time = 8Tq to 25Tq SS = 1Tq PTS = 1Tq to 8Tq PBS1 = 2Tq to 8Tq PBS2 = 2Tq to 8Tq SJW = 1Tq to 4Tq Condition of PBS1 and PBS2: PBS1 PBS2 SJW Sampling point PBS2 SJW
Figure 23.10
Bit Timing Diagram
23.1.8
CANi Time Stamp Register (CiTSR Register) (i = 0, 1)
CANi Time Stamp Register (i = 0, 1)
b15 b8 b7 b0
Symbol C0TSR C1TSR
Address 0209h - 0208h 0289h - 0288h
Function
After Reset(1) 0000h 0000h
RW RO
Value of time stamp
NOTE: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.11
C0TSR and C1TSR Registers
The CiTSR register is a 16-bit counter. Bits TSPRE1 and TSPRE0 in the CiCTLR0 register determine the CAN bus bit clock divided by 1, 2, 3, or 4 as the count source. When a transmit or receive operation is completed, the value of the CiTSR register is automatically stored into the message slot. In loopback mode, the value of the CiTSR register is stored into the data frame receive message slot or remote frame receive message slot when a receive operation is completed, if the corresponding message slot is available to store the message. The value of the CiTSR register is not stored when a transmit operation is completed in loopback mode. The CiTSR register starts a counter increment when both the RESET1 and RESET0 bits in the CiCTLR0 register are set to 0 (CAN module is out of reset). The CiTSR register becomes 0000h in the following timings: * At the next count timing after the CiTSR register becomes FFFFh. * When both the RESET1 and RESET0 bits are set to 1 (CAN module is reset) by a program. * When the TSRESET bit in the CiCTLR0 register is set to 1 (CiTSR register reset) by a program. CAN bus bit clock = 1 CAN bit time
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 417 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.9
CANi Transmit Error Count Register (CiTEC Register) (i = 0, 1)
CANi Transmit Error Count Register (i = 0, 1)
b7 b0
Symbol C0TEC C1TEC
Address 020Ah 028Ah Function
After Reset(1) 00h 00h
RW RO
Transmit error count value
NOTE: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.12
C0TEC and C1TEC Registers
In an error active and an error passive state, a transmit error count value is stored into the CiTEC register. The count is decremented when a transmit operation is successfully completed and incremented when a transmit error occurs. In a bus-off state, the value in the CiTEC register is undefined. The CiTEC register becomes 00h when the CAN module is placed in an error active state again.
23.1.10 CANi Receive Error Count Register (CiREC Register) (i = 0, 1)
CANi Receive Error Count Register (i = 0, 1)
b7 b0
Symbol C0REC C1REC
Address 020Bh 028Bh
Function
After Reset(1) 00h 00h
RW RO
Receive error count value
NOTE: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.13
C0REC and C1REC Registers
In an error active and an error passive state, a receive error count value is stored into the CiREC register. The count is decremented when a receive operation is successfully completed and incremented when a receive error occurs. The CiREC register becomes 127 when a receive operation is successfully completed while the CiREC register equals or exceeds 128 (in an error passive state). In a bus-off state, the value in the CiREC register is undefined. The CiREC register becomes 00h when the CAN module is placed in an error active state again.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 418 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.11 CANi Slot Interrupt Status Register (CiSISTR Register) (i = 0, 1)
CANi Slot Interrupt Status Register (i = 0, 1)
b15 b8 b7 b0
Symbol C0SISTR C1SISTR
Bit Symbol SIS15 Bit Name
Address 020Dh - 020Ch 028Dh - 028Ch
Function Determines whether an interrupt of a corresponding message slot is requested or not. 0: Interrupt not requested 1: Interrupt requested (2)
After Reset(1) 0000h 0000h
RW RW
Message slot 15 interrupt request status bit Message slot 14 interrupt request status bit Message slot 13 interrupt request status bit Message slot 12 interrupt request status bit Message slot 11 interrupt request status bit Message slot 10 interrupt request status bit Message slot 9 interrupt request status bit Message slot 8 interrupt request status bit Message slot 7 interrupt request status bit Message slot 6 interrupt request status bit Message slot 5 interrupt request status bit Message slot 4 interrupt request status bit Message slot 3 interrupt request status bit Message slot 2 interrupt request status bit Message slot 1 interrupt request status bit Message slot 0 interrupt request status bit
SIS14
RW
SIS13
RW
SIS12
RW
SIS11
RW
SIS10
RW
SIS9
RW
SIS8
RW
SIS7
RW
SIS6
RW
SIS5
RW
SIS4
RW
SIS3
RW
SIS2
RW
SIS1
RW
SIS0
RW
NOTES: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set each bit to 0 by a program. Writing a 1 has no effect.
Figure 23.14
C0SISTR and C1SISTR Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
When using the CAN interrupt, the CiSISTR register (i = 0, 1) indicates which message slot has requested an interrupt. The SISj bit (j = 0 to 15) is not automatically set to 0 (interrupt not requested) even if the interrupt is acknowledged. Set the SISj bit to 0 by a program. Use the MOV instruction to set the SISj bits to 0. Write a 0 to the bit which is to set to 0, and write a 1 to the bit which is to remain unchanged. For example: To set the SIS0 bit in CAN0 to 0 mov.w #07FFFh, C0SISTR Refer to 23.4 CAN Interrupts for details.
23.1.11.1 Message Slot for Transmit Operation
The SISj bit becomes 1 (interrupt requested) when the value of the CiTSR register is stored into the message slot j after a transmit operation is completed.
23.1.11.2 Message Slot for Receive Operation
The SISj bit becomes 1 (interrupt requested) when the receive message is stored in the message slot j after a receive operation is completed. NOTES: 1. If the RSPLOCK bit in registers CiMCTL0 to CiMCTL15 is set to 0 (automatic answering to the remote frame enabled), the SISj bit becomes 1 both when the remote frame receive operation is completed and when the following data frame transmit operation is completed. 2. In the remote frame transmit message slot, the SISj bit becomes 1 both when the remote frame transmit operation is completed and when the data frame receive operation is completed. 3. If an interrupt generation (the SISj bit becomes 1) and writing a 0 to the SISj bit by a program occur simultaneously, the SISj bit becomes 1. 4. Regardless of whether the SIMj bit in the CiSIMKR register is set to 0 (interrupt request masked) or to 1 (interrupt request enabled), the SISj bit becomes 1 at the completion of the transmit operation or at the completion of the receive operation.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.12 CANi Slot Interrupt Mask Register (CiSIMKR Register) (i = 0, 1)
CANi Slot Interrupt Mask Register (i = 0, 1)(1)
b15 b8 b7 b0
Symbol C0SIMKR C1SIMKR
Bit Symbol SIM15 Bit Name
Address 0211h - 0210h 0291h - 0290h
Function
After Reset(2) 0000h 0000h
RW RW
Message slot 15 interrupt request mask bit Message slot 14 interrupt request mask bit Message slot 13 interrupt request mask bit Message slot 12 interrupt request mask bit Message slot 11 interrupt request mask bit Message slot 10 interrupt request mask bit Message slot 9 interrupt request mask bit Message slot 8 interrupt request mask bit Message slot 7 interrupt request mask bit Message slot 6 interrupt request mask bit Message slot 5 interrupt request mask bit Message slot 4 interrupt request mask bit Message slot 3 interrupt request mask bit Message slot 2 interrupt request mask bit Message slot 1 interrupt request mask bit Message slot 0 interrupt request mask bit
SIM14
Controls whether an interrupt request of the corresponding message slot is enabled or masked. 0: Interrupt request masked (disabled) 1: Interrupt request enabled
RW
SIM13
RW
SIM12
RW
SIM11
RW
SIM10
RW
SIM9
RW
SIM8
RW
SIM7
RW
SIM6
RW
SIM5
RW
SIM4
RW
SIM3
RW
SIM2
RW
SIM1
RW
SIM0
RW
NOTES: 1. Set the CiSIMKR register while the CiMCTLj (j = 0 to 15) register of the corresponding message slot to the bit to be changed, is set to 00h. 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.15
C0SIMKR and C1SIMKR Registers
The CiSIMKR register determines whether an interrupt request generated by completing a transmit/receive operation in the corresponding message slot is enabled or disabled. When the SIMj bit (j = 0 to 15) is set to 1 (interrupt request enabled), an interrupt request generated by completing a transmit operation or a receive operation in the corresponding message slot is enabled. Refer to 23.4 CAN Interrupts for details.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 421 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.13 CANi Error Interrupt Mask Register (CiEIMKR Register) (i = 0, 1)
CANi Error Interrupt Mask Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0EIMKR C1EIMKR
Bit Symbol BOIM Bit Name Bus-off interrupt mask bit Error-passive interrupt mask bit CAN bus-error interrupt mask bit
Address 0214h 0294h
Function 0: Interrupt request masked (disabled) 1: Interrupt request enabled 0: Interrupt request masked (disabled) 1: Interrupt request enabled 0: Interrupt request masked (disabled) 1: Interrupt request enabled
After Reset(1) XXXX X000b XXXX X000b
RW RW
EPIM
RW
BEIM - (b7-b3)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.16
C0EIMKR and C1EIMKR Registers
23.1.13.1 BOIM Bit
The BOIM bit determines whether an interrupt request is enabled or disabled when the CAN module is placed in a bus-off state. When the BOIM bit is set to 1, a bus-off interrupt request is enabled.
23.1.13.2 EPIM Bit
The EPIM bit determines whether an interrupt request is enabled or disabled when the CAN module is placed in an error passive state. When the EPIM bit is set to 1, an error passive interrupt request is enabled.
23.1.13.3 BEIM Bit
The BEIM bit determines whether an interrupt request is enabled or disabled when a CAN bus error occurs. When the BEIM bit is set to 1, a CAN bus error interrupt request is enabled. Refer to 23.4 CAN Interrupts for details.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.14 CANi Error Interrupt Status Register (CiEISTR Register) (i = 0, 1)
CANi Error Interrupt Status Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0EISTR C1EISTR
Bit Symbol BOIS Bit Name Bus-off interrupt status bit Error-passive interrupt status bit CAN bus-error interrupt status bit
Address 0215h 0295h
Function 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2) 0: Interrupt not requested 1: Interrupt requested (2)
After Reset(1) XXXX X000b XXXX X000b
RW RW
EPIS
RW
BEIS - (b7-b3)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set each bit to 0 by a program. Writing a 1 has no effect.
Figure 23.17
C0EISTR and C1EISTR Registers
When using the CAN interrupt, the CiEISTR register determines an error interrupt source. Bits BOIS, EPIS, and BEIS are not automatically set to 0 (interrupt not requested) even if the interrupt is acknowledged. Set these bits to 0 by a program. Use the MOV instruction to set each bit in the CiEISTR register to 0. Write a 0 to the bit which is to set to 0, and write a 1 to the bit which is to remain unchanged. For example: To set the BOIS bit in CAN0 to 0 mov.b #006h, C0EISTR Refer to 23.4 CAN Interrupts for details.
23.1.14.1 BOIS Bit
The BOIS bit becomes 1 when the CAN module is placed in a bus-off state. NOTE: 1. Regardless of whether the BOIM bit in the CiEIMKR register is set to 0 (interrupt request masked) or 1 (interrupt request enabled), the BOIS bit becomes 1 when the CAN module becomes a bus-off state.
23.1.14.2 EPIS Bit
The EPIS bit becomes 1 when the CAN module is placed in an error passive state. NOTE: 1. Regardless of whether the EPIM bit in the CiEIMKR register is set to 0 (interrupt request masked) or 1 (interrupt request enabled), the EPIS bit becomes 1 when the CAN module becomes an error-passive state.
23.1.14.3 BEIS Bit
The BEIS bit becomes 1 when a CAN bus error is detected. NOTE: 1. Regardless of whether the BEIM bit in the CiEIMKR register is set to 0 (interrupt request masked) or 1 (interrupt request enabled), the BEIS bit becomes 1 when the CAN bus error is detected.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 423 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.15 CANi Error Source Register (CiEFR Register) (i = 0, 1)
CANi Error Source Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0EFR C1EFR
Bit Symbol ACKE Bit Name ACK error detect bit
Address 0216h 0296h
Function 0: ACK error not detected 1: ACK error detected(2) 0: CRC error not detected 1: CRC error detected(2) 0: FORM error not detected 1: FORM error detected(2) 0: Stuff error not detected 1: Stuff error detected (2)
After Reset(1) 00h 00h
RW RW
CRCE
CRC error detect bit
RW
FORME
FORM error detect bit
RW
STFE
Stuff error detect bit
RW
BITE0
Bit error detect bit 0
0: Bit error not detected while transmitting recessive "H" 1: Bit error detected while transmitting recessive "H"(2) 0: Bit error not detected while transmitting dominant "L" 1: Bit error detected while transmitting dominant "L"(2) 0: Error not detected while receiving 1: Error detected while receiving (2) 0: Error not detected while receiving 1: Error detected while receiving (2)
RW
BITE1
Bit error detect bit 1
RW
RCVE
Receive error detect bit
RW
TRE
Transmit error detect bit
RW
NOTES: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module. 2. Set each bit to 0 by a program. Writing a 1 has no effect.
Figure 23.18
C0EFR and C1EFR Registers
The CiEFR register determines an error source when a CAN bus error occurs. Set each bit in the CiEFR register to 0 after reading the CiEFR register by a program. Use the MOV instruction to set each bit in the CiEFR register to 0. Write a 0 to the bit which is to set to 0, and write a 1 to the bit which is to remain unchanged. For example: To set the ACKE bit in CAN0 to 0 mov.b #0FEh, C0EFR
23.1.15.1 ACKE Bit
The ACKE bit becomes 1 when an ACK error is detected.
23.1.15.2 CRCE Bit
The CRC bit becomes 1 when a CRC error is detected.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 424 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.15.3 FORME Bit
The FORME bit becomes 1 when a FORM error is detected.
23.1.15.4 STFE Bit
The STFE bit becomes 1 when a stuff error is detected.
23.1.15.5 BITE0 Bit
The BITE0 bit becomes 1 when a bit error is detected while transmitting recessive "H".
23.1.15.6 BITE1 Bit
The BITE1 bit becomes 1 when a bit error is detected while transmitting dominant "L".
23.1.15.7 RCVE Bit
The RCVE bit becomes 1 when a CAN bus error is detected while receiving.
23.1.15.8 TRE Bit
The TRE bit becomes 1 when a CAN bus error is detected while transmitting.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 425 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.16 CANi Mode Register (CiMDR Register) (i = 0, 1)
CANi Mode Register (i = 0, 1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0MDR C1MDR
Bit Symbol Bit Name
Address 0219h 0299h
Function
b1 b0
After Reset(2) XXXX XX00b XXXX XX00b
RW RW
CMOD
CAN operating mode select bit
0 0: Normal operating mode 0 1: Bus monitoring mode 1 0: Self-test mode 1 1: Do not set to this value
RW
- (b7-b2)
Unimplemented. Write 0. Read as undefined value.
-
NOTES: 1. Set the CiMDR register while the STATE_RESET bit in the CiSTR register is 1 (CAN module is in reset). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.19
C0MDR and C1MDR Registers
23.1.16.1 CMOD Bit
The CMOD bit selects a CAN operating mode. * Normal operating mode: Normal transmit and receive operations are enabled. * Bus monitoring mode(1): Only receive operation is enabled. Output signal from the CANiOUT pin is fixed to high level ("H") in bus monitoring mode. The CAN module transmits neither ACK nor error frame. * Self-test mode: The CAN module connects the CANiOUT pin to the CANiIN pin internally. The CAN module can communicate without additional device when using self-test mode and loop back mode. Output signal from the CANiOUT pin is fixed to "H" in self-test mode while transmitting. Figure 23.20 shows an image diagram in self-test mode. NOTE: 1. Do not generate a transmit request in bus monitoring mode. The CAN module in bus monitoring mode considers dominant "L" is received regardless of whether the actual ACK bit is dominant "L" or recessive "H". Therefore, when a transmit operation is completed until EOF, the CAN module determines a receive operation is successfully completed even if the ACK bit is recessive "H".
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 426 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CAN Module
Self-test mode
CANiIN
CANiIN pin
ACK signal generation circuit CANiOUT CANiOUT pin
i = 0,1
Figure 23.20
Self-Test Mode
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 427 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.17 CANi Single-Shot Control Register (CiSSCTLR Register) (i = 0, 1)
CANi Single-Shot Control Register (i = 0, 1)(1, 2)
b15 b8 b7 b0
Symbol C0SSCTLR C1SSCTLR
Bit Symbol SSC15 Bit Name Message slot 15 single-shot control bit Message slot 14 single-shot control bit Message slot 13 single-shot control bit Message slot 12 single-shot control bit Message slot 11 single-shot control bit Message slot 10 single-shot control bit Message slot 9 single-shot control bit Message slot 8 single-shot control bit Message slot 7 single-shot control bit Message slot 6 single-shot control bit Message slot 5 single-shot control bit Message slot 4 single-shot control bit Message slot 3 single-shot control bit Message slot 2 single-shot control bit Message slot 1 single-shot control bit Message slot 0 single-shot control bit
Address 0221h - 0220h 02A1h - 02A0h
Function 0: Single-shot mode not used 1: Single-shot mode used
After Reset(3) 0000h 0000h
RW RW
SSC14
RW
SSC13
RW
SSC12
RW
SSC11
RW
SSC10
RW
SSC9
RW
SSC8
RW
SSC7
RW
SSC6
RW
SSC5
RW
SSC4
RW
SSC3
RW
SSC2
RW
SSC1
RW
SSC0
RW
NOTES: 1. Set the CiSSCTLR register while the CiMCTLj register (j = 0 to 15) of the corresponding message slot to the bit to be changed, is set to 00h. 2. The CiSSCTLR register can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 0 (message slot control register and single-shot register selected). 3. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 0.
Figure 23.21
C0SSCTLR and C1SSCTLR Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 428 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
According to the CAN Specification 2.0 Part B, if a transmit operation is aborted due to the arbitration lost or transmit error, the CAN module continues retransmitting until the transmit operation is successfully completed. When a transmit operation is failed, the frame can be retransmitted if the SSCj bit (j = 0 to 15) in the CiSSCTLR register is set to 0, and the frame cannot be retransmitted if the SSCj bit is set to 1.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 429 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.18 CANi Single-Shot Status Register (CiSSSTR Register) (i = 0, 1)
CANi Single-Shot Status Register (i = 0, 1)(1)
b15 b8 b7 b0
Symbol C0SSSTR C1SSSTR
Bit Symbol SSS15 Bit Name Message slot 15 single-shot status bit Message slot 14 single-shot status bit Message slot 13 single-shot status bit Message slot 12 single-shot status bit Message slot 11 single-shot status bit Message slot 10 single-shot status bit Message slot 9 single-shot status bit Message slot 8 single-shot status bit Message slot 7 single-shot status bit Message slot 6 single-shot status bit Message slot 5 single-shot status bit Message slot 4 single-shot status bit Message slot 3 single-shot status bit Message slot 2 single-shot status bit Message slot 1 single-shot status bit Message slot 0 single-shot status bit
Address 0225h - 0224h 02A5h - 02A4h
Function
After Reset(2) 0000h 0000h
RW RW
0: No Arbitration lost nor transmit error occurred 1: Arbitration lost or transmit error occurred (3)
SSS14
RW
SSS13
RW
SSS12
RW
SSS11
RW
SSS10
RW
SSS9
RW
SSS8
RW
SSS7
RW
SSS6
RW
SSS5
RW
SSS4
RW
SSS3
RW
SSS2
RW
SSS1
RW
SSS0
RW
NOTES: 1. The CiSSSTR register can be accessed when the BANKSEL bit in the CiCTLR1 is set to 0 (message slot control register and single-shot register selected). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 0. 3. Set each bit to 0 by a program. Writing a 1 has no effect.
Figure 23.22
C0SSSTR and C1SSSTR Registers
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 430 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
If a transmit operation is aborted due to the arbitration lost or transmit error, the bit corresponding to the message slot j (j = 0 to 15) becomes 1. Set each bit in the CiSSSTR register to 0 after reading the CiSSSTR register by a program. Use the MOV instruction to set the SSSj bit to 0. Write a 0 to the bit which is to set to 0, and write a 1 to the bit which is to remain unchanged. For example: To set the SSS0 bit in CAN0 to 0 mov.w #07FFFh, C0SSSTR
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 431 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.19 CANi Global Mask Register, CANi Local Mask Register A, and CANi Local Mask Register B (CiGMRk, CiLMARk, and CiLMBRk Registers) (i = 0,1, k = 0 to 4)
CANi Global Mask Register Standard ID0(1) (i = 0, 1) CANi Local Mask Register A Standard ID0(1) CANi Local Mask Register B Standard ID0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0GMR0, C1GMR0 C0LMAR0, C1LMAR0 C0LMBR0, C1LMBR0
Bit Symbol SID6M Bit Name Standard ID6
Address 0228h, 02A8h 0230h, 02B0h(3) 0238h, 02B8h(4)
Function 0: ID not checked 1: ID checked
After Reset(2) XXX0 0000b XXX0 0000b XXX0 0000b
RW RW
SID7M
Standard ID7
RW
SID8M
Standard ID8
RW
SID9M
Standard ID9
RW
SID10M - (b7-b5)
Standard ID10 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. Registers CiGMR0, CiLMAR0, and CiLMBR0 can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 1 (mask register selected). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 1. 3. The C0LMAR0 register shares the same address with the C0MCTL0 register, and the C1MAR0 register with the C1MCTL0 register. 4. The C0LMBR0 register shares the same address with the C0MCTL8 register, and the C1LMBR0 register with the C1MCTL8 register.
Figure 23.23
C0GMR0, C1GMR0, C0LMAR0, C1LMAR0, C0LMBR0, and C1LMBR0 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Global Mask Register Standard ID1(1) (i = 0, 1) CANi Local Mask Register A Standard ID1(1) CANi Local Mask Register B Standard ID1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0GMR1, C1GMR1 C0LMAR1, C1LMAR1 C0LMBR1, C1LMBR1
Bit Symbol SID0M Bit Name Standard ID0
Address 0229h, 02A9h 0231h, 02B1h(3) 0239h, 02B9h(4)
Function 0: ID not checked 1: ID checked
After Reset(2) XX00 0000b XX00 0000b XX00 0000b
RW RW
SID1M
Standard ID1
RW
SID2M
Standard ID2
RW
SID3M
Standard ID3
RW
SID4M
Standard ID4
RW
SID5M - (b7-b6)
Standard ID5 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. Registers CiGMR1, CiLMAR1, and CiLMBR1 can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 1 (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 1. 3. The C0LMAR1 register shares the same address with the C0MCTL1 register, and the C1LMAR1 register with the C1MCTL1 register. 4. The C0LMBR1 register shares the same address with the C0MCTL9 register, and the C1LMBR1 register with the C1MCTL9 register.
Figure 23.24
C0GMR1, C1GMR1, C0LMAR1, C1LMAR1, C0LMBR1, and C1LMBR1 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Global Mask Register Extended ID0(1) (i = 0, 1) CANi Local Mask Register A Extended ID0(1) CANi Local Mask Register B Extended ID0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0GMR2, C1GMR2 C0LMAR2, C1LMAR2 C0LMBR2, C1LMBR2
Bit Symbol EID14M Bit Name Extended ID14
Address 022Ah, 02AAh 0232h, 02B2h(3) 023Ah, 02BAh(4)
Function 0: ID not checked 1: ID checked
After Reset(2) XXXX 0000b XXXX 0000b XXXX 0000b
RW RW
EID15M
Extended ID15
RW
EID16M
Extended ID16
RW
EID17M - (b7-b4)
Extended ID17 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. Registers CiGMR2, CiLMAR2, and CiLMBR2 can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 1 (mask register selected). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 1. 3. The C0LMAR2 register shares the same address with the C0MCTL2 register, and the C1LMAR2 register with the C1MCTL2 register. 4. The C0LMBR2 register shares the same address with the C0MCTL10 register, and the C1LMBR2 register with the C1MCTL10 register.
Figure 23.25
C0GMR2, C1GMR2, C0LMAR2, C1LMAR2, C0LMBR2, and C1LMBR2 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Global Mask Register Extended ID1(1) (i = 0,1) CANi Local Mask Register A Extended ID1(1) CANi Local Mask Register B Extended ID1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0GMR3, C1GMR3 C0LMAR3, C1LMAR3 C0LMBR3, C1LMBR3
Bit Symbol EID6M Bit Name Extended ID6
Address 022Bh, 02ABh 0233h, 02B3h(3) 023Bh, 02BBh(4)
Function 0: ID not checked 1: ID checked
After Reset(2) 00h 00h 00h
RW RW
EID7M
Extended ID7
RW
EID8M
Extended ID8
RW
EID9M
Extended ID9
RW
EID10M
Extended ID10
RW
EID11M
Extended ID11
RW
EID12M
Extended ID12
RW
EID13M
Extended ID13
RW
NOTES: 1. Registers CiGMR3, CiLMAR3, and CiLMBR3 can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 1 (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 1. 3. The C0LMAR3 register shares the same address with the C0MCTL3 register, and the C1LMAR3 register with the C1MCTL3 register. 4. The C0LMBR3 register shares the same address with the C0MCTL11 register, and the C1LMBR3 register with the C1MCTL11 register.
Figure 23.26
C0GMR3, C1GMR3, C0LMAR3, C1LMAR3, C0LMBR3, and C1LMBR3 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Global Mask Register Extended ID2(1) (i = 0, 1) CANi Local Mask Register A Extended ID2(1) CANi Local Mask Register B Extended ID2(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0GMR4, C1GMR4 C0LMAR4, C1LMAR4 C0LMBR4, C1LMBR4
Bit Symbol EID0M Bit Name Extended ID0
Address 022Ch, 02ACh 0234h, 02B4h(3) 023Ch, 02BCh(4)
Function 0: ID not checked 1: ID checked
After Reset (2) XX00 0000b XX00 0000b XX00 0000b
RW RW
EID1M
Extended ID1
RW
EID2M
Extended ID2
RW
EID3M
Extended ID3
RW
EID4M
Extended ID4
RW
EID5M - (b7-b6)
Extended ID5 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. Registers CiGMR4, CiLMAR4, and CiLMBR4 can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 1 (mask register selected). 2. Value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 1. 3. The C0LMAR4 register shares the same address with the C0MCTL4 register, and the C1LMAR4 register with the C1MCTL4 register. 4. The C0LMBR4 register shares the same address with the C0MCTL12 register, and the C1LMBR4 register with the C1MCTL12 register.
Figure 23.27
C0GMR4, C1GMR4, C0LMAR4, C1LMAR4, C0LMBR4, and C1LMBR4 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
Registers CiGMRk, CiLMARk, and CiLMBRk (i = 0, 1, k = 0 to 4) are used for acceptance filtering. By using these registers, users are able to select which messages to receive. The CiGMRk register determines whether IDs in the message slots 0 to 13 are checked or not. The CiLMARk register determines whether ID in the message slot 14 is checked or not. The CiLMBRk register determines whether ID in the message slot 15 is checked or not. * When the bit in the CiGMRk, CiLMARk, or CiLMBRk register is set to 0, the corresponding bit (ID bit) in the CANi message slot j's (j = 0 to 15) standard ID0, standard ID1, or extended ID0 to extended ID2 is masked in acceptance filtering. (The corresponding bit is assumed to have a matching ID.) * When the bit in the CiGMRk, CiLMARk, CiLMBRk register is set to 1, the corresponding ID bit is compared with a received ID in acceptance filtering. When the received ID matches the ID set in the message slot j, the receive data is stored into the message slot having the matched ID. NOTES: 1. Change the CiGMRk register while none of the message slots 0 to 13 has a receive request. 2. Change the CiLMARk register while the message slot 14 has no receive request. 3. Change the CiLMBRk register while the message slot 15 has no receive request. 4. When there are two or more receive message slots which have the matched ID with the received message, the received message is stored into the smallest-numbered message slot. Figure 23.28 shows individual mask registers and corresponding message slots. Figure 23.29 shows the acceptance filtering.
CiGMRk register CiLMARk register CiLMBRk register
i = 0, 1 k = 0 to 4
Message slot 0 to Message slot 13 Message slot 14 Message slot 15
Figure 23.28
Individual Mask Registers and Message Slots
For Standard ID
Receive message ID ID set in the message slot
CiGMR register CiLMAR register CiLMBR register SID0M Value of the mask bit 0: Whether a receive message ID is matched is handled as "don't care" (or masked) 1: Whether a receive message ID is matched is verified
SID0 Standard ID0 SID1 Standard ID1
SID1M
Acceptance verify signal
SID10 Standard ID10
SID10M
Acceptance verify signal 0: Receive message is ignored (Message is stored into no message slot) 1: Receive message is stored into a message slot having a matched ID
Figure 23.29
Acceptance Filtering
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 437 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.20 CANi Message Slot j Control Register (CiMCTLj Register) (i = 0, 1, j = 0 to 15)
CANi Message Slot j Control Register (i = 0,1, j = 0 to 15)(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0MCTL0 to C0MCTL15 C1MCTL0 to C1MCTL15
Bit Symbol When transmitting, SENTDATA When receiving, NEWDATA When transmitting, TRMACTIVE When receiving, INVALDATA MSGLOST Bit Name
Address 0230h - 023Fh 02B0h - 02BFh(4)
(3)
After Reset(2) 00h 00h
Function RW
Transmit complete flag Receive complete flag
When transmitting 0: Transmit operation not completed 1: Transmit operation completed (5) When transmitting 0: Not transmitting 1: Transmitting
When receiving 0: Receive operation not completed 1: Receive operation completed(5) When receiving 0: Not storing receive data 1: Storing receive data
RW
Transmitting flag Receiving flag
RO
Overwrite flag
0: Overwrite not occurred 1: Overwrite occurred(5) Not in BasicCAN mode 0: Data frame 1: Remote frame In BasicCAN mode(6) 0: Data frame received (status) 1: Remote frame received (status) 0: Automatic answering to the remote frame enabled 1: Automatic answering to the remote frame disabled 0: Data frame transmitted/received 1: Remote frame transmitted/received 0: Receive operation not requested 1: Receive operation requested (7) 0: Transmit operation not requested 1: Transmit operation requested (7)
RW
REMACTIVE
Remote frame transmit/receive status flag
RO
RSPLOCK
Automatic answering disable mode select bit
RW
REMOTE
Remote frame set bit
RW
RECREQ
Receive request bit
RW
TRMREQ
Transmit request bit
RW
NOTES: 1. The CiMCTLj register can be accessed when the BANKSEL bit in the CiCTLR1 register is set to 0 (message slot control register and single-shot register selected). 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset, supplying the clock to the CAN module, and setting the BANKSEL bit to 0. 3. Registers C0MCTL0 to C0MCTL4 share addresses with registers C0LMAR0 to C0LMAR4, and registers C0MCTL8 to C0MCTL12 with registers C0LMBR0 to C0LMBR4 respectively. 4. Registers C1MCTL0 to C1MCTL4 share addresses with registers C1LMAR0 to C1LMAR4, and registers C1MCTL8 to C1MCTL12 with registers C1LMBR0 to C1LMBR4 respectively. 5. Set the bit to 0 by a program. Writing a 1 has no effect. 6. BasicCAN mode can be used with the message slot 14 and 15. 7. Do not set both the RECREQ and TRMREQ bits to 1 simultaneously.
Figure 23.30
C0MCTL0 to C0MCTL15 and C1MCTL0 to C1MCTL15 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 23.4
23. CAN Module
CiMCTLj Register (i = 0, 1, j = 0 to 15) Settings for Transmit/Receive Operation
Bit Setting in the CiMCTLj Register Transmit/Receive Operation Mode No transmit nor receive operation Data frame receive operation Remote frame receive operation Remote frame receive operation (Data frame is transmitted after remote frame is received.) Data frame transmit operation Remote frame transmit operation (Data frame is received after remote frame is transmitted.)
TRMREQ RECREQ REMOTE RSPLOCK MSGLOST SENTDATA NEWDATA 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
23.1.20.1 SENTDATA/NEWDATA Bit
The SENTDATA/NEWDATA bit indicates CAN message transmit/receive operation is completed. Set the SENTDATA/NEWDATA bit to 0 (transmit/receive operation not completed) by a program prior to transmitting or receiving. The SENTDATA/NEWDATA bit is not set to 0 automatically. While the TRMACTIVE/INVALDATA bit is 1 (transmitting or storing receive data), the SENTDATA/NEWDATA bit cannot be set to 0. SENTDATA: The SENTDATA bit becomes 1 (transmit operation completed) when a transmit operation is completed in the transmit message slot. NEWDATA: The NEWDATA bit becomes 1 (receive operation completed) after the message to be stored into the message slot j (j = 0 to 15) is successfully received. NOTES: 1. To read a receive data from the message slot j, set the NEWDATA bit to 0 before reading. If the NEWDATA bit becomes 1 while reading the message slot, this indicates that new receive data has been stored into the message slot while reading and the returned data contains an undefined value. In this case, discard the data with an undefined value and then read the message slot again after setting the NEWDATA bit to 0. 2. When the remote frame is transmitted or received, the SENTDATA/NEWDATA bit remains unchanged even after remote frame transmit or receive operation is completed. The SENTDATA/NEWDATA bit becomes 1 when the following data frame transmit or receive operation is completed.
23.1.20.2 TRMACTIVE/INVALDATA Bit
The TRMACTIVE/INVALDATA bit indicates that the CAN protocol controller is accessing the message slot j. The TRMACTIVE/INVALDATA bit becomes 1 when the controller is accessing, and becomes 0 when not accessing. TRMACTIVE: The TRMACTIVE bit becomes 1 (transmitting) when a transmit operation is started. The TRMACTIVE bit becomes 0 (not transmitting) when the CAN module loses arbitration, a CAN bus error occurs, or when a transmit operation is completed. INVALDATA: The INVALDATA bit becomes 1 (storing receive data) while the received message is being stored into the message slot j after the receive operation is completed. The INVALDATA bit becomes 0 (not storing receive data) when the receive data has been stored. While the INVALDTA bit is 1, a value read from the message slot j is undefined.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 439 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.20.3 MSGLOST Bit
The MSGLOST bit is enabled when the data frame receive operation or remote frame transmit operation (data frame is received after the remote frame is transmitted) shown in Table 23.4 is selected. The MSGLOST bit becomes 1 (overwrite occurred) when the message slot j (j = 0 to 15) is overwritten by a new receive data while the NEWDATA bit is 1 (receive operation completed). Set the MSGLOST bit to 0 (overwrite not occurred) after reading it by a program.
23.1.20.4 REMACTIVE Bit
The REMACTIVE bit becomes 1 (remote frame) when the message slot j is set for the remote frame transmit or receive operation, while the STATE_BASICCAN bit in the CiSTR register is 0 (not in BasicCAN mode). Then, the REMACTIVE bit becomes 0 (data frame) after the remote frame transmit or receive operation is completed. In BasicCAN mode, the REMACTIVE bit in the CiMCTL14 or CiMCTL15 register becomes 0 when the data frame is received, and becomes 1 when the remote frame is received.
23.1.20.5 RSPLOCK Bit
The RSPLOCK bit is enabled when the remote frame receive operation shown in Table 23.4 is selected. The RSPLOCK bit determines the operation after the remote frame is received. When the RSPLOCK bit is set to 0 (automatic answering to remote frame enabled), a slot automatically switches to a transmit slot after the remote frame is received and the message set in the message slot is automatically transmitted as the data frame. When the RSPLOCK bit is set to 1 (automatic answering to remote frame disabled), the message is not automatically transmitted after the remote frame is received. Set the RSPLOCK bit to 0 when any transmit/receive mode other than remote frame receive mode is selected.
23.1.20.6 REMOTE Bit
The REMOTE bit determines transmit/receive mode shown in Table 23.4. Set the REMOTE bit to 0 to transmit or receive the data frame. Set it to 1 to transmit or receive the remote frame. The following occurs when the remote frame is transmitted or received. * Transmitting the remote frame A message set in the message slot j is transmitted as the remote frame. After a transmit operation is completed, the slot automatically switches to a data frame receive message slot. If the data frame is received before a remote frame transmit operation is completed, the data frame is stored into the message slot j and the remote frame is not transmitted. * Receiving the remote frame The message slot receives the remote frame. The RSPLOCK bit determines the operation after the remote frame is received.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 440 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.20.7 RECREQ Bit
The RECREQ bit determines transmit/receive mode shown in Table 23.4. When the RECREQ bit is set to 1 (receive operation requested), the message slot is set to receive the data frame or remote frame. If the REMOTE bit is set to 1 (remote frame transmitted/received) and the RSPLOCK bit is set to 0 (automatic answering to the remote frame enabled), the data frame is transmitted automatically after the remote frame is received, regardless of the RECREQ bit setting to 0. Set the RECREQ bit to 0 (receive operation not requested) to transmit the data frame or remote frame. Do not set both the TRMREQ and RECREQ bits in the same message slot to 1.
23.1.20.8 TRMREQ Bit
The TRMREQ bit determines transmit/receive mode shown in Table 23.4. When the TRMREQ bit is set to 1 (transmit operation requested), the data frame or remote frame is transmitted. If the REMOTE bit is set to 0 (remote frame transmitted/received), the message slot automatically switches to a receive slot for the data frame after the remote frame is transmitted, regardless of the TRMREQ bit setting to 1. Set the TRMREQ bit to 0 (transmit operation not requested) to receive the data frame or remote frame. Do not set both the TRMREQ and RECREQ bits in the same message slot to 1. NOTES: 1. When a transmit operation request occurs in multiple message slots, the data frame or remote frame in the slot which has the smallest slot number is transmitted first. 2. In single-shot mode, if a transmit operation is aborted due to the arbitration lost or transmit error, the value in the CiMCTLj register is cleared to 00h.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 441 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.21 CANi Slot Buffer Select Register (CiSBS Register) (i = 0, 1)
CANi Slot Buffer Select Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SBS C1SBS
Bit Symbol SBS00 Bit Name
Address 0240h 0250h
Function
b3 b2 b1 b0
After Reset(2) 00h 00h
RW RW
SBS01 CANi message slot buffer 0 number select bit(1) SBS02
SBS03
0 0 0 0: Message slot 0 0 0 0 1: Message slot 1 0 0 1 0: Message slot 2 0 0 1 1: Message slot 3 . . . . . . 1 1 0 0: Message slot 12 1 1 0 1: Message slot 13 1 1 1 0: Message slot 14 1 1 1 1: Message slot 15
b7 b6 b5 b4
RW
RW
RW
SBS10
SBS11 CANi message slot buffer 1 number select bit(1) SBS12
SBS13
0 0 0 0: Message slot 0 0 0 0 1: Message slot 1 0 0 1 0: Message slot 2 0 0 1 1: Message slot 3 . . . . . . 1 1 0 0: Message slot 12 1 1 0 1: Message slot 13 1 1 1 0: Message slot 14 1 1 1 1: Message slot 15
RW
RW
RW
RW
NOTES: 1. 16 CANi message slots are provided. Each message slot can be selected as a transmit message slot or receive message slot. 2. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
Figure 23.31
C0SBS and C1SBS Registers
23.1.21.1 SBS03 to SBS00 Bits
The message slot j (j = 0 to 15), selected with bits SBS03 to SBS00, is allocated to the CANi message slot buffer 0. The message slot j can be accessed via the allocated addresses (CAN0: addresses 01E0h to 01EFh; CAN1: 0260h to 026Fh).
23.1.21.2 SBS13 to SBS10 Bits
The message slot j, selected with bits SBS13 to SBS10, is allocated to the CANi message slot buffer 1. The message slot j can be accessed via the allocated addresses (CAN0: addresses 01F0h to 01FFh; CAN1: 0270h to 027Fh).
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 442 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.22 CANi Message Slot Buffer j (i = 0, 1; j = 0, 1)
CANi Message Slot Buffer j Standard ID0 (i = 0, 1; j = 0, 1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLOT0_0, C0SLOT1_0 C1SLOT0_0, C1SLOT1_0
Bit Symbol SID6 Bit Name Standard ID6
Address 01E0h, 01F0h 0260h, 0270h
Function Read or write standard ID6 in the message slot k (k = 0 to 15) Read or write standard ID7 in the message slot k Read or write standard ID8 in the message slot k Read or write standard ID9 in the message slot k Read or write standard ID10 in the message slot k
After Reset Undefined Undefined
RW RW
SID7
Standard ID7
RW
SID8
Standard ID8
RW
SID9
Standard ID9
RW
SID10 - (b7-b5)
Standard ID10 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTE: 1. Use the CiSBS register to select the message slot k which is accessed through the CiSLOTj_0 register.
CANi Message Slot Buffer j Standard ID1 (i = 0, 1; j = 0, 1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLOT0_1, C0SLOT1_1 C1SLOT0_1, C1SLOT1_1
Bit Symbol SID0 Bit Name Standard ID0
Address 01E1h, 01F1h 0261h, 0271h
Function Read or write standard ID0 in the message slot k (k = 0 to 15) Read or write standard ID1 in the message slot k Read or write standard ID2 in the message slot k Read or write standard ID3 in the message slot k Read or write standard ID4 in the message slot k Read or write standard ID5 in the message slot k
After Reset Undefined Undefined
RW RW
SID1
Standard ID1
RW
SID2
Standard ID2
RW
SID3
Standard ID3
RW
SID4
Standard ID4
RW
SID5 - (b7-b6)
Standard ID5 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTE: 1. Use the CiSBS register to select the message slot k which is accessed through the CiSLOTj_1 register.
Figure 23.32
C0SLOT0_0, C0SLOT1_0, C1SLOT0_0, and C1SLOT1_0 Registers, C0SLOT0_1, C0SLOT1_1, C1SLOT0_1, and C1SLOT1_1 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Message Slot Buffer j Extended ID0 (i = 0, 1; j = 0,1)(1)(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLOT0_2, C0SLOT1_2 C1SLOT0_2, C1SLOT1_2
Bit Symbol EID14 Bit Name Extended ID14
Address 01E2h, 01F2h 0262h, 0272h
Function Read or write extended ID14 in the message slot k (k = 0 to 15) Read or write extended ID15 in the message slot k Read or write extended ID16 in the message slot k Read or write extended ID17 in the message slot k
After Reset Undefined Undefined
RW RW
EID15
Extended ID15
RW
EID16
Extended ID16
RW
EID17 - (b7-b4)
Extended ID17 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. If a receive slot is standard ID formatted, bits EID17 to EID14 are undefined when receive data is stored. 2. Use the CiSBS register to select the message slot k which is accessed through the CiSLOTj_2 register.
CANi Message Slot Buffer j Extended ID1 (i = 0,1; j = 0, 1)(1)(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLOT0_3, C0SLOT1_3 C1SLOT0_3, C1SLOT1_3
Bit Symbol EID6 Bit Name Extended ID6
Address 01E3h, 01F3h 0263h, 0273h
Function Read or write extended ID6 in the message slot k (k = 0 to 15) Read or write extended ID7 in the message slot k Read or write extended ID8 in the message slot k Read or write extended ID9 in the message slot k Read or write extended ID10 in the message slot k Read or write extended ID11 in the message slot k Read or write extended ID12 in the message slot k Read or write extended ID13 in the message slot k
After Reset Undefined Undefined
RW RW
EID7
Extended ID7
RW
EID8
Extended ID8
RW
EID9
Extended ID9
RW
EID10
Extended ID10
RW
EID11
Extended ID11
RW
EID12
Extended ID12
RW
EID13
Extended ID13
RW
NOTES: 1. If a receive slot is standard ID formatted, bits EID13 to EID6 are undefined when receive data is stored. 2. Use the CiSBS register to select the message slot k which is accessed through the CiSLOTj_3 register.
Figure 23.33
C0SLOT0_2, C0SLOT1_2, C1SLOT0_2, and C1SLOT1_2 Registers, C0SLOT0_3, C0SLOT1_3, C1SLOT0_3, and C1SLOT1_3 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Message Slot Buffer j Extended ID2 (i = 0, 1; j = 0, 1)(1)(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLOT0_4, C0SLOT1_4 C1SLOT0_4, C1SLOT1_4
Bit Symbol EID0 Bit Name Extended ID0
Address 01E4h, 01F4h 0264h, 0274h
Function Read or write extended ID0 in the message slot k (k = 0 to 15) Read or write extended ID1 in the message slot k Read or write extended ID2 in the message slot k Read or write extended ID3 in the message slot k Read or write extended ID4 in the message slot k Read or write extended ID5 in the message slot k
After Reset Undefined Undefined
RW RW
EID1
Extended ID1
RW
EID2
Extended ID2
RW
EID3
Extended ID3
RW
EID4
Extended ID4
RW
EID5 - (b7-b6)
Extended ID5 Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. If a receive slot is standard ID formatted, bits EID5 to EID0 are undefined when received data is stored. 2. Use the CiSBS register to select the message slot k which is accessed through the CiSLOTj_4 register.
CANi Message Slot Buffer j Data Length Code (i = 0, 1; j = 0, 1)(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol C0SLOT0_5, C0SLOT1_5 C1SLOT0_5, C1SLOT1_5
Bit Symbol DLC0 Bit Name
Address 01E5h, 01F5h 0265h, 0275h
Function
After Reset Undefined Undefined
RW RW
DLC1 Data length set bit DLC2 Read or write the data length set bit in the message slot k (k = 0 to 15)
RW
RW
DLC3 - (b7-b4) Unimplemented. Write 0. Read as undefined value.
RW
-
NOTE: 1. Use the CiSBS register to select the message slot k which is accessed through the CiSLOTj_5 register.
Figure 23.34
C0SLOT0_4, C0SLOT1_4, C1SLOT0_4, and C1SLOT1_4 Registers C0SLOT0_5, C0SLOT1_5, C1SLOT0_5, and C1SLOT1_5 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Message Slot Buffer j Data m (i = 0, 1; j = 0, 1; m = 0 to 7)(1)(2)
b7 b0
Symbol C0SLOT0_6 to C0SLOT0_13 C0SLOT1_6 to C0SLOT1_13 C1SLOT0_6 to C1SLOT0_13 C1SLOT1_6 to C1SLOT1_13
Function
Address 01E6h - 01EDh 01F6h - 01FDh 0266h - 026Dh 0276h - 027Dh
After Reset Undefined Undefined Undefined Undefined
Setting Range 00h to FFh RW RW
Read or write data m in the message slot k (k = 0 to 15)
NOTES: 1. Use the CiSBS register to select data m in the message slot k which is accessed through registers CiSLOTj_6 to CiSLOTj_13. 2. When a data frame receive operation is selected, data that exceeds the received data is undefined.
CANi Message Slot Buffer j Time Stamp High-Ordered (i = 0, 1; j = 0, 1)(1)
b7 b0
Symbol C0SLOT0_14, C0SLOT1_14 C1SLOT0_14, C1SLOT1_14
Function
Address 01EEh, 01FEh 026Eh, 027Eh
After Reset Undefined Undefined
Setting Range 00h to FFh RW RW
Read or write time stamp high-ordered in the message slot k (k = 0 to 15)
NOTE: 1. Use the CiSBS register to select the time stamp high-ordered in the message slot k which is accessed through the CiSLOTj_14 register.
CANi Message Slot Buffer j Time Stamp Low-Ordered (i = 0, 1; j = 0, 1)(1)
b7 b0
Symbol C0SLOT0_15, C0SLOT1_15 C1SLOT0_15, C1SLOT1_15
Function
Address 01EFh, 01FFh 026Fh, 027Fh
After Reset Undefined Undefined
Setting Range 00h to FFh RW RW
Read or write time stamp low-ordered in the message slot k (k = 0 to 15)
NOTE: 1. Use the CiSBS register to select the time stamp low-ordered in the message slot k which is accessed through the CiSLOTj_15 register.
Figure 23.35
C0SLOT0_6 to C0SLOT0_13, C0SLOT1_6 to C0SLOT1_13, C1SLOT0_6 to C1SLOT0_13, and C1SLOT1_6 to C1SLOT1_13 Registers, C0SLOT0_14, C0SLOT1_14, C1SLOT0_14, and C1SLOT1_14 Registers C0SLOT0_15, C0SLOT1_15, C1SLOT0_15, and C1SLOT1_15 Registers
The value in the message slot selected by the CiSBS register is returned by reading the message slot buffer. When writing to the message slot buffer, the value can be written in the message slot selected by the CiSBS register. Write to the message slot k (k = 0 to 15) while the corresponding CiMCTLk register is set to 00h.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.1.23 CANi Acceptance Filter Support Register (CiAFS Register) (i = 0, 1)
CANi Acceptance Filter Support Register (i = 0,1)
b15 b8 b7 b0
Symbol C0AFS C1AFS
Function
Address 0245h - 0244h 0255h - 0254h
After Reset(1) 0100h 0100h
Setting Range 0000h to FFFFh RW RW
Data to determine the received ID is generated
NOTE: 1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock to the CAN module.
b15 b0 SID5 SID4 SID3 SID2 SID1 SID0 SID10 SID9 SID8 SID7 SID6
Write
b15
3-8 decoding
b8
b7 SID9 b4 004h 0 00Ch 0 SID8 b3 003h 0 00Bh 0 SID7 SID6 b2 002h 0 00Ah 0 SID5 b1 001h 1 009h 0 SID4 b0 000h 0 008h 0
b0 SID3
Read
CSID7 CSID6 CSID5 CSID4 CSID3 CSID2 CSID1 CSID0 SID10 b7 b6 006h 0 00Eh 0 b5 005h 0 00Dh 0
Data for a data table search is generated from the received ID in standard format. The table search with this data determines whether or not the received ID is valid.
Top + 00h Top + 01h
007h 0 00Fh 1
Top + DEh
6F7h 0
6F6h 0
6F5h 0
6F4h 0
6F3h 1
6F2h 0
6F1h 0
6F0h 0
Top + FEh Top + FFh
7F7h 0 7FFh 0
7F6h 0 7FEh 0
7F5h 0 7FDh 1
7F4h 0 7FCh 0
7F3h 0 7FBh 0
7F2h 0 7FAh 0
7F1h 0 7F9h 0
7F0h 1 7F8h 0
When the received ID is 6F3h
b15
Address search information
b8 b7 SID5 SID4 SID3 SID2 SID1 SID0 0 1 1 0 0 SID10 1 1 0 0 0
Bit search information
b0 SID10 SID9 SID8 SID7 SID6 1 1 0 1 1 SID0
Write to the CiAFS register
0
Received ID
1
6 1 D 0 1 1
F 1 E 1 0 0
3 1 3 1
Divide it to 8 bits and 3 bits
8 bits
b15 0 0 0 0 08h 1 0 0 b8 0 b7 1 1 D 0 1 1 1
3 bits
b0 1 E 0
Read from the CiAFS register
Bit search information Bit search information
01h 02h 04h 08h 10h 20h 40h 80h b7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 b0 01 10 00 00 00 00 00 00
Address search information 3 low-order bits of received ID
0h 1h 2h 3h 4h 5h 6h 7h
Because the value of the 3 low-order bits is 3, b3 in the left table is 1. (If the value of the 3 low-order bits is 4, b4 in the left table is 1.)
i = 0, 1
Figure 23.36
C0AFS and C1AFS Registers
The CiAFS register enables prompt performance of a table search to determine the validity of the received ID. This function is for standard-formatted ID only.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.2 23.2.1
CAN Clock and CPU Clock CAN Clock
The CAN clock is an operating clock for the CAN module. f1 is selected as the CAN clock when the PM25 bit in the PM2 register is set to 0. fCAN is selected as the CAN clock when the PM25 bit is set to 1. Set the PM25 bit while the SLEEP bit in CiSLPR register (i = 0, 1) is set to 0 (sleep mode).
23.2.2
CPU Clock
Follow the procedure below before accessing the CAN-associated registers. * When the PM25 bit is set to 0 (f1): (1) Set the PM24 bit to 0 (CPU clock is selected by the CM07 bit). (2) Set the CM21 bit in the CM2 register to 0 (CPU clock is selected by the CM17 bit). (3) Set bits MCD4 to MCD0 to 10010b (no division). (4) Set the PM13 bit in the PM1 register to 1 (2 wait states). * When the PM25 bit is set to 1 (fCAN): (1) Set the PM24 bit to 1 (CPU clock is selected by the CM07 bit). (2) Set the PM13 bit in the PM1 register to 1 (2 wait states). (3) Wait for the time to switch clock.(1) Do not enter wait mode or stop mode when the PM24 bit is set to 1. NOTE: 1. The wait time to switch clock varies depending on the CPU clock frequency before and after the PM24 bit is changed. * High frequency: Higher frequency compared "before the PM24 bit changes" with "after the PM24 bit changes" * Low frequency: Lower frequency compared "before the PM24 bit changes" with "after the PM24 bit changes" 2 x High frequency Low frequency
Wait time to switch clock >
cycles
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.3 23.3.1
Setting and Timing in CAN-Associated Registers CAN Module Initialize Timing
Figure 23.37 shows an operation example when the CAN module is initialized. (1) The CAN module can be initialized when the STATE_RESET bit in the CiSTR register (i = 0, 1) becomes 1 (CAN module is in reset) after both the RESET1 and RESET0 bits in the CiCTLR0 register are set to 1 (CAN module is reset). (2) Set necessary CAN-associated registers. (3) CAN communication can be established again when the STATE_RESET bit becomes 0 (CAN module is not in reset) after both the RESET1 and RESET0 bits are set to 0 (CAN module is out of reset).
Set to 1 by a program simultaneously
Set to 0 by a program simultaneously
RESET0 bit
1 0 1 0 1 0 Verify the STATE_RESET bit Initialize the CAN module Verify the STATE_RESET bit Operation (1) Operation (2) Operation (3) CAN operation
RESET1 bit
STATE_RESET bit
Figure 23.37
Example of CAN Module Initialize Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.3.2
CAN Transmit Timing
Figure 23.38 shows an operation example when the CAN transmits a data frame or remote frame. (1) When the TRMREQ bit in the CiMCTLj register (i = 0, 1; j = 0 to 15) is set to 1 (transmit operation requested) while the CAN bus is in an idle state, the TRMACTIVE bit in the CiMCTLj register becomes 1 (transmitting), the TRMSTATE bit in the CiSTR register becomes 1 (transmitting), and a CAN transmit operation is started. (2) After a CAN transmit operation is completed, the SENTDATA bit in the CiMCTLj register becomes 1 (transmit operation completed), the TRMSUCC bit in the CiSTR register becomes 1 (transmit operation completed), and the SISj bit in the CiSISTR register becomes 1 (interrupt requested).
Transmit operation started (1) CAN bus Bus-idle 1 0 1 0 1 0 1 0 TRMSUCC bit 1 0 1 SISj bit j = 0 to 15 0 Set to 1 by a program Transmit frame Transmit frame
Transmit operation completed (2)
Intermission field
Bus-idle
TRMREQ bit
Set to 0 by a program
TRMACTIVE bit
TRMSTATE bit
SENTDATA bit
Set to 0 by a program
Figure 23.38
Example of CAN Data Frame Transmit Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.3.3
CAN Receive Timing
Figure 23.39 shows an operation example when the CAN receives a data frame or remote frame. (1) When the RECREQ bit in the CiMCTLj register (i = 0, 1; j = 0 to 15) is set to 1 (receive operation requested), the CAN module is ready to receive a data frame or remote frame. (2) When a CAN receive operation is started, the RECSTATE bit in the CiSTR register becomes 1 (receiving). (3) After the CAN receive operation is completed, the RECSUCC bit in the CiSTR register becomes 1 (receive operation completed). And then, the NEWDATA bit in the CiMCTLj register becomes 1 (receive operation completed) and the INVALDATA bit in the CiMCTLj register becomes 1 (storing receive data). (4) After data is stored into the message slot, the INVALDATA bit becomes 0 (not storing receive data) and the SISj bit in the CiSISTR register becomes 1 (interrupt requested).
(1) CAN bus Bus-idle
Receive operation started (2) Receive frame Receive frame
Receive operation completed (4) (3)
Intermission field
Bus-idle
RECREQ bit
1 0 1 0 1 0 1 0 Set to 1 by a program Set to 0 by a program
RECSTATE bit
RECSUCC bit
NEWDATA bit
INVALDATA bit
1 0 1
SISj bit j = 0 to 15
0 Set to 0 by a program
Figure 23.39
Example of CAN Data Frame Receive Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.3.4
CAN Bus Error Timing
Figure 23.40 shows an operation example when a CAN bus error occurs. (1) When a CAN bus error is detected, the STATE_BUSERROR bit in the CiSTR register becomes 1 (error occurred), the BEIS bit in the CiEISTR register becomes 1 (interrupt requested), and the CAN module transmits an error frame.
(1)
Error detected Error frame
CAN bus STATE_BUSERROR bit
1 0 1 0
Transmit / receive frame
BEIS bit
Set to 0 by a program
Figure 23.40
Operation Example when CAN Bus Error Occurs
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.4
CAN Interrupts
The CAN1 wake-up interrupt and CANij interrupt (i = 0, 1; j = 0 to 2) are provided as the CAN interrupts. The CAN1 wake-up interrupt, CANij interrupt are shared with the intelligent I/O interrupts. Refer to 11. Interrupts for details on the interrupt. Figure 23.41 shows a block diagram of the CAN1 wake-up interrupt and CANij interrupt.
CAN0 Message slot k transmit operation completed Message slot k receive operation completed Error CAN0j interrupt CAN00 interrupt request
IIO9IR register
IIO9IE regsiter IRLT bit 0 1 CAN00E bit
Intelligent I/O interrupt 9 request
CAN00R bit
Associated registers C0SISTR register C0EISTR register C0SIMKR register C0EIMKR register INTSEL bit CAN01 interrupt request
IIO10IR register
IIO10IE regsiter IRLT bit 0 1 CAN01E bit
Intelligent I/O interrupt 10 request
CAN01R bit
IIO11IR register CAN02 interrupt request
IIO11IE regsiter IRLT bit 0 1 CAN02E bit
Intelligent I/O interrupt 11 request
CAN02R bit
CAN1 Message slot k transmit operation completed Message slot k receive operation completed Error CAN1j interrupt CAN10 interrupt request
IIO0IR register
IIO0IE regsiter IRLT bit 0 1 CAN10E bit
Intelligent I/O interrupt 0 request
CAN10R bit
Associated registers C1SISTR register C1EISTR register C1SIMKR register C1EIMKR register INTSEL bit CAN11 interrupt request
IIO1IR register
IIO1IE regsiter IRLT bit 0 1 CAN11E bit
Intelligent I/O interrupt 1 request
CAN11R bit
IIO5IR register CAN12 interrupt request
IIO5IE regsiter IRLT bit 0 1 0 1 CAN12E bit CAN1WUE bit Intelligent I/O interrupt 5 request
CAN12R bit
CAN1WUR bit CAN1WU interrupt request j = 0 to 2 k = 0 to 15 INTSEL bit: Bit in the CiCTLR1 register (i = 0, 1)
Figure 23.41
CAN1 Wake-UP Interrupt and CANij Interrupt Block Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 453 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.4.1
CAN1 Wake-Up Interrupt
When a signal applied to the CAN1WU pin is at the falling edge, the CAN1WUR bit in the IIO5IR register becomes 1 (interrupt requested), regardless of the value of the SLEEP bit in the C1SLPR register. When P7_7 (CAN0IN) is used as a CAN0 input port, the CAN0 wake-up interrupt becomes available by using event counter mode of TA3IN that shares a pin with CAN0. When P8_3 (CAN0IN/CAN1IN) is used as a CAN input port, the CAN0 and CAN1 wake-up interrupts become available by using INT1 that shares a pin with CAN0IN/CAN1IN.
23.4.2
CANij Interrupt
The followings are the CANij interrupt request sources. (i = 0, 1; j = 0 to 2) * CANi message slot k (k = 0 to 15) transmit operation completed * CANi message slot k receive operation completed * CANi bus error detected * CANi error-passive state entered * CANi bus-off state entered When the INTSEL bit in the CiCTLR1 register is set to 0, the result of logical sum of interrupt requests from the above five sources becomes the CANij interrupt request. When the INTSEL bit is set to 1, the interrupt requests from three types of CANij interrupt request sources, which are CANi message slot k transmit operation completed, CANi message slot k receive operation completed, and CANi error (bus error detected, error-passive state entered, and bus-off state entered), are individually output.
23.4.2.1
When the INTSEL Bit is Set to 0 (output CAN interrupt request via OR gate)
When the INTSEL bit is set to 0 (output CAN interrupt request via OR gate), all the CANi0, CANi1, and CANi2 interrupt requests are generated by any of the CANij interrupt source. Table 23.5 lists interrupt sources and the corresponding interrupt registers (when INTSEL bit is set to 0). Figure 23.42 shows a CANij interrupt block diagram (when INTSEL bit is set to 0). When a CANij interrupt request is generated, the interrupt status bit (the corresponding bit in the CiSISTR register or CiEISTR register) becomes 1 (interrupt requested). And then, if the interrupt mask bit (the corresponding bit in the CiSIMKR register or CiEIMKR register) is set to 1 (interrupt request enabled), all the corresponding CANijR bits in the IIOnIR register (n = 9, 10, 11 when i = 0; n = 0, 1, 5 when i = 1) become 1 (interrupt requested). NOTE: 1. The interrupt status bits in registers CiSISTR and CiEISTR are not cleared to 0 automatically when an interrupt request is acknowledged. Set each bit to 0 by a program. While any of enabled status bits remains 1, the CANijR bit does not become 1 (interrupt requested) when a CANij interrupt request is generated.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 23.5 Interrupt Sources and Interrupt Registers (When INTSEL Bit is Set to 0)
23. CAN Module
CANij Interrupt CANij interrupt source Interrupt status bit 0: interrupt not requested 1: interrupt requested Interrupt mask bit 0: interrupt request disabled 1: interrupt request enabled
Intelligent I/O interrupt Intelligent I/O interrupt request 0: interrupt not requested 1: interrupt requested
CANi message slot k receive operation completed CANi message slot k transmit operation completed CANi bus error detected CANi error-passive state entered CANi bus-off state entered
SISk bit in the CiSISTR register
SIMk bit in the CiSIMKR register
BEIS bit in the CiEISTR register EPIS bit in the CiEISTR register BOIS bit in the CiEISTR register
BEIM bit in the CiEIMKR register EPIM bit in the CiEIMKR register BOIM bit in the CiEIMKR register
When i = 0, CAN0jR bit in registers IIO9IR, IIO10IR, and IIO11IR When i = 1, CAN1jR bit in registers IIO0IR, IIO1IR, and IIO5IR
CANi Interrupt
CANi message slot 0 receive operation completed CANi message slot 0 transmit operation completed
Intelligent I/O interrupt
INTSEL bit
SIS0 bit SIM0 bit
1 0 CANi0R bit
CANi message slot 15 receive operation completed CANi message slot 15 transmit operation completed CANi bus error detected CANi error-passive state entered CANi bus-off state entered i = 0, 1
SIS15 bit SIM15 bit
INTSEL bit 1 0 CANi1R bit
BEIS bit BEIM bit EPIS bit EPIM bit BOIS bit BOIM bit INTSEL bit 1 0 CANi2R bit
Figure 23.42
CANij Interrupt Block Diagram (When INTSEL Bit is Set to 0)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
23.4.2.2
When the INTSEL Bit is Set to 1 (output CAN interrupt request individually)
When the INTSEL bit is set to 1 (output CAN interrupt request individually), the following three types of CANij interrupt sources output an interrupt request individually. * When CANi message slot k transmit operation is completed, CANi0 interrupt request is generated. * When CANi message slot k receive operation is completed, CANi1 interrupt request is generated. * When CANi error (bus error detected, error-passive state entered, and bus-off state entered) occurs, CANi2 interrupt request is generated. Table 23.6 lists interrupt sources and the corresponding interrupt registers (when INTSEL bit is set to 1). Figure 23.43 shows a CANij interrupt block diagram (when INTSEL bit is set to 1). When a CANij interrupt request is generated, the interrupt status bit (the corresponding bit in the CiSISTR register or CiEISTR register) becomes 1 (interrupt requested). And then, if the interrupt mask bit (the corresponding bit in the CiSIMKR register or CiEIMKR register) is set to 1 (interrupt request enabled), the corresponding intelligent I/O interrupt request bit becomes 1 (interrupt requested). NOTES: 1. The SISk bits in the CiSISTR register are not cleared to 0 automatically when an interrupt request is acknowledged. Set each bit to 0 by program. If the SISk bit remains 1, the CANi0R or CANi1R bit in the IIOnIR register (n = 9, 10 when i = 0, n = 0, 1 when i = 1) still becomes 1 (interrupt requested) when a CANi transmit/receive interrupt request is generated. 2. The bits in the CiEISTR register are not cleared to 0 automatically when an interrupt request is acknowledged. Set each bit to 0 by program. While any of enabled status bits remains 1, the CANi2R bit does not become 1 (interrupt requested) when a CANi error (bus error detected, error-passive state entered, and bus-off state entered) interrupt request is generated. Table 23.6 Interrupt Sources and Interrupt Registers (When INTSEL Bit is Set to 1)
CANij Interrupt CANij interrupt source Interrupt status bit 0: interrupt not requested 1: interrupt requested Interrupt mask bit 0: interrupt request disabled 1: interrupt request enabled
Intelligent I/O interrupt Intelligent I/O interrupt request 0: interrupt not requested 1: interrupt requested When i = 0, CAN00R bit in the IIO9IR register When i = 1, CAN10R bit in the IIO0IR register When i = 0, CAN01R bit in the IIO10IR register When i = 1, CAN11R bit in the IIO1IR register When i = 0, CAN02R bit in the IIO11IR register When i = 1, CAN12R bit in the IIO5IR register
CANi message slot k receive operation completed SISk bit in the CiSISTR register CANi message slot k transmit operation completed BEIS bit in the CiEISTR register EPIS bit in the CiEISTR register BOIS bit in the CiEISTR register BEIM bit in the CiEIMKR register EPIM bit in the CiEIMKR register BOIM bit in the CiEIMKR register SIMk bit in the CiSIMKR register
CANi bus error detected CANi error-passive state entered CANi bus-off state entered
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
23. CAN Module
CANi Interrupt
CANi message slot 0 receive operation completed CANi message slot 0 transmit operation completed
CANi message slot 0 to 15 receive operation completed interrupt request 1 0
Intelligent I/O Interrupt
INTSEL bit CANi0R bit
SIM0 bit
SIS0 bit
CANi message slot 15 receive operation completed CANi message slot 15 transmit operation completed
CANi message slot 0 to 15 transmit operation completed interrupt request
SIM15 bit 1 0 SIS15 bit
INTSEL bit CANi1R bit
CANi bus error detected CANi error-passive state entered CANi bus-off state entered
BEIS bit BEIM bit EPIS bit EPIM bit BOIS bit BOIM bit
CANi error interrupt request 1 0
INTSEL bit CANi2R bit
i = 0, 1
Figure 23.43
CANij Interrupt Block Diagram (When INTSEL Bit is Set to 1)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
24. Real-Time Port (RTP)
24. Real-Time Port (RTP)
When RTP output is selected, the values in the RTPiR register (i = 0 to 3) are output from pins RTPi_0 to RTPi_3 every time corresponding timer A or timer B underflows. Output values from pins RTPi_0 to RTPi_3 are undefined until the first timer A or timer B underflow. If the undefined RTP output becomes a problem, set pins as I/O ports in the Function Select Register A until the first timer A or timer B underflow. After the first timer A or timer B underflow, set the pins as RTP outputs in the Function Select Register A to E settings. Set timer A or timer B corresponding to RTP output to timer mode. Figure 24.1 shows block diagram of RTP function. Figure 24.2 shows RTP-associated registers. Figure 24.3 shows RTP output timing. Table 24.1 lists pin settings.
RTP0R b7
b0
Timer A0 Underflow Signal
T D D D D T T T Q Q Q Q
RTP0_0 (P6_0) RTP0_1 (P6_1) RTP0_2 (P7_0) RTP0_3 (P7_1)
RTP1R b7
b0
Timer B0 Underflow Signal
T D D D D T T T Q Q Q Q
RTP1_0 (P10_0) RTP1_1 (P10_1) RTP1_2 (P10_2) RTP1_3 (P10_3)
RTP2R b7
b0
Timer A2 Underflow Signal
T D D D D T T T Q Q Q Q
RTP2_0 (P7_4) RTP2_1 (P7_5) RTP2_2 (P7_7) RTP2_3 (P8_1)
RTP3R b7
b0
Timer B2 Underflow Signal
T D D D D T T T Q Q Q Q
RTP3_0 (P10_4) RTP3_1 (P10_5) RTP3_2 (P10_6) RTP3_3 (P10_7)
Figure 24.1
RTP Block Diagram
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
24. Real-Time Port (RTP)
RTP Output Buffer Register i (i = 0 to 3)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RTP0R to RTP3R
Bit Symbol RTPi0
Address 01D8h to 01DBh
Bit Name
After Reset XXh
Function 0 : "L" output 1 : "H" output 0 : "L" output 1 : "H" output 0 : "L" output 1 : "H" output 0 : "L" output 1 : "H" output RW WO
RTPi_0 Output Buffer
RTPi1
RTPi_1 Output Buffer
WO
RTPi2
RTPi_2 Output Buffer
WO
RTPi3
RTPi_3 Output Buffer Unimplemented. Write 0. Read as undefined value.
WO
- (b7-b4)
-
Figure 24.2
RTP0R to RTP3R Registers
Pins RTPi_0 to RTPi_3 are selected in the Function Select Registers A to E. Count starts Underflows Underflows
Contents of the counter (hexadecimal)
Time Timer A/timer B count start bit RTPiR register value 1 0 05h 0Ah
RTPi_3
Undefined
RTPi_2 Real-time port output RTPi_1
Undefined
Undefined
RTPi_0 Timer A/timer B IR bit i = 0 to 3 1 0
Undefined
Set to 0 by an interrupt request acknowledgement or by a program
Figure 24.3
RTP Output Timing
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 24.1
Port P6_0 P6_1 P7_0(2) P7_1(2) P7_4 P7_5 P7_7 P8_1 P10_0 P10_1 P10_2 P10_3 P10_4 P10_5 P10_6 P10_7
24. Real-Time Port (RTP)
Pin Settings for Real Time Port
Bit Setting Function RTP0_0 RTP0_1 RTP0_2 RTP0_3 RTP2_0 RTP2_1 RTP2_2 RTP2_3 RTP1_0 RTP1_1 RTP1_2 RTP1_3 RTP3_0 RTP3_1 RTP3_2 RTP3_3 - - PSE1_0=1 PSE1_1=1 - - PSE1_7=1 PSE2_1=1 - - - - - - - - PSE1, PSE2 Registers - - PSD1_0=1 PSD1_1=1 PSD1_4=1 - PSD1_7=1 PSD2_1=1 - - - - - - - - PSD1, PSD2 Registers - - PSC_0=1 PSC_1=1 PSC_4=1 PSC_5=1 - PSC2_1=1 - - - - - - - - PSC, PSC2 Registers PSL0, PSL1, PSL2 Registers PSL0_0=1 PSL0_1=1 PSL1_0=0 PSL1_1=0 PSL1_4=0 PSL1_5=1 PSL1_7=1 PSL2_1=1 - - - - - - - - PS0, PS1,PS2,PS4 Registers(1) PS0_0=1 PS0_1=1 PS1_0=1 PS1_1=1 PS1_4=1 PS1_5=1 PS1_7=1 PS2_1=1 PS4_0=1 PS4_1=1 PS4_2=1 PS4_3=1 PS4_4=1 PS4_5=1 PS4_6=1 PS4_7=1
NOTES: 1. Set registers PS0, PS1, PS2, and PS4 after setting the other registers. 2. P7_0 and P7_1 are N-channel open drain output ports.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
25. Programmable I/O Ports
123 programmable I/O ports, P0 to P15 (excluding P8_5), are available in the 144-pin package. 87 programmable I/O ports, P0 to P10 (excluding P8_5), are available in the 100-pin package. The Port Pi Direction Registers determine individual port status, input or output. The pull-up control registers determine whether the ports, divided into groups of four, are pulled up or not. P8_5 is an input-only port and cannot be pulled up internally. The P8_5 bit in the P8 register indicates an NMI input level since P8_5 shares its pin with NMI. Figures 25.1 to 25.4 show programmable I/O port configurations. Each pin functions as a programmable I/O port, I/O pin for internal peripheral function, or bus control pin. To use as an I/O pin for peripheral function, refer to the description for individual peripheral functions. Refer to 8. Bus when used as a bus control pin. Registers associated with the programmable I/O ports are as follows.
25.1
Port Pi Direction Register (PDi Register, i = 0 to 15)
Figure 25.5 shows the PDi register. The PDi register configures a programmable I/O port as either input or output. Each bit in the PDi register corresponds to one port. In memory expansion mode and microprocessor mode, the PDi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL / WR, WRH / BHE, RD, BCLK / ALE / CLKOUT, HLDA / ALE, HOLD, ALE, and RDY. No bit controlling P8_5 is provided in the PDi register.
25.2
Port Pi Register (Pi Register, i = 0 to 15)
Figure 25.6 shows the Pi register. The MCU inputs/outputs data from/to external devices by reading and writing to the Pi register. The Pi register consists of a port latch to hold output data and a circuit to read the pin level. Each bit in the Pi register corresponds to one port. In memory expansion mode and microprocessor mode, the Pi register corresponding to the following bus control pins cannot be written and the port level cannot be read from the Pi register: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH / BHE, RD, BCLK / ALE / CLKOUT, HLDA / ALE, HOLD, ALE, and RDY.
25.3
Function Select Register A (PSj Register, j = 0 to 9)
Figures 25.7 to 25.11 show the PSj registers. The PSj register selects either I/O port or peripheral function output if these functions share a single pin (excluding DA0 and DA1). When multiple peripheral function outputs are assigned to a single pin, set registers PSL0 to PSL3, PSL5 to PSL7, PSL9, PSC, PSC2, PSC3, PSC6, PSD1, PSD2, PSE1, and PSE2 to select which function to use. Tables 25.3 to 25.13 list peripheral function output control settings for each pin.
25.4
Function Select Register B (PSLk Register, k = 0 to 3, 5 to 7, 9)
Figures 25.12 to 25.15 show the PSLk register. When multiple peripheral function outputs are assigned to a single pin, the PSLk register selects which peripheral function output to use. Refer to 25.11 Analog Input and Other Peripheral Function Input for information on bits PSL3_3 to PSL3_6 in the PSL3 register.
25.5
Function Select Register C (PSC, PSC2, PSC3, and PSC6 Registers)
Figures 25.16 and 25.17 show registers PSC, PSC2, PSC3, and PSC6. When multiple peripheral function outputs are assigned to a single pin, registers PSC, PSC2, PSC3, and PSC6 select which peripheral function output to use. Refer to 25.11 Analog Input and Other Peripheral Function Input for information on the PSC_7 bit in the PSC register.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
25.6
Function Select Register D (PSD1 and PSD2 Registers)
Figure 25.18 shows registers PSD1 and PSD2. When multiple peripheral function outputs are assigned to a single pin, registers PSD1 and PSD2 select which peripheral function output to use.
25.7
Function Select Register E (PSE1 and PSE2 Registers)
Figure 25.19 shows registers PSE1 and PSE2. When multiple peripheral function outputs are assigned to a single pin, registers PSE1 and PSE2 select which peripheral function output to use.
25.8
Pull-up Control Register 0 to 4 (PUR0 to PUR4 Registers)
Figures 25.20 to 25.23 show registers PUR0 to PUR4. Registers PUR0 to PUR4 select whether the ports, divided into groups of four, are pulled up or not. Set the bit in registers PUR0 to PUR4 to 1 (pull-up) and the bit in the PDi register to 0 (input mode) to pull-up the corresponding port. In memory expansion mode and microprocessor mode, set bits, corresponding to the bus control pins (P0 to P5), in registers PUR0 and PUR1 to 0 (no pull-up). P0, P1, and P4_0 to P4_3 can be pulled up when they are used as input ports in memory expansion mode and microprocessor mode.
25.9
Port Control Register (PCR Register)
Figure 25.24 shows the PCR register. The PCR register selects either CMOS output or N-channel open drain output as port P1 output format. When the PCR0 bit is set to 1, P channel in the CMOS port is turned off at all times and in result port P1 becomes N-channel open drain output. This is, however, pseudo open drain. Therefore, the absolute maximum rating of the input voltage is from -0.3 V to VCC2 + 0.3 V. To use port P1 as data bus in memory expansion mode and microprocessor mode, set the PCR0 bit to 0 (CMOS output). When port P1 is used as a port in memory expansion mode and microprocessor mode, set the output format using the PCR0 bit.
25.10 Input Function Select Register (IPS, IPSA, and IPSB Registers)
Figures 25.24 to 25.25 show registers IPS, IPSA, and IPSB. Registers IPS and IPSA determine which pins are used as input pins for intelligent I/O or CAN. Refer to 25.11 Analog Input and Other Peripheral Function Input for information on the IPS2 bit in the IPS register and the IPSB register.
25.11 Analog Input and Other Peripheral Function Input
Bits PSL3_3 to PSL3_6 in the PSL3 register, the PSC_7 bit in the PSC register, the IPS2 bit in the IPS register, and bits IPSB_0 to IPSB_7 in the IPSB register are used to separate peripheral function inputs from analog input/ output. If the analog I/O shares the pin with other peripheral function inputs, a through current may flow to the peripheral function inputs when an intermediate voltage is applied to the pin. To use the analog I/O (DA0, DA1, ANEX0, ANEX1, AN_4 to AN_7 or AN15_0 to AN15_7), set the corresponding bit to 1 (analog I/O), and disconnect the peripheral function inputs to prevent an intermediate voltage from being applied to the peripheral function inputs. When bits PSL3_3 to PSL3_6 (for P9_3 to P9_6), the IPS2 bit, and bits IPSB_0 to IPSB_7 (for P15_0 to P15_7) are set to 1, the input buffer for the peripheral functions except for the port function is disconnected. For P10_4 to P10_7 (AN_4 to AN_7/KI0 to KI3), when the PSC_7 bit is set to 1, the input buffer for the peripheral functions including the port function is disconnected and ports P10_4 to P10_7 are read as undefined. Also, the IR bit in the KUPIC register remains unchanged as 0 (interrupt not requested) even if KI0 to KI3 pin input levels are changed. Set the corresponding bit to 0 (except analog I/O) when analog I/O is not used.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Programmable I/O ports
Pull-up select PDi register
Port latch Data bus
A Peripheral function input Peripheral function input Analog signal
B C D
Option Port P0_0 to P0_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_2 P5_5, P5_7 P8_3, P8_4 P8_6, P8_7 : Available
(A) Hysteresis
(B) Peripheral function input
(C) Peripheral function input
(D) Analog I/F
-
-
-
- - - -: Not available
- -
-
- -
- - -
- -
Figure 25.1
Programmable I/O Ports (1/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Programmable I/O ports with the port control register
Pull-up select PDi register PCR0 bit Port latch Data bus A Peripheral function input PCR0 bit: bit in the PCR register
Option Port P1_0 to P1_4 P1_5 to P1_7 : Available (A) Hysteresis (B) Peripheral function input
B
- -: Not available
-
Programmable I/O ports with the function select register
INV03
Value written to INV03 bit Write signal to INV03 bit
D T R
Q
RESET NMI INV05 Pull-up select
INV02
Registers PS1 and PS2
PDi register
Peripheral function output Port latch
Data bus
Peripheral function input Port P7_2 to P7_5, P8_0, P8_1
Figure 25.2
Programmable I/O Ports (2/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Programmable I/O ports with the function select register
Pull-up select Registers PS0 to PS9(1, 2) PDi register E
Peripheral function output Port latch Data bus
A Peripheral function input Peripheral function input Analog signal
(B) Peripheral fucntion input (C) Peripheral fucntion input
B C D
(A) Hysteresis (D) Analog I/F (E) Circuit
Option Port
P5_3(1) P5_4, P5_6(2) P6_0 to P6_7 P7_0, P7_1(3) P7_6, P7_7 P8_2 P9_0 to P9_2 P9_3 to P9_6 P9_7 P10_0 to P10_3 P10_4 to P10_7 P11_0 to P11_3 P11_4, P12_0 P12_1 to P12_3 P12_4 to P12_7 P13_0 to P13_4 P13_5, P13_6
- - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - -
- -
-
- - - - - - - -
-
- - - - - - - - - - - - - - - -
(note 4)
P13_7 P14_0 to P14_3 P14_4 to P14_6 P15_0 P15_1 to P15_3 P15_4 P15_5 to P15_7
: Available -: Not available NOTES: 1. For P5_3, use the PM07 bit in the PM0 register, bits PM15 and PM14 in the PM1 register, and bits CM01 and CM00 in the CM0 register to select CLKOUT or ALE output. 2. For P5_4 and P5_6, use bits PM15 and PM14 to select ALE output. 3. P7_0 and P7_1 are N-channel open drain output ports. 4. These ports are provided in the 144-pin package only.
Figure 25.3
Programmable I/O Ports (3/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Input-only port (P8_5)
Data bus
NMI
Figure 25.4
Programmable I/O Ports (4/4)
Port Pi Direction Register (i = 0 to 15)(2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PD0 to PD3 PD4 to PD7 PD8 PD9, PD10 PD11 PD12, PD13 PD14 PD15
Bit Symbol PDi_0 Bit Name Port Pi_0 direction bit
Address 03E2h, 03E3h, 03E6h, 03E7h 03EAh, 03EBh, 03C2h, 03C3h 03C6h(4) 03C7h(1), 03CAh 03CBh(3, 4) 03CEh, 03CFh(3) 03D2h(3, 4) 03D3h(3)
Function
After Reset 00h 00h 00X0 0000b 00h XXX0 0000b 00h X000 0000b 00h
RW RW
0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port) 0: Input mode (functions as input port) 1: Output mode (functions as output port)
PDi_1
Port Pi_1 direction bit
RW
PDi_2
Port Pi_2 direction bit
RW
PDi_3
Port Pi_3 direction bit
RW
PDi_4
Port Pi_4 direction bit
RW
PDi_5
Port Pi_5 direction bit
RW
PDi_6
Port Pi_6 direction bit
RW
PDi_7
Port Pi_7 direction bit
RW
NOTES: 1. Set the PD9 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions. 2. In memory expansion mode or microprocessor mode, the PDi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE, RDY. 3. Set registers PD11 to PD15 to FFh in the 100-pin package. 4. Nothing is implemented to the PD8_5 bit in the PD8 register, bits PD11_7 to PD11_5 in the PD11 register, and the P14_7 bit in the PD14 register. Write a 0. A read from these bits returns undefined value.
Figure 25.5
PD0 to PD15 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Port Pi Register (1, 2) (i = 0 to 15)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P0 to P5 P6 to P10 P11 to P15
Bit Symbol Pi_0
Address 03E0h, 03E1h, 03E4h, 03E5h, 03E8h, 03E9h 03C0h, 03C1h(3), 03C4h(4), 03C5h, 03C8h 03C9h(5), 03CCh, 03CDh, 03D0h(5), 03D1h
Bit Name Port Pi_0 bit Function
After Reset Undefined Undefined Undefined
RW RW
Pi_1
Port Pi_1 bit
Input mode (The PDi_j bit (j = 0 to 7) in the PDi register = 0) Read: Return the pin level. Write: Write to the port latch. Output mode (The PDi_j bit in the PDi register = 1) Read: Return the port latch value. Write: Write to the port latch and the port latch value is output from the pin. 0: "L" level 1: "H" level
RW
Pi_2
Port Pi_2 bit
RW
Pi_3
Port Pi_3 bit
RW
Pi_4
Port Pi_4 bit
RW
Pi_5
Port Pi_5 bit
RW
Pi_6
Port Pi_6 bit
RW
Pi_7
Port Pi_7 bit
RW
NOTES: 1. In memory expansion mode and microprocessor mode, the Pi register corresponding to the following bus control pins cannot be written: A0 to A22, A23, D0 to D15, CS0 to CS3, WRL/ WR, WRH/BHE, RD, BCLK/ALE/CLKOUT, HLDA/ALE, HOLD, ALE, RDY. 2. Ports P11 to P15 are provided in the 144-pin package only. 3. P7_0 and P7_1 are N-channel open drain output ports. The pins are placed into high-impedance states when the corresponding bits to P7_0 and P7_1 are set to 1. 4. The P8_5 bit is a read-only bit. 5. Nothing is implemented to bits P11_5 to P11_7 in the P11 register and the P14_7 bit in the P14 register. Write a 0. A read from these bits returns undefined value.
Figure 25.6
P0 to P15 Registers
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register A0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS0
Bit Symbol PS0_0 Bit Name Port P6_0 output function select bit Port P6_1 output function select bit Port P6_2 output function select bit Port P6_3 output function select bit Port P6_4 output function select bit Port P6_5 output function select bit Port P6_6 output function select bit Port P6_7 output function select bit
Address 03B0h
Function 0: I/O port/peripheral function input 1: Select by the PSL0_0 bit 0: I/O port/peripheral function input 1: Select by the PSL0_1 bit 0: I/O port/peripheral function input 1: Select by the PSL0_2 bit 0: I/O port/peripheral function input 1: Select by the PSL0_3 bit 0: I/O port/peripheral function input 1: Select by the PSL0_4 bit 0: I/O port/peripheral function input 1: Select by the PSL0_5 bit 0: I/O port/peripheral function input 1: Select by the PSL0_6 bit 0: I/O port/peripheral function input 1: Select by the PSL0_7 bit
After Reset 00h
RW RW
PS0_1
RW
PS0_2
RW
PS0_3
RW
PS0_4
RW
PS0_5
RW
PS0_6
RW
PS0_7
RW
Function Select Register A1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS1
Bit Symbol PS1_0 Bit Name
Address 03B1h
Function 0: I/O port/peripheral function input 1: Select by the PSL1_0 bit 0: I/O port/peripheral function input 1: Select by the PSL1_1 bit 0: I/O port/peripheral function input 1: Select by the PSL1_2 bit 0: I/O port/peripheral function input 1: Select by the PSL1_3 bit 0: I/O port/peripheral function input 1: Select by the PSL1_4 bit 0: I/O port/peripheral function input 1: Select by the PSL1_5 bit 0: I/O port/peripheral function input 1: Select by the PSL1_6 bit 0: I/O port/peripheral function input 1: Select by the PSL1_7 bit
After Reset 00h
RW RW
Port P7_0 output function select bit Port P7_1 output function select bit Port P7_2 output function select bit Port P7_3 output function select bit Port P7_4 output function select bit Port P7_5 output function select bit Port P7_6 output function select bit Port P7_7 output function select bit
PS1_1
RW
PS1_2
RW
PS1_3
RW
PS1_4
RW
PS1_5
RW
PS1_6
RW
PS1_7
RW
Figure 25.7
PS0 Register, PS1 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 468 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register A2
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol PS2
Bit Symbol PS2_0 Bit Name Port P8_0 output function select bit Port P8_1 output function select bit Port P8_2 output function select bit Reserved bits
Address 03B4h
Function 0: I/O port/peripheral function input 1: Select by the PSL2_0 bit 0: I/O port/peripheral function input 1: Select by the PSL2_1 bit 0: I/O port/peripheral function input 1: Select by the PSL2_2 bit Set to 0
After Reset 00X0 0000b
RW RW
PS2_1
RW
PS2_2
RW
- (b4-b3) - (b5) - (b7-b6)
RW
Unimplemented. Write 0. Read as undefined value. Reserved bits Set to 0
-
RW
Function Select Register A3(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS3
Bit Symbol PS3_0 Bit Name Port P9_0 output function select bit Port P9_1 output function select bit Port P9_2 output function select bit Port P9_3 output function select bit Port P9_4 output function select bit Port P9_5 output function select bit Port P9_6 output function select bit Port P9_7 output function select bit
Address 03B5h
Function 0: I/O port/peripheral function input 1: Select by the PSL3_0 bit 0: I/O port/peripheral function input 1: Select by the PSL3_1 bit 0: I/O port/peripheral function input 1: Select by the PSL3_2 bit 0: I/O port/peripheral function input 1: RTS3 0: I/O port/peripheral function input 1: RTS4 0: I/O port/peripheral function input 1: CLK4 output 0: I/O port/peripheral function input 1: Select by the PSC3_6 bit 0: I/O port/peripheral function input 1: Select by the PSL3_7 bit
After Reset 00h
RW RW
PS3_1
RW
PS3_2
RW
PS3_3
RW
PS3_4
RW
PS3_5
RW
PS3_6
RW
PS3_7
RW
NOTE: 1. Set the PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
Figure 25.8
PS2 Register, PS3 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 469 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register A4
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS4
Bit Symbol PS4_0 Bit Name
Address 03B8h
Function 0: I/O port/peripheral function input 1: RTP1_0 0: I/O port/peripheral function input 1: RTP1_1 0: I/O port/peripheral function input 1: RTP1_2 0: I/O port/peripheral function input 1: RTP1_3 0: I/O port/peripheral function input 1: RTP3_0 0: I/O port/peripheral function input 1: RTP3_1 0: I/O port/peripheral function input 1: RTP3_2 0: I/O port/peripheral function input 1: RTP3_3
After Reset 00h
RW RW
Port P10_0 output function select bit Port P10_1 output function select bit Port P10_2 output function select bit Port P10_3 output function select bit Port P10_4 output function select bit Port P10_5 output function select bit Port P10_6 output function select bit Port P10_7 output function select bit
PS4_1
RW
PS4_2
RW
PS4_3
RW
PS4_4
RW
PS4_5
RW
PS4_6
RW
PS4_7
RW
Function Select Register A5(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol PS5
Bit Symbol PS5_0 Bit Name
Address 03B9h
Function 0: I/O port/peripheral function input 1: Select by the PSL5_0 bit 0: I/O port/peripheral function input 1: Select by the PSL5_1 bit 0: I/O port/peripheral function input 1: Select by the PSL5_2 bit 0: I/O port/peripheral function input 1: Select by the PSL5_3 bit Set to 0
After Reset XXX0 0000b
RW RW
Port P11_0 output function select bit Port P11_1 output function select bit Port P11_2 output function select bit Port P11_3 output function select bit Reserved bit Unimplemented. Write 0. Read as undefined value.
PS5_1
RW
PS5_2
RW
PS5_3
RW
- (b4) - (b7-b5)
RW
-
NOTE: 1. The PS5 register is provided in the 144-pin package only.
Figure 25.9
PS4 Register, PS5 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 470 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register A6(1)
b7 b6 b5 b4 b3 b2 b1 b0
0000
0
Symbol PS6
Bit Symbol PS6_0 Bit Name Port P12_0 output function select bit Port P12_1 output function select bit Reserved bit Port P12_3 output function select bit Reserved bits
Address 03BCh
Function 0: I/O port 1: Select by the PSL6_0 bit 0: I/O port/peripheral function input 1: Select by the PSL6_1 bit Set to 0 0: I/O port/peripheral function input 1: Select by the PSL6_3 bit Set to 0
After Reset 00h
RW RW
PS6_1
RW
- (b2)
PS6_3
RW
RW
- (b7-b4)
RW
NOTE: 1. The PS6 register is provided in the 144-pin package only.
Function Select Register A7(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PS7
Bit Symbol PS7_0 Bit Name Port P13_0 output function select bit Port P13_1 output function select bit Port P13_2 output function select bit Port P13_3 output function select bit Port P13_4 output function select bit Port P13_5 output function select bit Port P13_6 output function select bit Port P13_7 output function select bit
Address 03BDh
Function 0: I/O port 1: Select by the PSL7_0 bit 0: I/O port 1: Select by the PSL7_1 bit 0: I/O port 1: Select by the PSL7_2 bit 0: I/O port 1: Select by the PSL7_3 bit 0: I/O port 1: Select by the PSL7_4 bit 0: I/O port/peripheral function input 1: Select by the PSL7_5 bit 0: I/O port/peripheral function input 1: Select by the PSL7_6 bit 0: I/O port 1: Select by the PSL7_7 bit
After Reset 00h
RW RW
PS7_1
RW
PS7_2
RW
PS7_3
RW
PS7_4
RW
PS7_5
RW
PS7_6
RW
PS7_7
RW
NOTE: 1. The PS7 register is provided in the 144-pin package only.
Figure 25.10
PS6 Register, PS7 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 471 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register A8(1)
b7 b6 b5 b4 b3 b2 b1 b0
000
Symbol PS8
Bit Symbol PS8_0 Bit Name Port P14_0 output function select bit Port P14_1 output function select bit Port P14_2 output function select bit Port P14_3 output function select bit Reserved bits
Address 03A0h
Function 0: I/O port/peripheral function input 1: OUTC1_4 0: I/O port/peripheral function input 1: OUTC1_5 0: I/O port/peripheral function input 1: OUTC1_6 0: I/O port/peripheral function input 1: OUTC1_7 Set to 0
After Reset X000 0000b
RW RW
PS8_1
RW
PS8_2
RW
PS8_3
RW
- (b6-b4) - (b7)
RW
Unimplemented. Write 0. Read as undefined value.
-
NOTE: 1. The PS8 register is provided in the 144-pin package only.
Function Select Register A9(1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PS9
Bit Symbol PS9_0 Bit Name Port P15_0 output function select bit Port P15_1 output function select bit Reserved bit Port P15_3 output function select bit Port P15_4 output function select bit Reserved bit Port P15_6 output function select bit Port P15_7 output function select bit
Address 03A1h
Function 0: I/O port/peripheral function input 1: Select by the PSL9_0 bit 0: I/O port/peripheral function input 1: Select by the PSL9_1 bit Set to 0 0: I/O port/peripheral function input 1: RTS5 0: I/O port/peripheral function input 1: Select by the PSL9_4 bit Set to 0 0: I/O port/peripheral function input 1: CLK6 output 0: I/O port/peripheral function input 1: RTS6
After Reset 00h
RW RW
PS9_1
RW
- (b2)
PS9_3
RW
RW
PS9_4
RW
- (b5)
PS9_6
RW
RW
PS9_7
RW
NOTE: 1. The PS9 register is provided in the 144-pin package only.
Figure 25.11
PS8 Register, PS9 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 472 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register B0
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol PSL0
Bit Symbol PSL0_0 Bit Name
Address 03B2h
Function 0: RTS0 1: RTP0_0 0: CLK0 output 1: RTP0_1 0: SCL0 output 1: STXD0 0: TXD0/SDA0 output/IrDAOUT 1: Do not set to this value 0: RTS1 1: OUTC2_1/ISCLK2 output 0: CLK1 output 1: Do not set to this value 0: SCL1 output 1: STXD1 0: TXD1/SDA1 output 1: Do not set to this value
After Reset 00h
RW RW
Port P6_0 peripheral function output select bit Port P6_1 peripheral function output select bit Port P6_2 peripheral function output select bit Port P6_3 peripheral function output select bit Port P6_4 peripheral function output select bit Port P6_5 peripheral function output select bit Port P6_6 peripheral function output select bit Port P6_7 peripheral function output select bit
PSL0_1
RW
PSL0_2
RW
PSL0_3
RW
PSL0_4
RW
PSL0_5
RW
PSL0_6
RW
PSL0_7
RW
Function Select Register B1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSL1
Bit Symbol PSL1_0 Bit Name
Address 03B3h
Function 0: Select by the PSC_0 bit 1: TA0OUT output 0: Select by the PSC_1 bit 1: STXD2 0: Select by the PSC_2 bit 1: TA1OUT output 0: Select by the PSC_3 bit 1: V 0: Select by the PSC_4 bit 1: W 0: W 1: Select by the PSC_5 bit 0: Select by the PSC_6 bit 1: TA3OUT output 0: ISCLK0 output 1: Select by the PSD1_7 bit
After Reset 00h
RW RW
Port P7_0 peripheral function output select bit Port P7_1 peripheral function output select bit Port P7_2 peripheral function output select bit Port P7_3 peripheral function output select bit Port P7_4 peripheral function output select bit Port P7_5 peripheral function output select bit Port P7_6 peripheral function output select bit Port P7_7 peripheral function output select bit
PSL1_1
RW
PSL1_2
RW
PSL1_3
RW
PSL1_4
RW
PSL1_5
RW
PSL1_6
RW
PSL1_7
RW
Figure 25.12
PSL0 Register, PSL1 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 473 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register B2
b7 b6 b5 b4 b3 b2 b1 b0
00
001
Symbol PSL2
Bit Symbol PSL2_0 Bit Name
Address 03B6h
Function 0: TA4OUT output 1: U 0: U 1: Select by the PSC2_1 bit 0: Do not set to this value 1: Select by the PSC2_2 bit Set to 0
After Reset 00X0 0000b
RW RW
Port P8_0 peripheral function output select bit Port P8_1 peripheral function output select bit Port P8_2 peripheral function output select bit Reserved bits Unimplemented. Write 0. Read as undefined value. Reserved bits
PSL2_1
RW
PSL2_2
RW
- (b4-b3) - (b5) - (b7-b6)
RW
-
Set to 0
RW
Function Select Register B3
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol PSL3
Bit Symbol PSL3_0 Bit Name
Address 03B7h
Function 0: CLK3 output 1: Do not set to this value 0: SCL3 output 1: STXD3 0: TXD3/SDA3 output 1: OUTC2_0/ISTXD2/IEOUT 0: Peripheral function input 1: DA0 0: Peripheral function input 1: DA1
After Reset 00h
RW RW
Port P9_0 peripheral function output select bit Port P9_1 peripheral function output select bit Port P9_2 peripheral function output select bit Port P9_3 peripheral function output select bit (1) Port P9_4 peripheral function output select bit (1) Port P9_5 peripheral function output select bit (1) Port P9_6 peripheral function output select bit (1) Port P9_7 peripheral function output select bit
PSL3_1
RW
PSL3_2
RW
PSL3_3
RW
PSL3_4
RW
PSL3_5
0: Peripheral function input except ANEX0 1: ANEX0 0: Peripheral function input except ANEX1 1: ANEX1 0: SCL4 output 1: STXD4
RW
PSL3_6
RW
PSL3_7
RW
NOTE: 1. If DA0, DA1, ANEX0, and ANEX1 are used with the PSL3_i bit (i = 3 to 6) setting to 0, current consumption may increase.
Figure 25.13
PSL2 Register, PSL3 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 474 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register B5(1)
b7 b6 b5 b4 b3 b2 b1 b0
00000
Symbol PSL5
Bit Symbol PSL5_0 Bit Name
Address 03BBh
Function 0: OUTC1_0/ISTXD1 1: Do not set to this value 0: OUTC1_1/ISCLK1 output 1: Do not set to this value 0: OUTC1_2 1: Do not set to this value 0: OUTC1_3 1: Do not set to this value Set to 0
After Reset XXX0 0000b
RW RW
Port P11_0 peripheral function output select bit Port P11_1 peripheral function output select bit Port P11_2 peripheral function output select bit Port P11_3 peripheral function output select bit Reserved bit Unimplemented. Write 0. Read as undefined value.
PSL5_1
RW
PSL5_2
RW
PSL5_3
RW
- (b4) - (b7-b5)
RW
-
NOTE: 1. The PSL5 register is provided in the 144-pin package only.
Function Select Register B6(1)
b7 b6 b5 b4 b3 b2 b1 b0
00000000
Symbol PSL6
Bit Symbol PSL6_0 Bit Name
Address 03BEh
Function 0: Select by the PSC6_0 bit 1: Do not set to this value 0: Select by the PSC6_1 bit 1: Do not set to this value Set to 0 0: Select by the PSC6_3 bit 1: Do not set to this value Set to 0
After Reset 00h
RW RW
Port P12_0 peripheral function output select bit Port P12_1 peripheral function output select bit Reserved bit Port P12_3 peripheral function output select bit Reserved bits
PSL6_1
RW
- (b2)
PSL6_3
RW
RW
- (b7-b4)
RW
NOTE: 1. The PSL6 register is provided in the 144-pin package only.
Figure 25.14
PSL5 Register, PSL6 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 475 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register B7(1)
b7 b6 b5 b4 b3 b2 b1 b0
00000000
Symbol PSL7
Bit Symbol PSL7_0 Bit Name
Address 03BFh
Function 0: OUTC2_4 1: Do not set to this value 0: OUTC2_5 1: Do not set to this value 0: OUTC2_6 1: Do not set to this value 0: OUTC2_3 1: Do not set to this value 0: OUTC2_0/ISTXD2/IEOUT 1: Do not set to this value 0: OUTC2_2 1: Do not set to this value 0: OUTC2_1/ISCLK2 output 1: Do not set to this value 0: OUTC2_7 1: Do not set to this value
After Reset 00h
RW RW
Port P13_0 peripheral function output select bit Port P13_1 peripheral function output select bit Port P13_2 peripheral function output select bit Port P13_3 peripheral function output select bit Port P13_4 peripheral function output select bit Port P13_5 peripheral function output select bit Port P13_6 peripheral function output select bit Port P13_7 peripheral function output select bit
PSL7_1
RW
PSL7_2
RW
PSL7_3
RW
PSL7_4
RW
PSL7_5
RW
PSL7_6
RW
PSL7_7
RW
NOTE: 1. The PSL7 register is provided in the 144-pin package only.
Function Select Register B9(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol PSL9
Bit Symbol PSL9_0 Bit Name
Address 03A3h
Function 0: ISTXD0 1: TXD5 0: ISCLK0 output 1: CLK5 output
After Reset XXX0 XX00b
RW RW
Port P15_0 peripheral function output select bit Port P15_1 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. Port P15_4 peripheral function output select bit Unimplemented. Write 0. Read as undefined value.
PSL9_1
RW
- (b3-b2)
PSL9_4
-
0: Do not set to this value 1: TXD6
RW
- (b7-b5)
-
NOTE: 1. The PSL9 register is provided in the 144-pin package only.
Figure 25.15
PSL7 Register, PSL9 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 476 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register C
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSC
Bit Symbol PSC_0 Bit Name
Address 03AFh
Function 0: TXD2/SDA2 output 1: Select by the PSD1_0 bit 0: SCL2 output 1: Select by the PSD1_1 bit 0: CLK2 output 1: V 0: RTS2 1: OUTC1_0/ISTXD1 0: TA2OUT output 1: Select by the PSD1_4 bit 0: OUTC1_2 1: RTP2_1 0: Select by the PSD1_6 bit 1: CAN0OUT(1) 0: P10_4 to P10_7 or KI0 to KI3 1: AN_4 to AN_7(2)
After Reset 00h
RW RW
Port P7_0 peripheral function output select bit Port P7_1 peripheral function output select bit Port P7_2 peripheral function output select bit Port P7_3 peripheral function output select bit Port P7_4 peripheral function output select bit Port P7_5 peripheral function output select bit Port P7_6 peripheral function output select bit Port P10_4 to P10_7 peripheral function input select bit
PSC_1
RW
PSC_2
RW
PSC_3
RW
PSC_4
RW
PSC_5
RW
PSC_6
RW
PSC_7
RW
NOTES: 1. Set to 0 in M32C/87B. 2. Set bits ILVL2 to ILVL0 in the KUPIC register to 000b (interrupt disabled) to change the PSC_7 bit. If AN_4 to AN_7 are used with the PSC_7 bit setting to 0, current consumption may increase.
Function Select Register C2
b7 b6 b5 b4 b3 b2 b1 b0
1
Symbol PSC2
Bit Symbol Bit Name
Address 03ACh
Function
After Reset XXXX X00Xb
RW
- (b0)
PSC2_1
Unimplemented. Write 0. Read as undefined value. Port P8_1 peripheral function output select bit Port P8_2 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. 0: Do not set to this value 1: Select by the PSD2_1 bit 0: CAN0OUT 1: CAN1OUT(1)
-
RW
PSC2_2
RW
- (b7-b3)
-
NOTE: 1. Set to 0 in M32C/87A. Do not set the PSC2_2 bit in M32C/87B. Write a 0, if necessary.
Figure 25.16
PSC Register, PSC2 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 477 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register C3
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSC3
Bit Symbol Bit Name
Address 03ADh
Function
After Reset X0XX XXXXb
RW
- (b5-b0)
PSC3_6
Unimplemented. Write 0. Read as undefined value. Port P9_6 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. 0: TXD4/SDA4 output 1: CAN1OUT(1)
-
RW
- (b7)
-
NOTE: 1. Set to 0 in M32C/87A and M32C/87B.
Function Select Register C6(1)
b7 b6 b5 b4 b3 b2 b1 b0
1
11
Symbol PSC6
Bit Symbol PSC6_0 Bit Name
Address 03AAh
Function 0: Do not set to this value 1: TXD6 0: Do not set to this value 1: CLK6 output
After Reset XXXX 0X00b
RW RW
Port P12_0 peripheral function output select bit Port P12_1 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. Port P12_3 peripheral function output select bit Unimplemented. Write 0. Read as undefined value.
PSC6_1
RW
- (b2)
PSC6_3
-
0: Do not set to this value 1: RTS6
RW
- (b7-b4)
-
NOTE: 1. The PSC6 register is provided in the 144-pin package only.
Figure 25.17
PSC3 Register, PSC6 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 478 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register D1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSD1
Bit Symbol PSD1_0 Bit Name
Address 03A7h
Function 0: OUTC2_0/ISTXD2/IEOUT 1: Select by the PSE1_0 bit 0: OUTC2_2 1: Select by the PSE1_1 bit
After Reset 00X0 XX00b
RW RW
Port P7_0 peripheral function output select bit Port P7_1 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. Port P7_4 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. Port P7_6 peripheral function output select bit Port P7_7 peripheral function output select bit
PSD1_1
RW
- (b3-b2)
PSD1_4
-
0: OUTC1_1/ISCLK1 output 1: RTP2_0
RW
- (b5)
PSD1_6
-
0: ISTXD0 1: Select by the PSE1_6 bit 0: OUTC1_4 1: Select by the PSE1_7 bit
RW
PSD1_7
RW
Function Select Register D2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSD2
Bit Symbol Bit Name
Address 03A8h
Function
After Reset XXXX XX0Xb
RW
- (b0)
PSD2_1
Unimplemented. Write 0. Read as undefined value. Port P8_1 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. 0: OUTC1_5 1: Select by the PSE2_1 bit
-
RW
- (b7-b2)
-
Figure 25.18
PSD1 Register, PSD2 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 479 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Function Select Register E1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSE1
Bit Symbol PSE1_0 Bit Name
Address 03ABh
Function 0: OUTC1_6 1: RTP0_2 0: OUTC1_7 1: RTP0_3
After Reset 00XX XX00b
RW RW
Port P7_0 peripheral function output select bit Port P7_1 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. Port P7_6 peripheral function output select bit Port P7_7 peripheral function output select bit
PSE1_1
RW
- (b5-b2)
PSE1_6
-
0: OUTC1_3 1: TXD5 0: CLK5 output 1: RTP2_2
RW
PSE1_7
RW
Function Select Register E2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PSE2
Bit Symbol Bit Name
Address 03A4h
Function
After Reset XXXX XX0Xb
RW
- (b0)
PSE2_1
Unimplemented. Write 0. Read as undefined value. Port P8_1 peripheral function output select bit Unimplemented. Write 0. Read as undefined value. 0: RTS5 1: RTP2_3
-
RW
- (b7-b2)
-
Figure 25.19
PSE1 Register, PSE2 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 480 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Pull-Up Control Register 0(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0
Bit Symbol PU00 Bit Name P0_0 to P0_3 pull-up
Address 03F0h
Function
After Reset 00h
RW RW
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
PU01
P0_4 to P0_7 pull-up
RW
PU02
P1_0 to P1_3 pull-up
RW
PU03
P1_4 to P1_7 pull-up
RW
PU04
P2_0 to P2_3 pull-up
RW
PU05
P2_4 to P2_7 pull-up
RW
PU06
P3_0 to P3_3 pull-up
RW
PU07
P3_4 to P3_7 pull-up
RW
NOTE: 1. In memory expansion mode and microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as bus control pins. When using as I/O ports, it can be selected whether the ports are pulled up or not.
Pull-Up Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1
Bit Symbol PU10 Bit Name P4_0 to P4_3 pull-up
Address 03F1h
Function
After Reset XXXX 0000b
RW RW
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
PU11
P4_4 to P4_7 pull-up
RW
PU12
P5_0 to P5_3 pull-up
RW
PU13
P5_4 to P5_7 pull-up Unimplemented. Write 0. Read as undefined value.
RW
- (b7-b4)
-
NOTE: 1. In memory expansion mode and microprocessor mode, set each bit in the PUR0 register to 0 since port P0 to P5 are used as bus control pins. When using as I/O ports, it can be selected whether the ports are pulled up or not.
Figure 25.20
PUR0 Register, PUR1 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 481 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Pull-Up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2
Bit Symbol PU20 Bit Name P6_0 to P6_3 pull-up
Address 03DAh
Function
After Reset 00h
RW RW
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
PU21
P6_4 to P6_7 pull-up
RW
PU22
P7_2 to P7_3 pull-up(1)
RW
PU23
P7_4 to P7_7 pull-up
RW
PU24
P8_0 to P8_3 pull-up
RW
PU25
P8_4 to P8_7 pull-up(2)
RW
PU26
P9_0 to P9_3 pull-up
RW
PU27
P9_4 to P9_7 pull-up
RW
NOTES: 1. P7_0 and P7_1 cannot be pulled up. 2. P8_5 cannot be pulled up internally.
Figure 25.21
PUR2 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 482 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Pull-Up Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
<144-pin package>
Address 03DBh
Bit Name
Symbol PUR3
Bit Symbol PU30
After Reset 00h Function
RW RW
P10_0 to P10_3 pull-up
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
PU31
P10_4 to P10_7 pull-up
RW
PU32
P11_0 to P11_3 pull-up
RW
PU33
P11_4 pull-up
RW
PU34
P12_0 to P12_3 pull-up
RW
PU35
P12_4 to P12_7 pull-up
RW
PU36
P13_0 to P13_3 pull-up
RW
PU37
P13_4 to P13_7 pull-up
RW
Pull-Up Control Register 3
b7 b6 b5 b4 b3 b2 b1 b0
<100-pin package>
Address 03DBh Bit Name Function
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
000000
Symbol PUR3
Bit Symbol PU30
After Reset 00h
RW RW
P10_0 to P10_3 pull-up
PU31
P10_4 to P10_7 pull-up
RW
- (b7-b2)
Reserved bits
Set to 0
RW
Figure 25.22
PUR3 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 483 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Pull-Up Control Register 4(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR4 Bit Symbol
PU40
Address 03DCh Bit Name
P14_0 to P14_3 pull-up
After Reset XXXX 0000b Function
RW RW
Pull-up setting for the corresponding ports 0: Not pulled up 1: Pulled up
PU41
P14_4 to P14_6 pull-up
RW
PU42
P15_0 to P15_3 pull-up
RW
PU43
P15_4 to P15_7 pull-up Unimplemented. Write 0. Read as undefined value.
RW
- (b7-b4)
-
NOTE: 1. Set the PUR4 register to 00h in the 100-pin package.
Figure 25.23
PUR4 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 484 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol PCR
Bit Symbol PCR0 Bit Name Port P1 control bit(1)
Address 03FFh
Function 0: CMOS output 1: N-channel open drain output(2) Set to 0
After Reset XXXX X000b
RW RW
- (b2-b1) - (b7-b3)
Reserved bits Unimplemented. Write 0. Read as undefined value.
RW
-
NOTES: 1. In memory expansion mode and microprocessor mode, set the PCR0 bit to 0 since port P1 is used as data bus . When using port P1 as an I/O port, CMOS or N-channel open drain output can be selected. 2. This function is designed to use port P1 as pseudo open drain by always turning off P channel of the CMOS port . Therefore, the absolute maximum rating of the input voltage is from -0.3 V to VCC2 + 0.3 V.
Input Function Select Register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol IPS
Bit Symbol Bit Name Group 0 input pin select bit 0
Address 0178h
Function
After Reset 00h
RW
IPS0
Assigns ISCLK0 input and ISRXD0 to the following ports 0: P7_7, P8_0 1: P15_1, P15_2 Assigns INPC1_0, INPC1_1/ISCLK1 input/ INPC1_2/ISRXD1, INPC1_3, INPC1_4, INPC1_5, INPC1_6, and INPC1_7 to the following ports. 0: P7_3, P7_4, P7_5, P7_6, P7_7, P8_1, P7_0, P7_1 1: P11_0, P11_1, P11_2, P11_3, P14_0, P14_1, P14_2, P14_3 0: Except AN15 1: AN15 0: P7_7 1: P8_3
b5 b4
RW
IPS1
Group 1 input pin select bit 1
RW
IPS2
Port P15 peripheral function input select bit (1) CAN0IN function pin select bit
RW
IPS3
RW
IPS4 ISRXD2/IEIN function pin select bit IPS5 ISCLK2 function input pin select bit Reserved bit
0 0: P7_1 0 1: P9_1 1 0: P13_5 1 1: Do not set to this value. 0: P6_4 1: P13_6 Set to 0
RW
IPS6
RW
- (b7)
RW
NOTE: 1. If AN15_0 to AN15_7 are used with the IPS2 bit setting to 0, current consumption may increase.
Figure 25.24
PCR Register, IPS Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 485 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
25. Programmable I/O Ports
Input Function Select Register A
b7 b6 b5 b4 b3 b2 b1 b0
0000
00
Symbol IPSA
Bit Symbol IPSA_0 Bit Name
Address 0179h
Function 0: P8_0, P8_1, INT1 1: P7_6, P7_7, INT0 Set to 0 0: P9_5 1: P8_3(1) Set to 0
After Reset 00h
RW RW
Intelligent I/O two-phase pulse input pin switch bit Reserved bits
- (b2-b1)
IPSA_3
RW
CAN1IN function pin select bit
RW
- (b7-b4)
Reserved bits
RW
NOTE: 1. Do not set the IPSA_3 bit in M32C/87A and M32C/87B. Write a 0, if necessary.
Input Function Select Register B
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IPSB
Bit Symbol IPSB_0 Bit Name Port P15_0 input function select bit Port P15_1 input function select bit Port P15_2 input function select bit Port P15_3 input function select bit Port P15_4 input function select bit Port P15_5 input function select bit Port P15_6 input function select bit Port P15_7 input function select bit
Address 0177h
Function 0: Except AN15_0(2) 1: AN15_0 0: Except AN15_1(2) 1: AN15_1 0: Except AN15_2(2) 1: AN15_2 0: Except AN15_3(2) 1: AN15_3 0: Except AN15_4(2) 1: AN15_4 0: Except AN15_5(2) 1: AN15_5 0: Except AN15_6(2) 1: AN15_6 0: Except AN15_7(2) 1: AN15_7
After Reset 00h
RW RW
IPSB_1
RW
IPSB_2
RW
IPSB_3
RW
IPSB_4
RW
IPSB_5
RW
IPSB_6
RW
IPSB_7
RW
NOTES: 1. The IPSB register is enabled when the IPS2 bit in the IPS register is se to 0 (except AN15). 2. If the bits AN15_0 to AN15_7 are used with bits IPSB_0 to IPSB_7 setting to 0, current consumption may increase.
Figure 25.25
IPSA Register, IPSB Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 486 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 25.1 Unassigned Pin Handling in Single-Chip Mode
Pin Name P0 to P15 (excluding P8_5)(1) XOUT(2) NMI (P8_5) VREF Handling
25. Programmable I/O Ports
Set pins to input mode and connect each pin to VSS via a resistor (pull-down), or set pins to output mode and leave them open Leave the pin open Connect the pin to VCC1 via a resistor (pull-up) Connect the pin to VSS
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. It is when the external clock is input to the XIN pin.
Table 25.2
Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode
Pin Name Handling Set pins to input mode and connect each pin to VSS via a resistor (pull-down), or set pins to output mode and leave them open Leave the pin open Connect the pin to VCC2 via a resistor (pull-up) Connect the pin to VCC1 via a resistor (pull-up) Connect the pin to VSS
P1, P6 to P15 (excluding P8_5)(1) BHE, ALE, HLDA, XOUT(2), BCLK HOLD, RDY NMI(P8_5) VREF
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. It is when the external clock is applied to the XIN pin.
MCU
P0 to P15(1) (except for P8_5) (Input mode)
MCU
P1, P6 to P15(1) (except for P8_5) (Input mode)
(Input mode) (Output mode) NMI (P8_5) XOUT AVCC Open VCC1 Open VCC1
In single-chip mode
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
...
BYTE AVSS VREF
...
VSS
(Input mode) (Output mode) NMI (P8_5) BHE HLDA ALE XOUT BCLK HOLD RDY AVCC AVSS VREF VSS Open VCC1
In memory expansion mode and microprocessor mode
...
Open VCC2 VCC1
...
Figure 25.26
Unassigned Pin Handling
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 487 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 25.3
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
25. Programmable I/O Ports
Port P6 Peripheral Function Output Control
PS0 Register 0: P6_0/CTS0/SS0 1: Select by the PSL0_0 bit 0: P6_1/CLK0 input 1: Select by the PSL0_1 bit 0: P6_2/RXD0/SCL0 input/IrDAIN 1: Select by the PSL0_2 bit 0: P6_3/SRXD0/SDA0 input 1: Select by the PSL0_3 bit 0: P6_4/CTS1/SS1/ISCLK2 input 1: Select by the PSL0_4 bit 0: P6_5/CKL1 input 1: Select by the PSL0_5 bit 0: P6_6/RXD1/SCL1 input 1: Select by the PSL0_6 bit 0: P6_7/SRXD1/SDA1 input 1: Select by the PSL0_7 bit 0: RTS0 1: RTP0_0 0: CLK0 output 1: RTP0_1 0: SCL0 output 1: STXD0 0: TXD0/SDA0 output/IrDAOUT 1: Do not set to this value 0: RTS1 1: OUTC2_1/ISCLK2 output 0: CLK1 output 1: Do not set to this value 0: SCL1 output 1: STXD1 0: TXD1/SDA1 output 1: Do not set to this value PSL0 Register
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 488 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 25.4
Bit 0
25. Programmable I/O Ports
Port P7 Peripheral Function Output Control
PS1 Register PSL1 Register PSC Register 0: TXD2/ SDA2 output 1: Select by the PSD1_0 bit PSD1 Register 0: OUTC2_0/ ISTXD2/IEOUT 1: Select by the PSE1_0 bit PSE1 Register 0: OUTC1_6 1: RTP0_2
0: Select by the 0: P7_0/ PSC_0 bit TA0OUT input/ SRXD2/INPC1_6/ 1: TA0OUT output SDA2 input 1: Select by the PSL1_0 bit 0: P7_1/TA0IN/ TB5IN/RXD2/ SCL2 input/ INPC1_7/ ISRXD2/IEIN 1: Select by the PSL1_1 bit 0: P7_2/TA1OUT input/CLK2 input 1: Select by the PSL1_2 bit 0: P7_3/TA1IN/ CTS2/SS2/ INPC1_0 1: Select by the PSL1_3 bit 0: P7_4/TA2OUT input/INPC1_1/ ISCLK1 input 1: Select by the PSL1_4 bit 0: Select by the PSC_1 bit 1: STXD2
Bit 1
0: SCL2 output 1: Select by the PSD1_1 bit
0: OUTC2_2 1: Select by the PSE1_1 bit
0: OUTC1_7 1: RTP0_3
Bit 2
0: Select by the PSC_2 bit 1: TA1OUT output 0: Select by the PSC_3 bit 1: V
0: CLK2 output 1: V
Set to 0
Set to 0
Bit 3
0: RTS2 1:OUTC1_0/ ISTXD1
Set to 0
Set to 0
Bit 4
0: Select by the PSC_4 bit 1: W
0: TA2OUT output 1: Select by the PSD1_4 bit
0: OUTC1_1 ISCLK1 output 1: RTP2_0
Set to 0
Bit 5
0: P7_5/TA2IN/ 0: W INPC1_2/ISRXD1 1: Select by the 1: Select by the PSC_5 bit PSL1_5 bit 0: P7_6/TA3OUT input/INPC1_3 1: Select by the PSL1_6 bit 0: P7_7/TA3IN/ CAN0IN/CLK5 input/INPC1_4/ ISCLK0 input 1: Select by the PSL1_7 bit 0: Select by the PSC_6 bit 1: TA3OUT output 0: ISCLK0 output 1: Select by the PSD1_7 bit
0: OUTC1_2 1: RTP2_1
Set to 0
Set to 0
Bit 6
0: Select by the PSD1_6 bit 1: CAN0OUT(1) -
0: ISTXD0 1: Selected by the PSE1_6 bit 0: OUTC1_4 1: Select by the PSE1_7 bit
0: OUTC1_3 1: TXD5
Bit 7
0: CLK5 output 1: RTP2_2
NOTE: 1. Set to 0 in M32C/87B.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 489 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 25.5
Bit 0
25. Programmable I/O Ports
Port P8 Peripheral Function Output Control
PS2 Register 0: P8_0/TA4OUT input/RXD5/ ISRXD0 1: Select by the PSL2_0 bit 0: P8_1/TA4IN/ CTS5/INPC1_5 1: Select by the PSL2_1 bit 0: P8_2/INT0 1: Select by the PSL2 _2 bit PSL2 Register 0: TA4OUT output 1: U PSC2 Register Set to 0 PSD2 Register Set to 0 PSE2 Register Set to 0
Bit 1
0: U 1: Select by the PSC2_1 bit 0: Do not set to this value 1: Select by the PSC2_2 bit
0: Do not set to this value 1: Select by the PSD2_1 bit 0: CAN0OUT 1: CAN1OUT(1)
0: OUTC1_5 1: Select by the PSE2_1 bit Set to 0
0: RTS5 1: RTP2_3
Bit 2
Set to 0
Bits 3 to 7 Set to 00000b NOTE: 1. Set to 0 in M32C/87A. Do not set the bit 2 in the PSC2 register in M32C/87B. Write a 0, if necessary.
Table 25.6
Bit 0 Bit 1
Port P9 Peripheral Function Output Control
PS3 Register 0: P9_0/TB0IN/CLK3 input 1: Select by the PSL3_0 bit PSL3 Register 0: CLK3 output 1: Do not set to this value Set to 0 Set to 0 PSC3 Register
0: P9_1/TB1IN/RXD3/SCL3 input/ 0: SCL3 output 1: STXD3 ISRXD2/IEIN 1: Select by the PSL3_1 bit 0: P9_2/TB2IN/SRXD3/ SDA3 input 1: Select by the PSL3_2 bit 0: P9_3/TB3IN/CTS3/SS3/DA0 1: RTS3 0: P9_4/TB4IN/CTS4/SS4/DA1 1: RTS4 0: P9_5/ANEX0/CLK4 input/ CAN1IN/CAN1WU 1: CLK4 output 0: P9_6/SRXD4/ANEX1/ SDA4 input 1: Select by the PSC3_6 bit 0: P9_7/RXD4/ADTRG/ SCL4 input 1: Select by the PSL3_7 bit 0: TXD3/SDA3 output 1: OUTC2_0/ISTXD2/IEOUT 0: Peripheral function input 1: DA0 0: Peripheral function input 1: DA1 0: Peripheral function input except ANEX0 1: ANEX0 0: Peripheral function input except ANEX1 1: ANEX1 0: SCL4 output 1: STXD4
Bit 2
Set to 0
Bit 3 Bit 4 Bit 5
Set to 0 Set to 0 Set to 0
Bit 6
0: TXD4/SDA4 output 1: CAN1OUT(1) Set to 0
Bit 7
NOTE: 1. Set to 0 in M32C/87A and M32C/87B.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 490 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 25.7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
25. Programmable I/O Ports
Port P10 Peripheral Function Output Control (1)
PS4 Register 0: P10_0/AN_0 1: RTP1_0 0: P10_1/AN_1 1: RTP1_1 0: P10_2/AN_2 1: RTP1_2 0: P10_3/AN_3 1: RTP1_3 0: P10_4/AN_4/KI0 1: RTP3_0 0: P10_5/AN_5/KI1 1: RTP3_1 0: P10_6/AN_6/KI2 1: RTP3_2 0: P10_7/AN_7/KI3 1: RTP3_3
Table 25.8
Bit 7
Port P10 Peripheral Function Output Control (2)
PSC Register 0: P10_4 to P10_7 or KI0 to KI3 1: AN_4 to AN_7
Table 25.9
Bit 0 Bit 1 Bit 2 Bit 3
Port P11 Peripheral Function Output Control
PS5 Register 0: P11_0/INPC1_0 1: Select by the PSL5_0 bit 0: P11_1/INPC1_1/ISCLK1 input 1: Select by the PSL5_1 bit 0: P11_2/INPC1_2/ISRXD1 1: Select by the PSL5_2 bit 0: P11_3/INPC1_3 1: Select by the PSL5_3 bit PSL5 Register 0: OUTC1_0/ISTXD1 1: Do not set to this value 0: OUTC1_1/ISCLK1 output 1: Do not set to this value 0: OUTC1_2 1: Do not set to this value 0: OUTC1_3 1: Do not set to this value
Bits 4 to 7 Set to 0000b
Table 25.10
Bit 0 Bit 1 Bit 2 Bit 3
Port P12 Peripheral Function Output Control
PS6 Register PSL6 Register 0: Select by the PSC6_0 bit 1: Do not set to this value 0: Select by the PSC6_1 bit 1: Do not set to this value 0: Select by the PSC6_3 bit 1: Do not set to this value PSC6 Register 0: Do not set to this value 1: TXD6 0: Do not set to this value 1: CLK6 output 0: Do not set to this value 1: RTS6
0: P12_0 1: Select by the PSL6_0 bit 0: P12_1/CLK6 input 1: Select by the PSL6_1 bit Set to 0 0: P12_3/CTS6 1: Select by the PSL6_3 bit
Bits 4 to 7 Set to 0000b
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 491 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 25.11
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
25. Programmable I/O Ports
Port P13 Peripheral Function Output Control
PS7 Register PSL7 Register 0: OUTC2_4 1: Do not set to this value 0: OUTC2_5 1: Do not set to this value 0: OUTC2_6 1: Do not set to this value 0: OUTC2_3 1: Do not set to this value 0: OUTC2_0/ISTXD2/IEOUT 1: Do not set to this value 0: OUTC2_2 1: Do not set to this value 0: OUTC2_1/ISCLK2 output 1: Do not set to this value 0: OUTC2_7 1: Do not set to this value
0: P13_0 1: Select by the PSL7_0 bit 0: P13_1 1: Select by the PSL7_1 bit 0: P13_2 1: Select by the PSL7_2 bit 0: P13_3 1: Select by the PSL7_3 bit 0: P13_4 1: Select by the PSL7_4 bit 0: P13_5/ISRXD2/IEIN 1: Select by the PSL7_5 bit 0: P13_6/ISCLK2 input 1: Select by the PSL7_6 bit 0: P13_7 1: Select by the PSL7_7 bit
Table 25.12
Bit 0 Bit 1 Bit 2 Bit 3
Port P14 Peripheral Function Output Control
PS8 Register
0: P14_0/INPC1_4 1: OUTC1_4 0: P14_1/INPC1_5 1: OUTC1_5 0: P14_2/INPC1_6 1: OUTC1_6 0: P14_3/INPC1_7 1: OUTC1_7
Bits 4 to 7 Set to 0000b
Table 25.13
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Port P15 Peripheral Function Output Control
PS9 Register PSL9 Register 0: ISTXD0 1: TXD5 0: ISCLK0 output 1: CLK5 output Set to 0 0: Do not set to this value 1: TXD6 Set to 0 Set to 0
0: P15_0/AN15_0 1: Select by the PSL9_0 bit 0: P15_1/AN15_1/ISCLK0 input/CLK5 input 1: Select by the PSL9_1 bit Set to 0 0: P15_3/AN15_3/CTS5 1: RTS5 0: P15_4/AN15_4 1: Select by the PSL9_4 bit Set to 0 0: P15_6/AN15_6/CLK6 input 1: CLK6 output 0: P15_7/AN15_7/CTS6 1: RTS6
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 492 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26. Flash Memory
CPU rewrite mode, standard serial I/O mode, and parallel I/O mode can be used to erase and program the flash memory. The flash memory has the user ROM area and boot ROM area, and the rewrite control program for the standard serial I/O mode is stored in the boot ROM area. Table 26.1 lists specifications of the flash memory. (See Tables 1.1 to 1.4 for the items not listed in Table 26.1.) Table 26.2 lists overview of flash memory rewrite mode. Table 26.1 Flash Memory Specifications
Item Flash memory rewrite mode Erase unit Program unit Erase and program control method Protect method Number of commands Erase and program endurance Specification 3 modes (CPU rewrite mode, standard serial I/O mode, parallel I/O mode) On a block basis (See Figure 26.1) 16 bits, 8 bits(1) Software commands control erasing and programming on the flash memory The lock bit protects each block in the flash memory 7 commands 100 times(2)
Flash memory access disable function ROM code protect function (parallel I/O mode) ID code check function (standard serial I/O mode) NOTES: 1. The flash memory can be programmed in 8-bit (byte) units in parallel I/O mode only. 2. The erase and program endurance is the number of erase operations performed on individual blocks. For example, if the block A is erased without programming, the erased and program count stands at one for the block A.
Table 26.2
Flash Memory Rewrite Mode Overview
CPU Rewrite Mode User ROM area is programmed by the CPU executing software commands. EW0 mode: Execute the rewrite control program placed in an area other than the flash memory. EW1 mode: Execute the rewrite control program placed in the flash memory. User ROM area Single-chip mode Memory expansion mode (EW0 mode) Boot mode (EW0 mode) - Standard Serial I/O Mode User ROM area is programmed using a dedicated serial programmer. Standard serial I/O mode 1: Clock synchronous mode in UART1 Standard serial I/O mode 2: Clock asynchronous mode in UART1 Parallel I/O Mode User ROM and boot ROM areas are programmed using a dedicated parallel programmer.
Flash Memory Rewrite Mode Function
Rewritable area Operating mode
User ROM area Boot mode
User ROM area Boot ROM area Parallel I/O mode
ROM programmer
Serial programmer
Parallel programmer
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 493 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.1
Memory Map
Figure 26.1 shows the flash memory map. The user ROM area has an area to store programs, and another 4-Kbyte area as the block A for data storage. The user ROM area is divided into blocks, each of which can be protected (locked) from erasing or programming. The user ROM area can be programmed in CPU rewrite mode, standard serial I/O mode, or parallel I/O mode. The addresses of the boot ROM area are overlapped with the addresses of the user ROM area. The boot ROM area can only be rewritten in parallel I/O mode.
00F000h 00FFFFh F00000h
Block A: 4 Kbytes
Block 20: 64 Kbytes F0FFFFh F10000h Block 19: 64 Kbytes F1FFFFh F20000h Block 18: 64 Kbytes F2FFFFh F30000h Block 17: 64 Kbytes F3FFFFh F40000h Block 16: 64 Kbytes F4FFFFh F50000h Block 15: 64 Kbytes F5FFFFh F60000h Block 14: 64 Kbytes F6FFFFh F70000h Block 13: 64 Kbytes F7FFFFh F80000h Block 12: 64 Kbytes F8FFFFh F90000h Block 11: 64 K bytes F9FFFFh FA0000h Block 10: 64 Kbytes FAFFFFh FB0000h Block 9: 64 Kbytes FBFFFFh FC0000h Block 8: 64 Kbytes FCFFFFh FD0000h Block 7: 64 Kbytes FDFFFFh FE0000h Block 6: 64 Kbytes FEFFFFh FF0000h FF7FFFh FF8000h Block 4: 8 Kbytes FF9FFFh FFA000h Block 3: 8 Kbytes FFBFFFh FFC000h Block 2: 8 Kbytes Blocks 0 to 5 (32 + 8 + 8 + 8 + 4 + 4) Kbytes FFDFFFh FFE000h FFEFFFh FFF000h FFFFFFh Block 1: 4 Kbytes Block 0: 4 Kbytes FFF000h FFFFFFh 4 Kbytes Block 5: 32 Kbytes FF0000h
FFFFFFh
User ROM area
Boot ROM area(1)
NOTES: 1. The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment. This area can be rewritten only in parallel I/O mode. 2. When specifying a block, use the highest-order even address of the specified block. 3. This is a flash memory map in single-chip mode.
Figure 26.1
Flash Memory Map
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.1.1
Boot Mode
Use the following procedure to enter boot mode and a program in the boot ROM area is executed. (1) Apply an "L" (pull-down) to the P6_5 pin or apply an "H" (pull-up) to the P6_7 pin (2) Apply an "L" (pull-down) to the EPM (P5_5) pin and apply an "H" (pull-up) to the CE (P5_0) pin (3) Apply an "H" to the CNVSS pin (4) Perform a hardware reset When switching from the boot ROM area to the user ROM area, set the FMR05 bit in the FMR0 register to 1 (access the user ROM area) by the program placed in the area other than the flash memory. The rewrite control program for standard serial I/O mode is stored in the boot ROM area in the factory default configuration. If a given rewrite control program is written in the boot ROM area, the flash memory can be rewritten along the implemented system.
26.2
Functions to Prevent Access to Flash Memory
Parallel I/O mode has a ROM code protect function, and standard I/O mode has an ID code check function to prevent the flash memory from being read or programmed.
26.2.1
ROM Code Protect Function
The ROM code protect function disables reading or programming the contents of the flash memory in parallel I/ O mode. To use ROM code protect function, set the ROMCP1 bits in the ROMCP address. The ROMCP address is placed in a user ROM area. Figure 26.2 shows the ROMCP address.
26.2.2
ID Code Check Function
The ID code check function is used in standard serial I/O mode. The ID code sent from the serial programmer and the ID code written in the flash memory are checked to see if they match. If these ID codes do not match, the commands sent from the serial programmer are not accepted. However, if the four bytes of the reset vector are set to FFFFFFFFh(1), the ID codes are not checked and all commands can be accepted. The ID code is 7-byte data stored consecutively, beginning with the first byte, into addresses 0FFFFDFh, 0FFFFE3h, 0FFFFEBh, 0FFFFEFh, 0FFFFF3h, 0FFFFF7h, and 0FFFFFBh. To use ID code check function, write the program which specifies the ID code to these addresses. NOTE: 1. FFFFFFFFh is the factory default setting.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
ROM Code Protect Control Address(5)
b7 b6 b5 b4 b3 b2 b1 b0
111111
Symbol ROMCP
Bit Symbol
-
Address FFFFFFh
Bit Name Reserved bits Function Set to 1 to use ROM protect function
Factory setting FFh(4)
RW RW
(b5-b0)
ROMCP1
ROM code protect set bits(1)(2)(3)
0 0: ROM code protect enabled 0 1: ROM code protect enabled 1 0: ROM code protect enabled 1 1: ROM code protect disabled
b7 b6
RW
NOTES: 1. When the ROM code protect is enabled by setting the ROMCP1 bits to values other than 11b, the flash memory is protected against reading or rewriting the contents in parallel I/O mode. 2. Set the bits 5 to 0 to 111111b when the ROMCP1 bits are set to other than 11b. 3. To disable the ROM code protect, erase the block including the ROMCP address in standard serial I/O mode or CPU rewrite mode. 4. The ROMCP address is set to FFh when the block including the ROMCP address is erased. 5. When the ROMCP address is set to 00h or FFh, the ROM code protect function is disabled.
Figure 26.2
ROMCP Address
Address FFFFDFh to FFFFDCh FFFFE3h to FFFFE0h FFFFE7h to FFFFE4h FFFFEBh to FFFFE8h FFFFEFh to FFFFECh FFFFF3h to FFFFF0h FFFFF7h to FFFFF4h FFFFFBh to FFFFF8h FFFFFFh to FFFFFCh ID3 ID4 ID5 ID6 ID7 ROMCP NMI Vector Reset Vector Watchdog Timer Vector ID1 ID2 Undefined Instruction Vector Overflow Vector BRK Instruction Vector Address Match Vector
4 bytes
Figure 26.3
Addresses for Stored ID Codes
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3
CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be programmed by the CPU writing software commands with the MCU mounted on a board. In CPU rewrite mode, only the user ROM area shown in Figure 26.1 can be programmed. The boot ROM area cannot be rewritten. EW0 mode and EW1 mode are provided as CPU rewrite mode. Table 26.3 lists specifications of EW0 mode and EW1 mode. Figures 26.4 and 26.5 show associated registers. Figure 26.6 shows a setting procedure for EW0 mode. Figure 26.7 shows a setting procedure for EW1 mode. Figure 26.8 shows a setting procedure to enter and exit low power mode. Table 26.3
Item Operation
Specifications of EW0 Mode and EW1 Mode
EW0 Mode EW1 Mode * Program the user ROM area by executing * Erase and program a block where the the rewrite control program placed in an rewrite control program is not placed, by area other than the flash memory. executing the rewrite control program placed in the user ROM area. * Single-chip mode * Memory expansion mode * Boot mode * User ROM area (Single-chip mode, memory expansion mode) * Boot ROM area (Boot mode) All commands are available. * Single-chip mode
Processor mode
Areas where a rewrite program can be stored Software command
* User ROM area
* All commands, except read status register command, are available. Read array mode
Flash memory mode after Read status register mode erasing or programming Flash memory status detection
* Read bits FMR00, FMR06, and FMR07 in * Read bits FMR00, FMR06, and FMR07 in the FMR0 register by a program. the FMR0 register by a program. * Execute the read status register command to read bits SR7, SR5, and SR4 in the SRD register. Operating In a hold state (Stop) (I/O port maintains the status which is before executing a command.) Not acknowledged (it is acknowledged after completion of erase or program operation.)
CPU status during erase or program operation Peripheral interrupt request, DMA request, and DMACII request during erase or program operation
Acknowledged(2)
NOTES: 1. In both the EW0 mode and EW1 mode, when an NMI interrupt or watchdog timer interrupt is generated, the erase or program operation in progress is aborted and the interrupt is acknowledged. 2. To use peripheral function interrupts, place interrupt routine programs and the relocatable vector table in an area other than flash memory.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.1
Flash Memory Control Register (FMR0 and FMR1 Registers)
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol FMR0
Bit Symbol FMR00 Bit Name RY/BY status flag
Address 0057h
Function
After Reset 0000 0001b
RW RO
0: BUSY (programming or erasing in progress) (6) 1: READY 0: CPU rewrite mode disabled 1: CPU rewrite mode enabled 0: Lock bit enabled 1: Lock bit disabled 0: Flash memory started 1: Flash memory stopped (enters low-power consumption state and flash memory is initialized) Set to 0 0: Boot ROM area accessed 1: User ROM area accessed 0: Successfully completed 1: Terminated by error 0: Successfully completed 1: Terminated by error
FMR01
CPU rewrite mode select bit (1)(7)
RW
FMR02
Lock bit disable select bit (2)
RW
FMSTP
Flash memory stop bit (3)(5)
RW
- (b4)
FMR05
Reserved bit User ROM area select bit (3) (available in boot mode only) Program status flag (4)
RW
RW
FMR06
RO
FMR07
Erase status flag (4)
RO
NOTES: 1. Set bits FMR01 and FMR02 while the NMI pin level is held "H". 2. To set the FMR02 bit to 1, write a 1 to the FMR02 bit immediately after writing a 0 to the bit while the FMR01 bit is set to 1. Write the value in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. 3. Set bits FMSTP and FMR05 by the program placed in an area other than the flash memory. 4. Bits FMR07 and FMR06 are set to 0 by executing the clear status command. 5. The FMSTP bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled). Bits FMSTP can be set to 1 even when the FMR01 bit is set to 0, but the flash memory does not enter low-power consumption state nor is initialized. 6. Program and read operations by lock bit program command, read lock bit status command, and protect bit program command are included. 7. To change the FMR01 bit from 0 to 1, write a 1 to the FMR01 bit immediately after writing a 0 to it. Write the value in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. To change the FMR01 bit from 1 to 0, enter read array mode first, and then write to the address 0057h in 16-bit units. Set the eight high-order bits to 00h. e.g., To change the FMR01 bit from 1 to 0; Assembly language: mov.w #0000h, 0057h
Figure 26.4
FMR0 Register
26.3.1.1
FMR00 Bit
The FMR00 bit indicates the operating status of the flash memory. It becomes 0 while the program command, block erase command, lock bit program command, or read lock bit status command is being executed, otherwise, it is 1.
26.3.1.2
FMR01 Bit
The flash memory can accept a command when the FMR01 bit is set to 1 (CPU rewrite mode enabled). Set the FMR05 bit to 1 (user ROM area accessed) as well if the MCU is in boot mode.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.1.3
FMR02 Bit
The lock bit becomes invalid by setting the FMR02 bit to 1 (lock bit disabled). (Refer to 26.3.3 Data Protect Function for details.) The lock bit becomes valid by setting the FMR02 bit to 0 (lock bit enabled). The FMR02 bit does not change a lock bit status but disables a lock bit function. When the block erase command is executed while the FMR02 bit is set to 1, the lock bit status changes from 0 (locked) to 1 (unlocked).
26.3.1.4
FMSTP Bit
The FMSTP bit is used to initialize the flash memory control circuits, and also to reduce power consumption in the flash memory. Access to the flash memory is disabled when the FMSTP bit is set to 1 (flash memory stopped). Set the FMSTP bit to 1 by the program placed in an area other than the flash memory. Set the FMSTP bit to 1 in one of the following cases: * A flash memory access error occurs while erasing or programming in EW0 mode (the FMR00 bit does not switch back to 1 (ready)). * To further reduce power consumption in low-power consumption mode or on-chip oscillator low-power consumption mode. Figure 26.8 shows a flow chart illustrating entering and exiting low power mode. Follow the procedure on the flow chart. The flash memory is automatically turned off when entering wait mode or stop mode, and turned back on when exiting wait mode or stop mode. Set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) before entering wait mode or stop mode.
26.3.1.5
FMR05 Bit
The FMR05 bit selects access to either the boot ROM area or user ROM area in boot mode. Set to 0 to access (read) the boot ROM area or set to 1 to access (read, write, or erase) the user ROM area.
26.3.1.6
FMR06 Bit
The FMR06 bit is a read-only bit indicating the status of a program operation. The FMR06 bit becomes 1 when a program error occurs; otherwise, it is 0. Refer to 26.3.5 Full Status Check for details.
26.3.1.7
FMR07 Bit
The FMR07 bit is a read-only bit indicating the status of an erase operation. The FMR07 bit becomes 1 when an erase error occurs; otherwise, it is 0. Refer to 26.3.5 Full Status Check for details.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0
00
0
Symbol FMR1
Bit Symbol Bit Name Reserved bit
Address 0055h
Function Read as undefined value. 0: EW0 mode 1: EW1 mode Read as undefined value.
After Reset 0000 XX0Xb
RW
- (b0)
FMR11
-
EW1 mode select bit(1)
RW
- (b3-b2) - (b5-b4)
FMR16
Reserved bits
-
Reserved bits
Set to 0 0: Locked 1: Unlocked Set to 0
RW
Lock bit status flag
RO
- (b7)
Reserved bit
RW
NOTE: 1. To set the FMR11 bit to 1, write a 1 to the FMR11 bit immediately after writing a 0 to the bit while the FMR01 bit is set to 1.
Write the value in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. Set the FMR11 bit while "H" is applied to the NMI pin. When the FMR01 bit is set to 0, the FMR11 bit also becomes 0.
Figure 26.5
FMR1 Register
26.3.1.8
FMR11 Bit
When the FMR11 bit is set to 0 (EW0 mode), the flash memory enters EW0 mode. When the FMR11 bit is set to 1 (EW1 mode), the flash memory enters EW1 mode.
26.3.1.9
FMR16 Bit
The FMR16 bit is a read-only bit indicating the execution result of the read lock bit status command. When a block, on where the read lock bit status command is executed, is locked, the FMR16 bit becomes 0. When a block, on where the read lock bit status command is executed, is unlocked, the FMR16 bit becomes 1.
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26. Flash Memory
Start Transfer the rewrite control program to an area other than the flash memory
Jump to the rewrite control program transferred to an area other than the flash memory (Execute the following procedure using the rewrite control program transferred to an area other than the flash memory ) MCD register PM1 register: PM12 bit = 1 FMR0 register: FMR05 bit = 1 User ROM area accessed CPU rewrite mode enabled FMR0 register: FMR01 bit = 0 FMR0 register: FMR01 bit = 1 Execute the software commands Execute the read array command FMR0 register: FMR01 bit = 0 CPU rewrite mode disabled - To change the FMR01 bit from 1 to 0, enter read array mode
and then write to address 0057h in 16-bit units. Set the eight high-order bits to 00h.
Set the CPU clock frequency to 10 MHz or lower in CPU rewrite mode Internal memory wait state inserted
- To set the FMR01 bit to 1, write a 1 to the FMR01 bit immediately after writing a 0. Write the value to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. - Set it while "H" is applied to the NMI pin.
End
Figure 26.6
Setting Procedure for EW0 Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Start MCD register PM1 register: PM12 bit = 1 FMR0 register: FMR01 bit = 0 FMR0 register: FMR01 bit = 1 FMR1 register: FMR11 bit = 0 FMR1 register: FMR11 bit = 1 Execute the software commands FMR0 register: FMR01 bit = 0 End
NOTE: 1. Do not use EW1 mode in memory expansion mode or boot mode.
Set the CPU clock frequency to 10 MHz or lower in CPU rewrite mode Internal memory wait state inserted CPU rewrite mode enabled
- To set the FMR01 bit to 1, write a 1 to the FMR01 bit immediately after writing a 0. Write the value to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two setting. - Set it while the NMI pin level is held "H".
Enter EW1 mode
- To set the FMR11 bit to 1, write a 1 to the FMR11 bit immediately after writing a 0 to the bit while the FMR01 bit is set to 1. Do not generate an interrupt or a DMA or DMACII transfer between these two setting. - Set it while "H" is applied to the NMI pin.
CPU rewrite mode disabled - To change the FMR01 bit from 1 to 0, enter read array mode
and then write to address 0057h in 16-bit units. Set the eight high-order bits to 00h.
Figure 26.7
Setting Procedure for EW1 Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Start Transfer the program for low-power consumption mode to an area other than the flash memory
Jump to the program for low-power consumption mode transferred to an area other than the flash memory. Execute the following procedure using the program for low-power consumption mode transferred to an area other than the flash memory FMR0 register: FMR01 bit = 0 FMR0 register: FMR01 bit = 1 FMR0 register: FMSTP bit = 1 Switch the CPU clock source Stop main clock Processing in low-power consumption mode or on-chip oscillator low-power consumption mode Oscillate main clock Switch the CPU clock source FMR0 register: FMSTP bit = 0 FMR0 register: FMR01 bit = 0 Flash memory starts operating CPU rewrite mode disabled - To change the FMR01 bit from 1 to 0, enter read array mode
and then write to address 0057h in 16-bit units. Set the eight high-order bits to 00h.
CPU rewrite mode enabled
- To set the FMR01 bit to 1, write a 1 to the FMR01 bit immediately after writing a 0. Write the value to the FMR0 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. - Set it while "H" is applied to the NMI pin.
Flash memory stops operating
(Enters low-power consumption state and a flash memory is initialized)
When switching the CPU clock source, wait until the new CPU clock source stabilizes.
Wait for tps Jump to a given address in the flash memory
Wait time to stabilize flash memory circuit
- Add tps wait time by a program. - Do not access the flash memory during this wait time.
End
Figure 26.8
Setting Procedure to Enter and Exit Low Power Mode
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.2
Software Commands
Read or write commands and data from or to even addresses in the user ROM area in 16-bit units. When writing a command code, 8 high-order bits (D15 to D8) are ignored. Table 26.4 Software Commands
First Bus Cycle Software Command Read array Read status register Clear status register Program Block erase Lock bit program Read lock bit status Mode Write Write Write Write Write Write Write Address x x x WA x BA x Data (D15 to D0) xxFFh xx70h xx50h xx40h xx20h xx77h xx71h Mode - Read - Write Write Write Write Second Bus Cycle Address - x - WA BA BA BA Data (D15 to D0) - SRD - WD xxD0h xxD0h xxD0h
SRD: Data in the status register (D7 to D0) WA: Write address (The address specified in the first bus cycle is the same even address as the write address specified in the second bus cycle.) WD: 16-bit write data BA: Highest-order even address of a block x: Any even address in the user ROM area xx: 8 high-order bits of command code (ignored)
26.3.2.1
Read Array Command
The read array command is used to read the flash memory. The flash memory enters read array mode when the command code xxFFh is written in the first bus cycle. The content of the specified address can be read in 16-bit units when a read address is specified after the next bus cycle. The flash memory remains in read array mode until the other command is written. Therefore, the contents of multiple addresses can be read in succession.
26.3.2.2
Read Status Register Command
The read status register command is used to read the status register. When the command code xx70h is written in the first bus cycle, the status register can be read after the second bus cycle (refer to 26.3.4 Status Register (SRD Register) for details). To read the status register, read an even address in the user ROM area. Do not execute this command in EW1 mode.
26.3.2.3
Clear Status Register Command
The clear status register command is used to clear the status register. When the command code xx50h is written in the first bus cycle, bits FMR07 and FMR06 in the FMR0 register become 00b and bits SR5 and SR4 in the status register become 00b.
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26. Flash Memory
26.3.2.4
Program Command
The program command is used to write data to the flash memory in 16-bit units. A program operation (program and verify data) starts by writing the command code xx40h in the first bus cycle and data to the write address in the second bus cycle. The address value specified in the first bus cycle must be the same even address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register can be used to determine whether a program operation has been completed or not. The FMR00 bit becomes 0 (busy) during the program operation and becomes 1 (ready) when the program operation is completed. After a program operation is completed, the FMR06 bit in the FMR0 register is used to determine whether a program operation is completed successfully or not. (Refer to 26.3.5 Full Status Check for details.) Do not execute the program command to the same address more than once without executing the block erase command. Figure 26.9 shows a flow chart of the program command. The lock bit can protect each block from being programmed inadvertently. (Refer to 26.3.3 Data Protect Function for details.) In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when a program operation starts.
Start Write the command code xx40h to a write address Write command code and data to the same even address. Write data to the write address
FMR00 = 1? YES Full status check End
NO
Figure 26.9
Program Command
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.2.5
Block Erase Command
The block erase command is used to erase a specified block. By writing the command code xx20h in the first bus cycle and xxD0h to the highest-order even address of a block to be erased in the second bus cycle, an erase operation (erase and verify) starts on the specified block. The FMR00 bit in the FMR0 register can be used to determine whether an erase operation has been completed or not. The FMR00 bit becomes 0 (busy) during the erase operation, and becomes 1 (ready) when the erase operation is completed. After the erase operation is completed, the FMR07 bit in the FMR0 register is used to determine whether the erase operation is completed successfully or not. (Refer to 26.3.5 Full Status Check for details.) Figure 26.10 shows a flow chart of block erase command. The lock bit can protect each block from being erased inadvertently. (Refer to 26.3.3 Data Protect Function for details.) In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when an erase operation starts.
Start Write the command code xx20h Write command code and data to even address Write xxD0h to the highest-order even address of block
FMR00 = 1? YES Full status check End
NO
Figure 26.10
Block Erase Command
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.2.6
Lock Bit Program Command
The lock bit program command is used to set the lock bit of a given block to 0 (locked). By writing the command code xx77h in the first bus cycle and xxD0h to the highest-order even address of a block to be locked in the second bus cycle, the lock bit of the specified block becomes 0. The address specified in the first bus cycle must be the same highest-order even address of the block specified in the second bus cycle. Figure 26.11 shows a flow chart of lock bit program command. Execute the read lock bit status command to read lock bit status (lock bit data). The FMR00 bit in the FMR0 register can be used to determine whether a lock bit program operation has been completed or not. Refer to 26.3.3 Data Protect Function for information on lock bit functions and how to set it to 1 (unlocked). In EW1 mode, do not execute this command to the block where the rewrite control program is stored. In EW0 mode, the flash memory enters read status register mode when a program operation starts.
Start Write the command code xx77h to the highest-order even address of block Write command code and data to the same even address. Write xxD0h to the same highest-order even address of block
FMR00 = 1? YES Full status check End
NO
Figure 26.11
Lock Bit Program Command
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.2.7
Read Lock Bit Status Command
The read lock bit status command reads a lock bit status of a given block. By writing the command code xx71h in the first bus cycle and xxD0h to the highest-order even address of a block in the second bus cycle, the FMR16 bit in the FMR1 register stores information on whether the lock bit of the block is locked or not. Read the FMR16 bit after the FMR00 bit in the FMR0 register becomes 1 (ready). Figure 26.12 shows a flow chart of read lock bit status command.
Start
Write the command code xx71h Write command code and data to the same even address. Write xxD0h to the highest-order even address of block
FMR00 = 1? YES Read FMR16 bit End
NO
Figure 26.12
Read Lock Bit Status Command
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.3.3
Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit protects (locks) each block individually against erasing and programming. This prevents data from being inadvertently erased from or programmed to the flash memory. The following is the block conditions controlled by the lock bit. When the FMR02 bit in the FMR0 register is set to 0 (lock bit enabled); * If lock bit data is set to 0, the block is locked (block is protected against erasing and programming). * If lock bit data is set to 1, the block is unlocked (block can be erased or programmed). When the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled); * The block is unlocked regardless of the lock bit data status (block can be erased or programmed). When the block erase command is executed while the FMR02 bit is set to 1, the target block is erased regardless of the lock bit data status. The lock bit data of the target block becomes 1 when the block erase operation is completed.
26.3.4
Status Register (SRD Register)
In EW0 mode, the Status Register value is returned by reading the flash memory after executing the commands shown below. * Read status register command * Program command * Block erase command * Lock bit program command The Status Register indicates the operating status of the flash memory and whether an erase or program operation has completed successfully or not. The Status Register value is reflected on bits FMR00, FMR06, and FMR07 in the FMR0 register.
26.3.4.1
Sequencer Status (SR7 Bit, FMR00 Bit)
The sequencer status bit indicates the operating status of the flash memory. It becomes 0 while the program command, block erase command, lock bit program command, or read lock bit status command is being executed; otherwise, it is 1.
26.3.4.2
Erase Status (SR5 Bit, FMR07 Bit)
Refer to 26.3.5 Full Status Check.
26.3.4.3
Program Status (SR4 Bit, FMR06 Bit)
Refer to 26.3.5 Full Status Check.
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Table 26.5
Bit in Status Register SR0 (b0) SR1 (b1) SR2 (b2) SR3 (b3) SR4 (b4) SR5 (b5) SR6 (b6) SR7 (b7)
26. Flash Memory
Status Register
Bit in FMR0 Register - - - - FMR06(1) FMR07(1) - FMR00 Status Name Reserved bit Reserved bit Reserved bit Reserved bit Program status Erase status Reserved bit Sequencer status Description 0 - - - - Successfully completed Successfully completed - BUSY 1 - - - - Error Error - READY Value after Reset - - - - 0 0 - 1
b7 to b0: These bits return the value of 8 low-order bits by reading an even address of the flash memory in 16-bit units. NOTE: 1. Bits FMR07 (SR5) and FMR06 (SR4) become 0 by executing the clear status register command. When the FMR07 (SR5) or FMR06 (SR4) bit is 1, the program command, block erase command, lock bit program command, and read lock bit status command cannot be accepted by the flash memory.
26.3.5
Full Status Check
If an error occurs, bits FMR07 and FMR06 in the FMR0 register become 1, indicating the occurrence of an error. Therefore, by checking these status bits (full status check), the execution result can be confirmed. Table 26.6 lists error types and FMR0 register values. Figure 26.13 shows a flow chart of the full status check and handling procedure for each error. Table 26.6 Errors and FMR0 Register Values
Error Error Occurrence Condition * When a command is written incorrectly * When invalid data (data other than xxD0h or xxFFh) is written in the second bus cycle of the lock bit program command or block erase command(1) * When the block erase command is executed to a locked block(2) * When the block erase command is executed to an unlocked block, but the erase operation is not completed successfully * When the program command is executed to a locked block(2) * When the program command is executed to an unlocked block, but the program operation is not completed successfully * The lock bit program command is executed, but the program operation is not completed successfully
FMR0 Register (Status Register) values FMR07 (SR5) 1 FMR06 (SR4) 1
Command sequence error
1
0
Erase error
0
1
Program error
NOTES: 1. The flash memory enters read array mode when the command code xxFFh is written in the second bus cycle of these commands. At the same time, the command code written in the first bus cycle is ignored. 2. When the FMR02 bit in the FMR0 register is set to 1 (lock bit disabled), no error occurs under these conditions.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Start
FMR06 = 1 and FMR07 = 1? NO
YES
Command sequence error
(1) Execute the clear status register command to set bits FMR06 and FMR07 to 0 (successfully completed). (2) Check if the command is written correctly and execute the correct command.
FMR07 = 0 ? YES
NO
Erase error
(1) Execute the clear status register command to set the erase status flag to 0 (successfully completed). (2) Execute the read lock bit status command. Set the FMR02 bit in the FMR0 register to 1 (lock bit disabled) if the lock bit of the block where the error has occurred is set to 0 (locked). (3) Execute the block erase command again. NOTE: 1. If an error still occurs, the block in error cannot be used.
FMR06 = 0 ? YES
NO
Program error
[When a program operation is executed] (1) Execute the clear status register command to set the program status flag to 0. (2) Execute the read lock bit status command. Set the FMR02 bit to 1 if the lock bit of the block where the error has occurred is set to 0. If the lock bit is set to 1 (unlocked), the address in which error has occurred cannot be used as it is. Execute the block erase command to erase the block, in which error has occurred, before executing the program command to program to the same address again. (3) Execute the program command again. NOTE: 2. If an error still occurs, the address in error cannot be used. [When a lock bit program operation is executed] (1) Execute the clear status register command to set the program status flag to 0. (2) Set the FMR02 bit to 1. (3) Execute the block erase command to erase the block where the error has occurred. (4) Execute the lock bit program command again after programming data. NOTE: 3. If an error still occurs, the block in error cannot be used.
End
NOTE: 4. When either the FMR06 or FMR07 bit is 1 (terminated by error), the program command, block erase command, lock bit program command, and read lock bit status command cannot be accepted. Execute the clear status register command before executing these commands.
Figure 26.13
Full Status Check and Handling Procedure for Each Error
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.4
Standard Serial I/O Mode
In standard serial I/O mode, the user ROM area can be programmed with the MCU mounted on a board by using a serial programmer supporting the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). For additional information about the serial programmer, contact your serial programmer manufacturer. Refer to the user's manual of your serial programmer for details on operating instructions. Table 26.7 lists pin functions for flash memory standard serial I/O mode. Figures 26.14 to 26.16 show pin connections for standard serial I/O mode.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Table 26.7
Pin Name VCC VSS CNVSS RESET XIN XOUT BYTE AVCC, AVSS VREF P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 P5_5 P5_1 to P5_4 P5_6, P5_7 P6_0 to P6_3 P6_4 P6_5
Pin Functions for Flash Memory Standard Serial I/O Mode
Function Power supply input CNVSS Reset input Clock input Clock output BYTE input Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 CE input EPM input Input port P5 Input port P6 BUSY output SCLK input
I/O Type I I I I O I I I I I I I I I I I I O I Supply Voltage
Description Apply the guaranteed erase/program supply voltage to the VCC1 pin. Apply 0 V to the VSS pin Apply an "H" signal to the pin Reset input pin Connect a ceramic resonator or a crystal oscillator between pins XIN and XOUT To use the external clock, input the clock to the XIN pin and leave the XOUT pin open Apply an "H" or "L" signal to the pin Connect AVCC to VCC1 Connect AVSS to VSS Reference voltage input pin for the A/D converter Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" signal to the pin Apply an "L" signal to the pin Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Standard serial I/O mode 1: BUSY signal output pin Standard serial I/O mode 2: Program operation verify monitor Standard serial I/O mode 1: Serial clock input pin. This pin needs to be pulled up. Standard serial I/O mode 2: Apply an "L" signal to the pin Serial data input pin Serial data output pin. This pin needs to be pulled up when used in standard serial I/O mode1. Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" signal Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1) Apply an "H" or "L" signal to the pin, or leave it open(1)
-
VCC1 VCC1 VCC1 VCC1 VCC1
- -
VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC2 VCC1 VCC1 VCC1
P6_6 P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6, P8_7 P8_5 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 to P14_7 P15_0 to P15_7
Data input RXD Data output TXD Input port P7 Input port P8 NMI input Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Input port P14 Input port P15
I O I I I I I I I I I I
VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC2 VCC2 VCC1 VCC1
I: Input O: Output I/O: Input and output NOTE: 1. These pins are provided in the 144-pin package only.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Mode setting Signal CNVSS EPM RESET CE Value VCC1 VSS VSS VCC1 VCC2
VCC2
73 72
71 70
69
68 67
66
65 64 63
62 61
60
59
58 57
56 55
54
77 76 75 74
53 52
79 78
80
51
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
1 2 3
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 100-pin package Flash Memory Version (PLQP0100JB-A (100P6S-A))
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
28 29 30
CE
EPM
BUSY RXD SCLK TXD
10
11 12
14
15 16
17 18 19
20 21 22
13
23
26 27
24
25
4 5
6
8 9
7
VSS
VCC1
CNVSS
Connect an oscillation circuit
RESET
Figure 26.14
Pin Connections in Standard Serial I/O Mode (1/3)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Mode setting Signal CNVSS EPM RESET CE Value VCC1 VSS VSS VCC1 VCC2 VCC2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
21 22 23 24 10 13 14 15 16 17 18 11 12 20 25 19
51
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
CE
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 100-pin package Flash Memory Version (PLQP0100KB-A (100P6Q-A))
EPM
BUSY RXD
SCLK TXD
1
2
4
7
8
3
5
6
9
VSS
VCC1 CNVSS Connect an oscillation circuit
RESET
Figure 26.15
Pin Connections in Standard Serial I/O Mode (2/3)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
Mode setting Signal CNVSS EPM RESET CE Value VCC1 VSS VSS VCC1 VCC2
VCC2
108
107 106
105 104
103 102
101 100
79 78 75 77 76
94
93 92
99
98
97 96
95
91 90
81
89
88
87 86
85
84 83 82
80
75
74
73
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
1 2 3 4 5 6 7
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) 144-pin package Flash Memory Version (PLQP0144KA-A (144P6Q-A))
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
31 32 33 34 35 36
CE
EPM
SCLK RXD TXD
BUSY
10
20 21 22
24
25
11 12
14
15 16
17 18 19
26 27
28
29 30
13
23
8 9
VSS
VCC Connect an oscillation circuit RESET
CNVSS
Figure 26.16
Pin Connections in Standard Serial I/O Mode (3/3)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.4.1
Pin Handling in Standard Serial I/O Mode
Figure 26.17 shows an example of a pin handling in standard serial I/O mode 1. Figure 26.18 shows an example of a pin handling in standard serial I/O mode 2. Refer to the user's manual of your serial programmer to handle pins controlled by the serial programmer since controlled pins vary depending on the serial programmer.
VCC1
MCU
VCC2
Clock input
VCC1
SCLK
CE(P5_0) EPM(P5_5) VCC1
Data output BUSY output Data input
TXD BUSY RXD
CNVSS VCC1
VCC1
Reset input User reset signal
RESET
NMI
NOTES: 1. Control pins and external circuit vary depending on the programmer. Refer to the user's manual of the programmer for information. 2. In this example, a selector controls the input voltage applied to CNVSS to switch between single-chip mode and standard serial I/O mode. 3. If there is a possibility the user reset signal becomes "L" in standard serial I/O mode 1, break the connection between the user reset signal and the RESET pin by using such as a jumper selector.
Figure 26.17
Pin Handling in Standard Serial I/O Mode 1
MCU
VCC2 SCLK CE(P5_0) Data output TXD EPM(P5_5) VCC1
Monitor output
BUSY CNVSS
Data input
VCC1
RXD
VCC1
Reset input User reset signal
RESET
NMI
NOTE: 1. In this example, a selector controls the input voltage applied to CNVSS to switch between single-chip mode and standard serial I/O mode.
Figure 26.18
Pin Handling in Standard Serial I/O Mode 2
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
26. Flash Memory
26.5
Parallel I/O Mode
In parallel I/O mode, the user ROM area and the boot ROM area can be programmed by using a parallel programmer supporting the M32C/87 Group (M32C/87, M32C/87A, M32C/87B). For additional information about the parallel programmer, contact your parallel programmer manufacturer. Refer to the user's manual of your parallel programmer for details on operating instructions.
26.5.1
Boot ROM Area
The boot ROM area has one 4K-byte block. The rewrite control program for standard serial I/O mode is stored in the boot ROM area in factory default configuration. Do not rewrite the boot ROM area to use the serial programmer. In parallel I/O mode, the boot ROM area is allocated in addresses FFF000h to FFFFFFh. Rewrite only this address block if it is necessary to rewrite the boot ROM area. (Do not access other than addresses FFF000h to FFFFFFh.)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
27. Electrical Characteristics
Table 27.1
Symbol VCC1, VCC2 VCC2 AVCC VI Supply voltage Supply voltage Analog supply voltage Input voltage RESET, CNVSS, BYTE, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1), VREF, XIN P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 VO Output voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P14_0 to 14_6, P15_0 to P15_7(1), XOUT P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P7_0, P7_1 Pd Topr Power consumption Operating ambient temperature during CPU operation during programming or erasing Flash memory -40CTopr85C
Absolute Maximum Ratings
Parameter Condition VCC1 = AVCC - VCC1 = AVCC Value -0.3 to 6.0 -0.3 to VCC1 + 0.1 -0.3 to 6.0 -0.3 to VCC1 + 0.3 Unit V V V V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 -0.3 to VCC1 + 0.3 V
-0.3 to VCC2 + 0.3
-0.3 to 6.0 500 -20 to 85/ -40 to 85(2) 0 to 60 -65 to 150 mW C C C
Tstg
Storage temperature
NOTES: 1. P11 to P15 are provided in the 144-pin package only. 2. Contact a Renesas sales office if temperature range of -40 to 85C is required.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 27.2
27. Electrical Characteristics
Recommended Operating Conditions (1/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter Supply voltage (VCC1 VCC2) Analog supply voltage Supply voltage Analog supply voltage 0.8VCC2 Input high "H" P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, voltage P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7(1), 0.8VCC1 P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P7_0, P7_1 P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode and microprocessor mode) 0.8VCC1 0.5VCC2 P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) 0.8VCC2 Standard Min. 3.0 Typ. 5.0 VCC1 0 0 VCC2 Max. 5.5 Unit V V V V V
Symbol VCC1, VCC2 AVCC VSS AVSS VIH
VCC1
6.0 VCC2 VCC2
VIL
Input low "L" voltage
P2_0 to P2_7,P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(2) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7(1), P9_0 to P9_7, P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(2), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7 (in single-chip mode) P0_0 to P0_7, P1_0 to P1_7 (in memory expansion mode and microprocessor mode)
0
0.2VCC2
V
0
0.2VCC1
0 0
0.2VCC2
0.16VCC2
NOTES: 1. VIH and VIL reference for P8_7 apply when P8_7 is used as a programmable input port. It does not apply when P8_7 is used as XCIN. 2. P11 to P15 are provided in the 144-pin package only.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 27.3
27. Electrical Characteristics
Recommended Operating Conditions (2/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified
Parameter Peak output high "H" current(2) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3) Standard Min. Typ. Max. -10.0 Unit mA
Symbol
IOH(peak)
IOH(avg)
Average output high "H" current(1)
-5.0
mA
IOL(peak)
Peak output low "L" current(2)
10.0
mA
IOL(avg)
Average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, output low "L" P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, current(1) P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(3)
5.0
mA
NOTES: 1. Average output current is the average value within 100 ms. 2. A total IOL(peak) of P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14, and P15 must be 80 mA or less. A total IOL(peak) of P3, P4, P5, P6, P7,P8_0 to P8_4, P12, and P13 must be 80 mA or less. A total IOH(peak) of P0, P1, P2, and P11 must be -40 mA or less. A total IOH(peak) of P8_6 to P8_7, P9, P10, P14, and P15 must be -40 mA or less. A total IOH(peak) of P3, P4, P5, P12, and P13 must be -40 mA or less. A total IOH(peak) of P6, P7, and P8_0 to P8_4 must be -40 mA or less. 3. P11 to P15 are provided in the 144-pin package only.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 27.4
27. Electrical Characteristics
Recommended Operating Conditions (3/3) (VCC1 = VCC2 = 3.0 to 5.5 V, Topr = -20 to 85C unless otherwise specified)
Parameter CPU clock frequency (same frequency as f(BCLK)) Main clock input oscillation frequency Sub clock frequency On-chip oscillator frequency VCO clock frequency (PLL frequency synthesizer) PLL clock frequency Wait time to stabilize PLL frequency synthesizer VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V VCC1 = 5.0V VCC1 = 3.3V 20 10 10 VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V VCC1 = 4.2 to 5.5V VCC1 = 3.0 to 5.5V Standard Min. 0 0 0 0 32.768 1 80 32 24 5 10 Typ. Max. 32 24 32 24 50 Unit MHz MHz MHz MHz kHz MHz MHz MHz MHz ms ms
Symbol f(CPU) f(XIN) f(XCIN) f(Ring) f(VCO) f(PLL) tsu(PLL)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 27.5 Electrical Characteristics (1/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Output high "H" voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) Measurement Condition IOH = -5 mA Standard Min.
VCC2 - 2.0
Symbol VOH
Typ.
Max. VCC2
Unit V
IOH = -5 mA
VCC1 - 2.0
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7 IOH = -200 A VCC2 - 0.3 P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = -200 A VCC1 - 0.3 P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8, ADTRG, CTS0 to CTS6, CLK0 to CLK6, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD6, SCL0 to SCL4, SDA0 to SDA4, INPC1_0 to INPC1_7, ISCLK0 to ISCLK2, ISRXD0 to ISRXD2, IEIN, CAN0IN, CAN1IN, CAN1WU RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -1 mA No load applied No load applied IOL = 5 mA 3.0 2.5 1.6
VCC2
V
VCC1
VCC1
V V V
2.0
V
IOL = 200 A
0.45
V
IOL = 1 mA No load applied No load applied 0.2 0 0
2.0
V V V
1.0
V
0.2
1.8
V
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 523 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 27.6 Electrical Characteristics (2/3) (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 32 MHz unless otherwise specified)
Parameter Input high "H" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Measurement Condition VI = 5 V Standard Min. Typ. Max. 5.0 Unit A
Symbol IIH
IIL
Input low "L" P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode
VI = 0V
-5.0
A
RPULLUP Pull-up resistance
VI = 0V
30
50
167
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
1.5 10 2.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 524 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 27.7 Electrical Characteristics (3/3) (VCC1 = VCC2 = 5.5 V, VSS = 0 V, Topr = 25C)
Measurement Condition(1) Flash memory version f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode While flash memory is operating f(CPU) = 32 kHz In low-power consumption mode While flash memory is stopped(2) Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C Mask ROM version f(CPU) = 32 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C 32 19 12 1 30 50 Standard Min. Typ. Max. 32 19 12 2.6 430 45 Unit mA mA mA mA A
Symbol Parameter ICC Power supply current
30
A
50
A
0.8
5 50 45
A A mA mA mA mA A A
0.8
5 50
A A
NOTES: 1. In single-chip mode, leave the output pins open and connect the input pins to VSS. 2. Value is obtained when setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on RAM.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 525 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 27.8 A/D Conversion Characteristics
(VCC1 = VCC2 = AVCC = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified) Symbol - INL Parameter Resolution Integral nonlinearity error Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 5 V AN_0 to AN_7, AN0_0 to AN0_7, AN2_0 to AN2_7, AN15_0 to AN15_7, ANEX0, ANEX1 External op-amp connection mode DNL - - tCONV tCONV tSAMP VREF VIA Differential nonlinearity error Offset error Gain error VREF = VCC1 time(1)(2) 8 2.06 1.75 0.188 2 0 VCC1 VREF 10-bit conversion Sampling time(1) Standard Min. Typ. Max. 10 3 Unit Bits LSB
7 1 3 3 40
LSB LSB LSB LSB k s s s V V
RLADDER Resistor ladder 8-bit conversion time(1)(2) Reference voltage Analog input voltage
NOTES: 1. The value is obtained when AD frequency is at 16 MHz. Keep AD frequency at 16 MHz or lower. 2. With using the sample and hold function
Table 27.9
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 4.2 to 5.5 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 32MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.5 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measured when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if the VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 526 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 27.10 Flash Memory Electrical Characteristics (VCC1 = 4.5 V to 5.5 V, 3.0 to 3.6 V, Topr = 0 to 60C unless otherwise specified)
Symbol - - - - Parameter Erase and program endurance(1) Word program time (16 bits) (VCC1 = 5.0 V, Topr = 25C) Lock bit program time Block erase time (VCC1 = 5.0 V, Topr = 25C) 4-Kbyte block 8-Kbyte block 32-Kbyte block 64-Kbyte block tps - Wait time to stabilize flash memory circuit Data hold time (Topr = -40 to 85C) 10 Measurement Condition Standard Min. 100 25 25 0.3 0.3 0.5 0.8 300 300 4 4 4 4 15 Typ. Max. Unit times s s s s s s s years
NOTE: 1. If erase and program endurance is n times (n = 100), each block can be erased n times. For example, if a 4Kbyte block A is erased after programming a word data 2,048 times, each to a different address, this counts as one erase and program time. Data can not be programmed to the same address more than once without erasing the block. (rewrite prohibited)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 527 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Table 27.11 Voltage Detection Circuit Electrical Characteristics (VCC1 = VCC2 = 3.0 to 5.5 V, VSS = 0 V, Topr = 25C unless otherwise specified)
Parameter Vdet4 detection voltage Vdet3 detection voltage Hardware reset 2 hold voltage Hardware reset 2 release voltage VCC1 = 3.0 V to 5.5 V Measurement Condition Standard Min. 3.3 Typ. 3.8 3.0 2.0 3.1 Max. 4.4 Unit V V V V
Symbol Vdet4 Vdet3 Vdet3s Vdet3r
NOTES: 1. Vdet4 > Vdet3 2. Vdet3r > Vdet3 is not guaranteed.
Table 27.12
Symbol td(P-R) td(S-R) td(E-A)
Power Supply Circuit Timing Characteristics
Parameter Wait time to stabilize internal supply voltage when power-on Wait time to release hardware reset 2 Start-up time for Vdet3 and Vdet4 detection circuit Measurement Condition VCC1 = 3.0 to 5.5 V VCC1 = Vdet3r to 5.5 V VCC1 = 3.0 to 5.5 V 6(1) Standard Min. Typ. Max. 2 20 20 Unit ms ms s
NOTE: 1. When VCC1 = 5 V
td(P-R) Wait time to stabilize internal supply voltage when power-on
Recommended operating voltage VCC1 CPU clock td(P-R)
td(S-R) Wait time to release hardware reset 2
VCC1
Vdet3r td(S-R)
CPU clock
td(E-A) Start-up time for Vdet3 and Vdet4 detection circuit
VC26, VC27 Vdet3 and Vdet4 detection circuit
Stop td(E-A)
Operating
Figure 27.1
Power Supply Timing Diagram
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 528 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.13
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. 31.25 13.75 13.75 5 5 Max. Unit ns ns ns ns ns
Table 27.14
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 40 40 Max. Unit ns ns ns
Table 27.15
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 27.16
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 27.17
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 100 Max. Unit ns ns
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 529 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.18
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 27.19
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. 800 200 200 Max. Unit ns ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 27.20
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 27.21
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 27.22
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 530 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.23
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 27.24
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 6
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 27.25
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 1
Intelligent I/O Communication Function (Groups 0 and 1)
Parameter ISCLKi input cycle time ISCLKi input high ("H") pulse width ISCLKi input low ("L") pulse width ISTXDi output delay time ISTXDi output hold time ISRXDi input setup time ISRXDi input hold time 0 100 100 Standard Min. 600 300 300 100 Max. Unit ns ns ns ns ns ns ns
Table 27.26
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Intelligent I/O Communication Function (Group 2)
Parameter ISCLK2 input cycle time ISCLK2 input high ("H") pulse width ISCLK2 input low ("L") pulse width ISTXD2 output delay time ISTXD2 output hold time ISRXD2 input setup time ISRXD2 input hold time 0 150 100 Standard Min. 600 300 300 180 Max. Unit ns ns ns ns ns ns ns
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 531 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.27
Symbol tw(INH) tw(INL)
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. 250 250 Max. Unit ns ns
i = 0 to 8(1) NOTE: 1. INT6 to INT8 are provided in the 144-pin package only.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 532 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.28
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
Memory Expansion mode and Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 26 26 30 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = tac1(AD-DB) = tac2(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1) - 35 [ns] (if external bus cycle is a + b, n = a + b) - 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 533 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.29
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(3) Address output hold time (WR standard)(3) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR WR output width standard)(3) -5 (note 2) (note 1) (note 2) standard)(3) Chip-select signal output hold time (WR standard)(3) See Figure 27.2 -3 0 (note 1) 18 -5 18 -3 0 (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = th(WR-AD) = th(WR-CS) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 15 [ns] - 10 [ns] - 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) tw(WR) = = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b) - 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 534 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 5V
Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.30
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 standard)(5) Chip-select signal output hold time (WR standard)(5) See Figure 27.2 -3 (note 1) (note 1) 18 -5 18 -5 (note 2) (note 1) 18 -3 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 10 [ns] - 10 [ns] - 10 [ns]
th(WR-AD) = th(RD-CS) =
th(WR-CS) = th(WR-DB) =
- 10 [ns] - 15 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 20 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 535 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
30 pF
Note 1
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
Figure 27.2
P0 to P15 Measurement Circuit
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 536 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1=VCC2=5V
tc
XIN input
tr
tw(H) tc(TA) tw(TAH)
tf
tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse input TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
th(TIN-UP)
tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi ISCLKi TXDi ISTXDi RXDi ISRXDi
tw(INL)
tw(CKL)
th(C-Q)
td(C-Q)
tsu(D-C)
th(C-D)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 27.3
VCC1 = VCC2 = 5 V Timing Diagram (1/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode and Microprocessor Mode
BCLK RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
(Multiplexed bus)
RD
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
tsu(HOLD-BCLK) th(BCLK-HOLD)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions - VCC1 = VCC2 = 4.2 to 5.5 V - Input high and low voltage: VIH = 4.0 V, VIL = 1.0 V - Output high and low voltage: VOH = 2.5 V, VOL = 2.5 V
Figure 27.4
VCC1 = VCC2 = 5 V Timing Diagram (2/4)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 538 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1) th(BCLK-CS) -3ns.min
VCC1=VCC2=5V
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(RD-CS) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-RD)
18ns.max
th(RD-AD) 0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2) th(BCLK-RD) -5ns.min
DBi
Hi-Z
tsu(DB-BCLK) 26ns.min(1)
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
th(RD-DB) 0ns.min
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max th(WR-CS)(3) th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-WR) 18ns.max th(WR-AD)(3) tw(WR)(3) th(BCLK-WR) -5ns.min td(DB-WR)(3) th(WR-DB)(3)
WR,WRL,WRH
DBi NOTES: Measurement Conditions: 3. Varies with operation frequency: - VCC1 = VCC2 = 4.2 to 5.5 V td(DB-WR) = (tcyc x m - 20) ns.min - Input high and low voltage: VIH = 2.5 V, VIL = 0.8 V ( if external bus cycle a + b, m = b) - Output high and low voltage: VOH = 2.0 V, VOL = 0.8 V th(WR-DB) = (tcyc / 2 - 15) ns.min th(WR-AD) = (tcyc / 2 - 10) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min 109 tw(WR) = (tcyc / 2 x n - 15) ns.min tcyc= (if external bus cycle a + b, n = (b x 2) - 1) f(BCLK)
Figure 27.5
VCC1 = VCC2 = 5 V Timing Diagram (3/4)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 539 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=5V
ALE
td(BCLK-CS) 18ns.max
tcyc th(RD-CS)(1)
th(BCLK-CS) -3ns.min
CSi
td(AD-ALE)(1) th(ALE-AD)(1)
tsu(DB-BCLK) 26ns.min
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2) -3ns.min
th(BCLK-CS)
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max th(BCLK-WR) -5ns.min
th(BCLK-AD) -3ns.min
WR,WRL,WRH
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 10) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 15) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) Measurement Conditions: 109 - VCC1 = VCC2 = 4.2 to 5.5 V tcyc= - Input high and low voltage VIH = 2.5 V, VIL = 0.8 V f(BCLK) - Output high and low voltage VOH = 2.0 V, VOL = 0.8 V
Figure 27.6
VCC1 = VCC2 = 5 V Timing Diagram (4/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 27.31 Electrical Characteristics (1/3)
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified) Symbol VOH Output high "H" voltage Parameter P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7(1) P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VOL Output low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "L" voltage P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XOUT XCOUT Drive capability = high Drive capability = low VT+ - VTHysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to INT8, ADTRG, CTS0 to CTS6, CLK0 to CLK6, TA0OUT to TA4OUT, NMI, KI0 to KI3, RXD0 to RXD6, SCL0 to SCL4, SDA0 to SDA4, INPC1_0 to INPC1_7, ISCLK0 to ISCLK2, ISRXD0 to ISRXD2, IEIN, CAN0IN, CAN1IN, CAN1WU RESET NOTE: 1. P11 to P15 are provided in the 144-pin package only. IOH = -0.1 mA No load applied No load applied IOL = 1 mA Measurement Condition IOH = -1 mA Standard Min.
VCC2 - 0.6
Typ.
Max. VCC2
Unit V
VCC1 - 0.6
VCC1
2.7 2.5 1.6
VCC1
V V V
0.5
V
IOL = 0.1 mA No load applied No load applied 0.2 0 0
0.5
V V V
1.0
V
0.2
1.8
V
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 541 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 27.32 Electrical Characteristics (2/3) (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C, f(CPU) = 24 MHz unless otherwise specified)
Parameter Input high P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, "H" current P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE Input low "L" current P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1), XIN, RESET, CNVSS, BYTE P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7,P10_0 to P10_7, P11_0 to P11_4, P12_0 to P12_7, P13_0 to P13_7, P14_0 to P14_6, P15_0 to P15_7(1) XIN XCIN In stop mode 2.0 Measurement Condition VI = 3 V Standard Min. Typ. Max. 4.0 Unit A
Symbol IIH
IIL
VI = 0V
-4.0
A
RPULLUP Pull-up resistance
VI=0V
40
90
500
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM data retention voltage
3.0 20.0
M M V
NOTE: 1. P11 to P15 are provided in the 144-pin package only.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 542 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 27.33 Electrical Characteristics (3/3) (VCC1 = VCC2 = 3.3 V, VSS = 0 V, Topr = 25C)
Measurement Condition(1) Flash memory version f(CPU) = 24 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode While flash memory is operating f(CPU) = 32 kHz In low-power consumption mode While flash memory is stopped(2) Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C Mask ROM version f(CPU) = 24 MHz f(CPU) = 16 MHz f(CPU) = 8 MHz f(CPU) = f(Ring) In on-chip oscillator low-power consumption mode f(CPU) = 32 kHz In low-power consumption mode Wait mode: f(CPU) = f(Ring) After entering wait mode from on-chip oscillator low-power consumption mode Stop mode (while clock is stopped) Stop mode (while clock is stopped) Topr = 85C 23 17 11 1 30 45 Standard Min. Typ. Max. 23 17 11 2.6 430 33 Unit mA mA mA mA A
Symbol Parameter ICC Power supply current
30
A
45
A
0.8
5 50 33
A A mA mA mA mA A A
0.8
5 50
A A
NOTES: 1. In single-chip mode, leave the output pins open and connect the input pins to VSS. 2. Value is obtained when setting the FMSTP bit in the FMR0 register to 1 (flash memory stopped) and running the program on RAM.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 543 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Table 27.34 A/D Conversion Characteristics (VCC1 = VCC2 = AVCC = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Integral nonlinearity error (8-bit) Differential nonlinearity error (8-bit) Offset error (8-bit) Gain error (8-bit) VREF = VCC1 time(1)(2) 8 4.9 3 0 VCC1 VREF 8-bit conversion Measurement Condition VREF = VCC1 VREF = VCC1 = VCC2 = 3.3 V Standard Min. Typ. Max. 10 2 1 2 2 40 Unit Bits LSB LSB LSB LSB k s V V
Symbol - INL DNL - - tCONV VREF VIA
RLADDER Resistor ladder Reference voltage Analog input voltage
NOTES: 1. The value when AD frequency is at 10 MHz. Keep AD frequency at 10 MHz or lower. If f(CPU) (=fAD) is 24 MHz, divide f(CPU) by 3 to make it 8 MHz. The conversion time in this case is 6.1 s. 2. Sample and hold function is not available.
Table 27.35
D/A Conversion Characteristics (VCC1 = VCC2 = VREF = 3.0 to 3.6 V, VSS = AVSS = 0 V, Topr = -20 to 85C, f(CPU) = 24MHz unless otherwise specified)
Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current (note 1) 4 10 Measurement Condition Standard Min. Typ. Max. 8 1.0 3 20 1.0 Unit Bits % s k mA
Symbol - - tsu RO IVREF
NOTE: 1. Measurement when one D/A converter is used, and the DAi register (i = 0, 1) of the unused D/A converter is set to 00h. The current flown into the resistor ladder in the A/D converter is excluded. IVREF flows even if VCUT bit in the AD0CON1 register is set to 0 (VREF not connected)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 544 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.36
Symbol tc tw(H) tw(L) tr tf
External Clock Input
Parameter External clock input cycle time External clock input high ("H") pulse width External clock input low ("L") pulse width External clock rise time External clock fall time Standard Min. 41 18 18 5 5 Max. Unit ns ns ns ns ns
Table 27.37
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Count Source Input in Event Counter Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 40 40 Max. Unit ns ns ns
Table 27.38
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (Gate Signal Input in Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 27.39
Symbol tc(TA) tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in One-Shot Timer Mode)
Parameter TAiIN input cycle time TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 200 100 100 Max. Unit ns ns ns
Table 27.40
Symbol tw(TAH) tw(TAL) i = 0 to 4
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Parameter TAiIN input high ("H") pulse width TAiIN input low ("L") pulse width Standard Min. 100 100 Max. Unit ns ns
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 545 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.41
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) i = 0 to 4 TAiOUT input cycle time TAiOUT input high ("H") pulse width TAiOUT input low ("L") pulse width TAiOUT input setup time TAiOUT input hold time
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Parameter Standard Min. 2000 1000 1000 400 400 Max. Unit ns ns ns ns ns
Table 27.42
Symbol tc(TA)
Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Parameter TAiIN input cycle time Standard Min. 2 500 500 Max. Unit s ns ns
tsu(TAIN-TAOUT) TAiOUT input setup time tsu(TAOUT-TAIN) TAiIN input setup time
i = 0 to 4
Table 27.43
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Count Source Input in Event Counter Mode)
Parameter TBiIN input cycle time (counted on one edge) TBiIN input high ("H") pulse width (counted on one edge) TBiIN input low ("L") pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input high ("H") pulse width (counted on both edges) TBiIN input low ("L") pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 27.44
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Period Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
Table 27.45
Symbol tc(TB) tw(TBH) tw(TBL) i = 0 to 5
Timer B Input (Pulse Width Measurement Mode)
Parameter TBiIN input cycle time TBiIN input high ("H") pulse width TBiIN input low ("L") pulse width Standard Min. 400 200 200 Max. Unit ns ns ns
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 546 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.46
Symbol tc(AD) tw(ADL)
A/D Trigger Input
Parameter ADTRG input cycle time (required for trigger) ADTRG input low ("L") pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 27.47
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0 to 6
Serial Interface
Parameter CLKi input cycle time CLKi input high ("H") pulse width CLKi input low ("L") pulse width TXDi output delay time TXDi output hold time RXDi input setup time RXDi input hold time 0 70 90 Standard Min. 200 100 100 80 Max. Unit ns ns ns ns ns ns ns
Table 27.48
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) i = 0, 1
Intelligent I/O Communication Function (Groups 0 and 1)
Parameter ISCLKi input cycle time ISCLKi input high ("H") pulse width ISCLKi input low ("L") pulse width ISTXDi output delay time ISTXDi output hold time ISRXDi input setup time ISRXDi input hold time 0 100 100 Standard Min. 600 300 300 100 Max. Unit ns ns ns ns ns ns ns
Table 27.49
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D)
Intelligent I/O Communication Function (Group 2)
Parameter ISCLK2 input cycle time ISCLK2 input high ("H") pulse width ISCLK2 input low ("L") pulse width ISTXD2 output delay time ISTXD2 output hold time ISRXD2 input setup time ISRXD2 input hold time 0 150 100 Standard Min. 600 300 300 180 Max. Unit ns ns ns ns ns ns ns
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 547 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.50
Symbol tw(INH) tw(INL)
External Interrupt INTi Input (Edge Sensitive)
Parameter INTi input high ("H") pulse width INTi input low ("L") pulse width Standard Min. 250 250 Max. Unit ns ns
i = 0 to 8(1) NOTE: 1. INT6 to INT8 are provided in the 144-pin package only.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 548 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Timing Requirements (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.51
Symbol
tac1(RD-DB) tac1(AD-DB) tac2(RD-DB) tac2(AD-DB) tsu(DB-BCLK) tsu(RDY-BCLK) th(RD-DB) th(BCLK-RDY) th(BCLK-HOLD) td(BCLK-HLDA)
Memory Expansion Mode and Microprocessor Mode
Parameter Data input access time (RD standard) Data input access time (AD standard, CS standard) Data input access time (RD standard, when accessing a space with the multiplexed bus) Data input access time (AD standard, when accessing a space with the multiplexed bus) Data input setup time RDY input setup time Data input hold time RDY input hold time HOLD input hold time HLDA output delay time 30 40 60 0 0 0 25 Standard Min. Max. (note 1) (note 1) (note 1) (note 1) Unit ns ns ns ns ns ns ns ns ns ns ns
tsu(HOLD-BCLK) HOLD input setup time
NOTE: 1. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations. Insert wait states or lower the operation frequency, f(BCLK), if the calculated value is negative.
tac1(RD-DB) = tac1(AD-DB) = tac2(RD-DB) = 109 x m f(BCLK) x 2 109 x n f(BCLK) 109 x m f(BCLK) x 2 109 x p f(BCLK) x 2 - 35 [ns] (if external bus cycle is a + b, m = (b x 2) + 1) - 35 [ns] (if external bus cycle is a + b, n = a + b) - 35 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
tac2(AD-DB) =
- 35 [ns] (if external bus cycle is a + b, p = {(a + b - 1) x 2} + 1)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 549 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.52
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) tw(WR)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(3) Address output hold time (WR standard)(3) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR WR output width standard)(3) 0 (note 2) (note 1) (note 2) standard)(3) Chip-select signal output hold time (WR standard)(3) See Figure 27.2 -3 0 (note 1) 18 -5 18 -3 0 (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(WR-DB) = th(WR-AD) = th(WR-CS) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 - 20 [ns] - 15 [ns] - 10 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equations.
td(DB-WR) tw(WR) = = 109 x m f(BCLK) 109 x n f(BCLK) x 2 - 20 [ns] (if external bus cycle is a + b, m = b) - 15 [ns] (if external bus cycle is a + b, n = (b x 2) - 1)
3. tc [ns] is added when recovery cycle is inserted.
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 550 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1 = VCC2 = 3.3 V
Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85C unless otherwise specified) Table 27.53
Symbol
td(BCLK-AD) th(BCLK-AD) th(RD-AD) th(WR-AD) td(BCLK-CS) th(BCLK-CS) th(RD-CS) th(WR-CS) td(BCLK-RD) th(BCLK-RD) td(BCLK-WR) th(BCLK-WR) td(DB-WR) th(WR-DB) td(BCLK-ALE) th(BCLK-ALE) td(AD-ALE) th(ALE-AD) tdz(RD-AD)
Memory Expansion Mode and Microprocessor Mode (when accessing external memory space with multiplexed bus)
Parameter Address output delay time Address output hold time (BCLK standard) Address output hold time (RD standard)(5) Address output hold time (WR standard)(5) Chip-select signal output delay time Chip-select signal output hold time (BCLK standard) Chip-select signal output hold time (RD RD signal output delay time RD signal output hold time WR signal output delay time WR signal output hold time Data output delay time (WR standard) Data output hold time (WR standard)(5) ALE signal output delay time (BCLK standard) ALE signal output hold time (BCLK standard) ALE signal output delay time (address standard) ALE signal output hold time (address standard) Address output float start time -2 (note 3) (note 4) 8 standard)(5) Chip-select signal output hold time (WR standard)(5) See Figure 27.2 -3 (note 1) (note 1) 18 -5 18 0 (note 2) (note 1) 18 -3 (note 1) (note 1) 18 Measurement Condition Standard Min. Max. 18 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. Values, which depend on BCLK frequency, can be obtained from the following equations.
th(RD-AD) = 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 f(BCLK) x 2 109 x m f(BCLK) x 2 109 x n f(BCLK) x 2 109 x n f(BCLK) x 2 - 10 [ns] - 15 [ns] - 10 [ns]
th(WR-AD) = th(RD-CS) =
th(WR-CS) = th(WR-DB) =
- 10 [ns] - 20 [ns]
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(DB-WR) = - 25 [ns] (if external bus cycle is a + b, m = (b x 2) - 1)
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
td(AD-ALE) = - 20 [ns] (if external bus cycle is a + b, n = a)
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
th(ALE-AD) = - 20 [ns] (if external bus cycle is a + b, n = a)
5. tc [ns] is added when recovery cycle is inserted.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1=VCC2=3.3V
tc
XIN input
tr
tw(H) tc(TA) tw(TAH)
tf
tw(L)
TAiIN input
tw(TAL) tc(UP) tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input (counter increment/ decrement select input) In event counter mode TAiIN input (count on falling edge) TAiIN input (count on rising edge) In event counter mode with two-phase pulse input TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT) tsu(TAOUT-TAIN)
th(TIN-UP)
tsu(UP-TIN)
tc(TA)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB) tw(TBH)
TBiIN input
tw(TBL) tc(AD) tw(ADL)
ADTRG input
tc(CK) tw(CKH)
CLKi ISCLKi TXDi ISTXDi RXDi ISRXDi
tw(INL)
tw(CKL)
th(C-Q)
td(C-Q)
tsu(D-C)
th(C-D)
INTi input NMI input
2 CPU clock cycles + 300 ns or more ("L" width)
tw(INH)
2 CPU clock cycles + 300 ns or more
Figure 27.7
VCC1 = VCC2 = 3.3 V Timing Diagram (1/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
VCC1=VCC2=3.3V
Memory Expansion Mode and Microprocessor Mode
BCLK RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
(Multiplexed bus)
RD
WR, WRL, WRH
(Multiplexed bus)
RDY Input
tsu(RDY-BCLK) th(BCLK-RDY)
BCLK
tsu(HOLD-BCLK) th(BCLK-HOLD)
HOLD Input
HLDA Output
td(BCLK-HLDA) td(BCLK-HLDA) Hi-Z
P0, P1, P2, P3, P4, P5_0 to P5_2
Measurement Conditions -VCC1 = VCC2 = 3.0 to 3.6 V -Input high and low voltage: VIH = 2.4 V, VIL = 0.6 V -Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V
Figure 27.8
VCC1 = VCC2 = 3.3 V Timing Diagram (2/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space)
Read Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max(1)
VCC1=VCC2=3.3V
th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max(1) th(RD-CS) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-RD)
18ns.max
th(RD-AD) 0ns.min
RD
tac1(RD-DB)(2) tac1(AD-DB)(2) th(BCLK-RD) -5ns.min
DBi
Hi-Z
tsu(DB-BCLK) 30ns.min(1)
NOTES: 1. Values guaranteed only when the MCU is used stand-alone. A maximum of 35 ns is guaranteed for td(BCLK-AD) + tsu(DB-BCLK). 2. Varies with operation frequency: tac1(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) + 1) tac1(AD-DB) = (tcyc x n - 35) ns.max (if external bus cycle a + b, n = a + b)
th(RD-DB) 0ns.min
Write Timing (1 + 1 Bus Cycle)
BCLK
td(BCLK-CS) 18ns.max th(BCLK-CS) -3ns.min
CSi
tcyc td(BCLK-AD) 18ns.max th(WR-CS)(3) th(BCLK-AD) -3ns.min
ADi BHE
td(BCLK-WR) 18ns.max th(WR-AD)(3) tw(WR)(3) th(BCLK-WR) 0ns.min td(DB-WR)(3) th(WR-DB)(3)
WR,WRL,WRH
DBi NOTES: Measurement Conditions: 3. Varies with operation frequency: - VCC1 = VCC2 = 3.0 to 3.6 V td(DB-WR) = (tcyc x m - 20) ns.min - Input high and low voltage: VIH = 1.5 V, VIL = 0.5 V ( if external bus cycle a + b, m = b) - Output high and low voltage: VOH = 1.5 V, VOL = 1.5 V th(WR-DB) = (tcyc / 2 - 20) ns.min th(WR-AD) = (tcyc / 2 - 15) ns.min th(WR-CS) = (tcyc / 2 - 10) ns.min 109 tw(WR) = (tcyc / 2 x n - 15) ns.min tcyc= (if external bus cycle a + b, n = (b x 2) - 1) f(BCLK)
Figure 27.9
VCC1 = VCC2 = 3.3 V Timing Diagram (3/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
27. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus)
Read Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
VCC1=VCC2=3.3V
ALE
td(BCLK-CS) 18ns.max
tcyc th(RD-CS)(1)
th(BCLK-CS) -3ns.min
CSi
td(AD-ALE)(1) th(ALE-AD)(1)
tsu(DB-BCLK) 30ns.min
ADi /DBi
td(BCLK-AD) 18ns.max
Address
tdz(RD-AD) 8ns.max tac2(RD-DB)(1)
Data input
Address
th(RD-DB) 0ns.min th(BCLK-AD) -3ns.min
ADi BHE
tac2(AD-DB)(1) th(RD-AD)(1) td(BCLK-RD) 18ns.max th(BCLK-RD) -5ns.min
RD
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(RD-AD) = (tcyc / 2 - 10) ns.min, th(RD-CS) = (tcyc / 2 - 10) ns.min tac2(RD-DB) = (tcyc / 2 x m - 35) ns.max (if external bus cycle a + b, m = (b x 2) - 1) tac2(AD-DB) = (tcyc / 2 x p - 35) ns.max (if external bus cycle a + b, p = {(a + b - 1) x 2} + 1)
Write Timing (2 + 2 Bus Cycle)
BCLK
td(BCLK-ALE) 18ns.max th(BCLK-ALE) -2ns.min
ALE
td(BCLK-CS) 18ns.max tcyc th(WR-CS)(2) -3ns.min
th(BCLK-CS)
CSi
td(AD-ALE)(2) th(ALE-AD)(2)
ADi /DBi
td(BCLK-AD) 18ns.max
Address
Data output
td(DB-WR)(2) th(WR-DB)(2)
Address
ADi BHE
td(BCLK-WR) 18ns.max th(BCLK-WR) 0ns.min
th(BCLK-AD) -3ns.min
WR,WRL,WRH
th(WR-AD)(2)
NOTES: 1. Varies with operation frequency: td(AD-ALE) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(ALE-AD) = (tcyc / 2 x n - 20) ns.min (if external bus cycle a + b, n = a) th(WR-AD) = (tcyc / 2 - 15) ns.min, th(WR-CS) = (tcyc / 2 - 10) ns.min th(WR-DB) = (tcyc / 2 - 20) ns.min td(DB-WR) = (tcyc / 2 x m - 25) ns.min (if external bus cycle a + b, m = (b x 2) - 1) Measurement Conditions: 109 - VCC1 = VCC2 = 3.0 to 3.6 V tcyc= - Input high and low voltage VIH = 1.5 V, VIL = 0.5 V f(BCLK) - Output high and low voltage VOH = 1.5 V, VOL = 1.5 V
Figure 27.10
VCC1 = VCC2 = 3.3 V Timing Diagram (4/4)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28. Usage Notes
28.1 28.1.1 Power Supply Power-on
At power-on, supply voltage applied to the VCC1 must meet the SVCC standard. (Technical update: TN-M16C-116-0311) Table 28.1 Supply Voltage Power-up Slope
Symbol SVCC
Parameter
Standard Min. Typ. Max.
Unit V/ms
Supply voltage power-up slope (supply voltage range: 0 V to 2.0 V) 0.05
Voltage
SVCC Supply voltage power-up slope (VCC1)
SVCC 2.0 V
0V
Time
Figure 28.1
SVCC Timing
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.1.2
Table 28.2
Symbol f(ripple)
Power Supply Ripple
Power Supply Ripple
Parameter Power supply ripple tolerable frequency (VCC1) Power supply ripple voltage fluctuation range Power supply ripple voltage fluctuation rate (VCC1 = 5 V) (VCC1 = 3.3 V) (VCC1 = 5 V) (VCC1 = 3.3 V) Standard Min. Typ. Max. 10 0.5 0.3 0.3 0.3 Unit kHz V V V/ms V/ms
Stabilize supply voltage to meet the power supply standard listed in Table 28.2.
Vp-p(ripple) VCC(|V/T|)
f(ripple) Power supply ripple tolerable frequency (VCC1) Vp-p(ripple) Power supply ripple voltage fluctuation range
f(ripple)
VCC1
Vp-p(ripple)
Figure 28.2
Power Supply Fluctuation Timing
28.1.3
Noise
Use thick and shortest possible wiring to connect a bypass capacitor (0.1 F or more) between VCC and VSS.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.2 28.2.1
Special Function Registers (SFRs) 100 Pin-Package
Set addresses 03CBh, 03CEh, 03CFh, 03D2h, and 03D3h to FFh after reset when using the 100-pin package. Address 03DCh must be set to 00h after reset.
28.2.2
Register Settings
Table 28.3 lists registers containing write-only bits. Read-modify-write instructions cannot be used to set these registers. If these registers are set using a read-modify-write instruction, undefined values are read from the write-only bits in the register and written back to these bits. Table 28.4 lists read-modify-write instructions. When establishing new values by modifying previous ones, write the previous values into RAM as well as to the register. Change the contents of the RAM and then transfer the new values to the register. Table 28.3
WDTS register G0TB register G0RI register G1TB register G1RI register G2TB register U5BRG register U5TB register U6BRG register U6TB register U1BRG register U1TB register U4BRG register U4TB register TA11 register TA21 register
Registers with Write-Only Bits
Address 000Eh 00EAh 00ECh 012Ah 012Ch 016Dh to 016Ch 01C1h 01C3h to 01C2h 01C9h 01CBh to 01CAh 02E9h 02EBh to 02EAh 02F9h 02FBh to 02FAh 0303h to 0302h 0305h to 0304h Register TA41 register DTT register ICTB2 register U3BRG register U3TB register U2BRG register U2TB register UDF register TA0 register(1) TA1 register(1) TA2 register(1) TA3 register(1) TA4 register(1) U0BRG register U0TB register 030Ch 030Dh 0329h 032Bh to 032Ah 0339h 033Bh to 033Ah 0344h 0347h to 0346h 0349h to 0348h 034Bh to 034Ah 034Dh to 034Ch 034Fh to 034Eh 0369h 036Bh to 036Ah Address 0307h to 0306h
Register
NOTE: 1. In one-shot timer mode and pulse width modulation mode only.
Table 28.4
Function Transfer
Read-Modify-Write Instructions
Mnemonic MOVDir BCLR, BMCnd, BNOT, BSET, BTSTC, BTSTS ROLC, RORC, ROT, SHA, SHANC, SHL, SHLNC ABS, ADC, ADCF, ADD, ADDX, DADC, DADD, DEC, DSBB, DSUB, EXTS, INC, MUL, MULEX, MULU, NEG, SBB, SUB, SUBX AND, NOT, OR, XOR ADJNZ, SBJNZ
Bit manipulation Shift Arithmetic Logical Jump
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.3
Processor Mode
* When a port shares its pin with a bus control pin, such as address bus, data bus, CS, or RD, set its
corresponding Port Pi Register (i = 0 to 15) and Port Pi Direction Register after entering single-chip mode. (Technical update: TN-M16C-49-0004)
* Rewriting bits PM01 and PM00 in the PM0 register places the MCU in the corresponding processor mode
regardless of CNVSS input level. When setting bits PM01 and PM00 to 01b (memory expansion mode) or 11b (microprocessor mode), do not set simultaneously with bits PM07 to PM02. First, set bits PM02, PM05 and PM04, and PM07 in the PM0 register, and also set bits PM11 and PM10, PM15 and PM14 in the PM1 register. Then, set bits PM01 and PM00.
* When the MCU starts up in microprocessor mode, the internal ROM cannot be accessed.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.4 28.4.1
Bus HOLD Input
If the HOLD input is used, set bits PD4_0 to PD4_7 in the PD4 register and bits PD5_0 to PD5_2 in the PD5 register to 0 (input mode) prior to setting bits PM01 and PM00 in the PM0 register to 01b (memory expansion mode) or to 11b (microprocessor mode) to switch from single-chip mode to memory expansion mode or microprocessor mode. (Technical update: TN-M16C-59-0008)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.5 28.5.1
Clock Generation Circuits Main Clock
* When the CPU operating frequency is required 24 MHz or higher, make an oscillator connected to the main
clock circuit (XIN-XOUT), or a clock applied to the XIN pin have 24 MHz or lower frequency, and then multiply the main clock with the PLL frequency synthesizer. By using this procedure, a better EMC (Electromagnetic Compatibility) performance can be achieved than connecting a 24 MHz or higher frequency oscillator or using 24 MHz or higher input clock applied to the XIN pin.
* If the main clock is selected as the CPU clock while an external clock is applied to the XIN pin, do not stop
the external clock. (Technical update: TN-M16C-109-0309)
* When a clock applied to the XIN pin is used for the CPU clock, do not set the CM05 bit in the CM0 register
to 1 (stopped).
28.5.2
Sub Clock To Oscillate Sub Clock
28.5.2.1
To oscillate the sub clock, set the CM07 bit in the CM0 register to 0 (clock other than the sub clock) and the CM03 bit to 1 (XCIN-XOUT drive capability = high). Then, set the CM04 bit in the CM0 register to 1 (XCINXCOUT oscillation function). Once the sub clock becomes stabilized, set the CM03 bit to 0 (XCIN-XOUT drive capability = low). After the above procedure, the sub clock can be used as the CPU clock, or the count source for timer A and timer B. (Technical update: TN-16C-119A/EA)
28.5.2.2
Oscillation Parameter Matching
If an oscillation circuit constant matching for the sub clock oscillation circuit has only been evaluated with the drive capability = high, the constant matching for drive capability = low must also be evaluated. Contact your oscillator manufacturer for details on the oscillation circuit constant matching.
28.5.3
Clock Dividing Ratio
To change bits MCD4 to MCD0, set the PM12 bit in the PM1 register to 0 (no wait state).
28.5.4
Power Consumption Control
Stabilize the main clock, sub clock, or PLL clock prior to switching the clock source for the CPU clock to one of these clocks.
28.5.4.1
Wait Mode
* When entering wait mode with setting the CM02 bit in the CM0 register to 1 (peripheral clocks stop in wait
mode), set bits MCD4 to MCD0 in the MCD register for CPU clock frequency to be 10-MHz or lower after dividing the main clock.
* When entering wait mode, the instructions following the WAIT instruction are stored into the instruction
queue, and the program stops. Insert at least 4 NOP instructions after the WAIT instruction.
* To enter wait mode, execute the WAIT instruction while a high-level ("H") signal is applied to the NMI
pin.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.5.4.2
Stop Mode
* The MCU cannot enter stop mode if a low-level ("L") signal is applied to the NMI pin. Apply an "H" signal
to enter stop mode.
* To exit stop mode by reset, apply an "L" signal to RESET pin until a main clock oscillation stabilizes. * If using the NMI interrupt to exit stop mode, use the following procedure to set the CM10 bit in the CM1
register to 1 (all clocks stopped). (Technical update: TN-16C-127A/EA) (1) Exit stop mode using the NMI interrupt. (2) Generate a dummy interrupt. (3) Set the CM10 bit to 1 (all clocks stopped). e.g., int bset #63 CM1 ; dummy interrupt ; all clocks stopped
/*dummy interrupt routine*/ dummy reit
* When entering stop mode, the instructions following CM10 = 1 instruction are stored into the instruction
queue, and the program stops. When stop mode is exited, the instruction lined in the queue is executed before the exit interrupt routine is handled. Insert a jmp.b instruction as follows after the instruction to set the CM10 bit to 1. (Technical update: TN-16C-124A/EA) fset I bset 0, cm1 jmp.b LABEL_001 LABEL_001: nop nop nop nop mov.b #0, prcr . . . ; I flag is set to 1 ; all clocks stopped (stop mode) ; jmp.b instruction executed (no instruction between jmp.b and LABEL.) ; nop(1) ; nop(2) ; nop(3) ; nop(4) ; protection set
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.5.4.3
Suggestions to Reduce Power Consumption
The followings are suggestions to reduce power consumption when programming or designing systems. Ports: * Through current may flow into floating input pins. Set unassigned pins to input mode and connect them to VSS via a resistor (pull down), or set unassigned pins to output mode and leave them open. A/D converter: * When the A/D conversion is not performed, set the VCUT bit in the AD0CON1 register to 0 (VREF not connected). When the A/D conversion is performed, set the VCUT bit to 1 (VREF connection) and wait 1 s or more to start the A/D conversion. D/A converter: * When the D/A conversion is not performed, set the DAiE bit (i = 0, 1) in the DACON register to 0 (output disabled) and registers DACON1 and DAi to 00h. Peripheral function clock stop: * When entering wait mode from main clock mode, on-chip oscillator mode, or on-chip oscillator low-power consumption mode, power consumption can be reduced by setting the CM02 bit in the CM0 register to 1 to stop peripheral function clock source (fPFC). However, fC32 does not stop by setting the CM02 bit to 1.
* In low-speed mode, do not set the CM02 bit to 1 (peripheral clock stops in wait mode) when entering wait
mode. (Technical update: TN-M16C-69-0104)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.6
Protection
The PRC2 bit in the PRCR register becomes 0 (write disable) by a write to the SFR area after the PRC2 bit is set to 1 (write enable). Set a register protected by the PRC2 bit immediately after the PRC2 bit is set to 1. Do not generate an interrupt or a DMA or DMACII transfer between these two instructions.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.7 28.7.1
Interrupts ISP Setting
After reset, ISP is initialized to 000000h. The program may go out of control if an interrupt is acknowledged before setting a value to ISP. Therefore, ISP must be set before any interrupt request is acknowledged. Setting ISP to an even address allows interrupt sequences to be executed at a higher speed. To use the NMI interrupt, set ISP at the very beginning of the program. The NMI interrupt can be acknowledged after the first instruction has been executed after reset.
28.7.2
NMI Interrupt
* The NMI interrupt cannot be disabled. Connect the NMI pin to VCC1 via a resistor (pull-up) when not in
use.
* The P8_5 bit in the P8 register indicates the voltage level applied to the NMI pin. Read the P8_5 bit only to
determine the pin level after the NMI interrupt occurs.
28.7.3
INT Interrupt
* Edge Sensitive
Each "H" or "L" width of the signal applied to pins INT0 to INT8 must be 250 ns or more regardless of the CPU clock frequency.
* Level Sensitive
Each "H" or "L" width of the signal applied to pins INT0 to INT5 must be one CPU clock cycle + 200 ns or more. For example, each "H" or "L" width must be 234 ns or more if the CPU clock is 30 MHz.
* The IR bit in the INTiIC register (i = 0 to 5) may become 1 (interrupt requested) when the polarity settings
of pins INT0 to INT5 are changed. Set the IR bit to 0 (interrupt not requested) after the polarity setting is changed. Figure 28.3 shows a procedure to set the INTi interrupt source (i = 0 to 5).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
< Procedure for Edge Sensitive >
Start INTiIC register: bits ILVL2 to ILVL0 = 000b IFSR register: IFSRi bit INTiIC register: POL bit LVS bit = 0 INTiIC register: IR bit = 0 INTiIC register: bits ILVL2 to ILVL0 End Interrupt disabled Select either one edge or both edges Select polarity (Set to 0 when both edges are selected) Select edge sensitive Clear the interrupt request bit Interrupt enabled
< Procedure for Level Sensitive >
Start INTiIC register: bits ILVL2 to ILVL0 = 000b IFSR register: IFSRi bit = 0 INTiIC register: POL bit LVS bit = 1 INTiIC register: IR bit = 0 INTiIC register: bits ILVL2 to ILVL0 End Interrupt disabled Select one edge Select polarity Select level sensitive Clear the interrupt request bit Interrupt enabled i = 0 to 5
Figure 28.3
Procedure to set the INTi Interrupt Source (i = 0 to 5)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
* The INTiR bit (i = 6 to 8) in the IIOjIR register (j = 9 to 11) may become 1 (interrupt requested) when the
polarity settings of pins INT6 to INT8 are changed. Set the INTiR bit to 0 (interrupt not requested) after the polarity setting is changed. Figure 28.4 shows an example of the switching procedure for an INTi interrupt source. (i = 6 to 8)
Start IIOjIE register: INTiE bit = 0 IFSRA register: IFSRk bit IIOjIR register: INTiR bit = 0 IIOjIE register: INTiE bit = 1 End Interrupt disabled Select polarity for an interrupt Clear the interrupt request bit Interrupt enabled j = 9, k = 10 when i = 6 j = 10, k = 11 when i = 7 j = 11, k = 12 when i = 8
Figure 28.4
Switching Procedure for INTi (i = 6 to 8) Interrupt Source
28.7.4
Changing Interrupt Control Register
To change the Interrupt Control Register while an interrupt request is disabled, use the following instructions. Changing IR bit: The IR bit may not be changed to 0 (interrupt not requested) by writing, depending on which instruction is used. If this causes a problem, use MOV instruction to change the register. (Technical update: TN-M16C-85-0204) Changing any bits other than IR bit: If an interrupt request is generated while writing to the corresponding Interrupt Control Register with instructions such as MOV, the IR bit may not become 1 (interrupt requested) and the interrupt is not acknowledged. If this causes a problem, use the following instructions to write to the register: AND, OR, BCLR, BSET
28.7.5
Changing IIOiIR Register (i = 0 to 11)
* Interrupt request flag
An interrupt request flag becomes 1 (interrupt requested) when an interrupt request is generated. This flag does not automatically become 0 when the interrupt request is acknowledged. Use AND or BCLR instruction to set it to 0 (interrupt not requested) in the interrupt routine. If any of these flags remains 1, the IR bit in the IIOiIC (CANjIC (j = 0 to 5)) register does not become 1 when an interrupt request is generated in the same register. (Interrupt does not occur.) If an interrupt request is generated while writing a 0 to the corresponding interrupt request flag, the flag may not be cleared to 0. In this case, keep writing a 0 until 0 is read.
28.7.6
Changing RLVL Register
The DMAII bit in the RLVL register is undefined after reset. To use interrupt priority level 7 for an interrupt, set it to 0 before setting the Interrupt Control Register.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.8
DMAC
* Set the DMAC-associated registers while bits MDi1 and MDi0 (i = 0 to 3) in the channel i are set to 00b (DMA disabled). Then, set bits MDi1 and MDi0 to 01b (single transfer) or 11b (repeat transfer) at the end of the setup procedure, which enables the DMA request of the channel i to be acknowledged. * Write a 1 (requested) to the DRQ bit when setting the DMiSL register. In the M32C/80 Series, if a DMA request is generated but a receiving channel is not ready(1), a DMA transfer does not occur and the DRQ bit becomes 0. NOTE: 1. Bits MDi1 and MDi0 are set to 00b or the DCTi register is 0000h (transferred 0 time). * To start a DMA transfer using a software trigger, set bits DSR and DRQ in the DMiSL register to 1 simultaneously. e.g., OR.B #0A0h, DMiSL ; set bits DSR and DRQ to 1 simultaneously * While the DCTi register in the channel i is set to 1, do not generate a DMA request in the channel i in the timing that bits MDi1 and MDi0 in the DMDj register (j = 0, 1) corresponding to the channel i are set to 01b (single transfer) or 11b (repeat transfer). (Technical update: TN-M16C-88-0209) * Select a peripheral function used as a DMA request source after setting the DMA-associated registers. When the INT interrupt is selected as a DMA request source, do not set the DCTi register to 1. * Wait six CPU clock cycles or more by a program to enable DMA after setting the DMiSL register(2). NOTE: 2. To enable DMA means changing bits MDi1 and MDi0 in the DMDj register from 00b (DMA disabled) to 01b (single transfer) or 11b (repeat transfer).
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.9 28.9.1
Timers Timer A, Timer B
Timers are stopped after reset. Set the TAiS (i = 0 to 4) or TBjS (j = 0 to 5) bit in the TABSR or TBSR register to 1 (count starts) after setting timer operating mode, count source, and counter value. Change the following registers and bits while the corresponding timer is stopped (the TAiS or TBjS bit is set to 0 (count stops)). * Registers TAiMR and TBjMR * UDF register * Bits TAZIE, TA0TGL, and TA0TGH in the ONSF register * TRGSR register
28.9.2
Timer A Timer A (Timer Mode)
28.9.2.1
* The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
* The TAi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. When the TAi register is set while a counter is stopped, the setting value can be read until a counter is started.
28.9.2.2
Timer A (Event Counter Mode)
* The TAiS bit (i = 0 to 4) is set to 0 (count stops) after reset. Set the TAiS bit to 1 (count starts) after
selecting timer operating mode and setting the TAi register.
* The TAi register indicates a counter value while counting at any given time. In the reload timing, however,
FFFFh can be read if the timer underflows, or 0000h if the timer overflows. When the TAi register is set while the counter is stopped, the setting value can be read until a counter is started.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.9.2.3
Timer A (One-Shot Timer Mode)
* The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
* The following occurs when the TAiS bit in the TABSR register is set to 0 (count stops) while counting. * The counter stops counting and the contents of the reload register is reloaded. * The TAiOUT pin outputs a low-level ("L") signal. * The IR bit in the TAiIC register becomes 1 (interrupt requested) after one CPU clock cycle. * One-shot timer is operated by an internal count source. When an external trigger is selected, a maximum of
one count source clock delay occurs between the trigger input to the TAiIN pin and the one-shot timer output.
* The IR bit becomes 1 when one of the following procedures are used to set timer operating mode. * When selecting one-shot timer mode after reset. * When switching from timer mode to one-shot timer mode. * When switching from event counter mode to one-shot timer mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after one of the above setting has done.
* When a retrigger occurs while counting, the contents of the reload register is reloaded after the counter
decrements by one, and continues counting. To generate a retrigger while counting, wait 1 count source clock cycle or more after the last trigger generation.
* When an external trigger input is used to start counting in timer A one-shot timer mode, do not provide an
external retrigger input for 300 ns before a timer A counter value reaches 0000h. The external retrigger may be ignored. (Technical update: TN-16C-125A/EA)
28.9.2.4
Timer A (Pulse Width Modulation Mode)
* The TAiS bit (i = 0 to 4) in the TABSR register is set to 0 (count stops) after reset. Set the TAiS bit to 1
(count starts) after selecting timer operating mode and setting the TAi register.
* The IR bit becomes 1 when one of the following procedures are used to set timer operating mode. * When selecting PWM mode after reset. * When switching from timer mode to PWM mode. * When switching from event counter mode to PWM mode.
To use the timer Ai interrupt (IR bit), set the IR bit to 0 after one of the above setting has done.
* The following occurs when the TAiS bit is set to 0 (count stops) while PWM pulse is output. * The counter stops. * If the TAiOUT pin outputs a high-level ("H") signal, the signal changes to "L" and the IR bit
becomes 1. * If the TAiOUT pin outputs an "L" signal, its output signal and the IR bit remains unchanged.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.9.3
Timer B Timer B (Timer Mode, Event Counter Mode)
28.9.3.1
* The TBiS bit (i = 0 to 5) in the TABSR or TBSR register is set to 0 (count stops) after reset. Set the TBiS
bit to 1 (count starts) after selecting timer operating mode and setting the TBi register. Bits TB2S to TB0S are bits 7 to 5 in the TABSR register. Bits TB5S to TB3S are bits 7 to 5 in the TBSR register.
* The TBi register indicates a counter value while counting at any given time. However, FFFFh can be read
in the reload timing. When the TBi register is set while a counter is stopped, the setting value can be read until a counter is started.
28.9.3.2
Timer B (Pulse Period/Pulse Width Measurement Mode)
* To set the MR3 bit to 0 (no overflow has occurred), wait for one or more count source cycles to write to the
TBiMR register after the MR3 bit becomes 1, while the TBiS bit is set to 1. (Technical update: TN-M16C-75-0110)
* Use the IR bit in the TBiIC register to detect overflow. The MR3 bit is used only to determine an interrupt
request source within the interrupt routine.
* When the first valid edge is input after the count starts, an undefined value is transferred to the reload
register. At this time, the timer Bi interrupt request is not generated.
* The counter value is undefined when the count starts. Therefore, the MR3 bit may become 1 (overflow) and
causes a timer Bi interrupt request to be generated before a valid edge is input.
* The IR bit may become 1 (interrupt requested) by changing bits MR1 and MR0 in the TBiMR register after
the count starts. If the same value is written to bits MR1 and MR0, the IR bit is not changed.
* Pulse width is repeatedly measured in pulse width measurement mode. Determine by a program whether
the measurement result is high ("H") or low ("L").
* If an overflow and a valid edge input occur simultaneously in pulse period measurement mode, an interrupt
request is generated only once, which results in the valid edge not being recognized. Do not let an overflow occur.
* In pulse width measurement mode, determine whether an interrupt source is a valid edge input or an
overflow by reading the port level in the TBi interrupt routine.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.10 Three-Phase Motor Control Timer Function
* Do not write to the TAi or the TAi1 register (i = 1, 2, 4) in the timing that timer B2 underflows. If there is a
possibility to write in this timing, read the value of the timer B2 register to verify that there is a sufficient time until timer B2 underflows, and then write to the TAi or the TAi1 register immediately. (Technical update: TN-M16C-86-0205)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.11 Serial Interfaces 28.11.1 Changing UiBRG Register (i = 0 to 6)
Set the UiBRG register after setting bits CLK1 and CLK0 in the UiC0 register. When bits CLK1 and CLK0 are changed, set the UiBRG register again.
28.11.2 Clock Synchronous Mode 28.11.2.1 Selecting External Clock
If an external clock is selected, meet the following conditions while the external clock is held "H" when the CKPOL bit in the UiC0 register (i = 0 to 6) is set to 0 (transmit data output at the falling edge and receive data input at the rising edge of the serial clock), or while the external clock is held "L" when the CKPOL bit is set to 1 (transmit data output at the rising edge and receive data input at the falling edge of the serial clock) * Set the TE bit in the UiC1 register to 1 (transmit operation enabled). * Set the RE bit in the UiC1 register to 1 (receive operation enabled). * The TI bit in the UiC1 register is 0 (data in the UiTB register). The RE bit setting is not required for a transmit-only operation.
28.11.2.2 Receive Operation
* In clock synchronous mode, the serial clock is controlled by the transmit control circuit. Set the UARTiassociated registers for a transmit operation as well, even if the MCU is used only for receive operation. Dummy data is output from the TXDi pin while receiving if the TXDi pin is set to output mode.
* If data is received continuously, an overrun error occurs when the RI bit in the UiC1 register is 1 (data in the
UiRB register) and the seventh bit of the next data is received in the UARTi receive shift register. And the OER bit in the UiRB register becomes 1 (overrun error). In this case, a read from the UiRB register returns undefined values. If an overrun error occurs, the IR bit in the SmRIC register (m = 0 to 4), the U5RR in the IIO0IR register, or U6RR bit in the IIO9IR register is not changed to 1.
* The following two conditions must be satisfied to use continuous receive mode (UiRRM bit is set to 1).
(1) The CKDIR bit in the UiMR register is set to 1 (external clock). (2) The RTS function is not used. To receive data continuously under the other conditions, set the UiRRM bit to 0 (continuous receive mode disabled), and write dummy data to the UiTB register every time a receive operation is completed.
28.11.3 UART Mode
Set the UmERE bit in the UmC1 register after setting the UmMR register.
28.11.4 Special Mode 1 (I2C Mode)
To generate the start condition, stop condition, or restart condition, set the STSPSEL bit in the UmSMR4 register to 0. Then, wait for a half clock cycle of the serial clock or more to change individual condition generation bit (the STAREQ bit, STPREQ bit, or RSTAREQ bit) from 0 to 1. (Technical update: TN-16C-130A/EA)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.12 A/D Converter
* Set the ADST bit to 1 (A/D conversion starts) after setting registers AD0CON0 (ADST bit excluded),
AD0CON1, AD0CON2, AD0CON3, and AD0CON4.
* When the VCUT bit in the AD0CON1 register is changed from 0 (VREF not connected) to 1 (VREF
connected), wait for 1 s or more to start A/D conversion. Set the VCUT bit to 0 when A/D conversion is not used to reduce current consumption.
*To prevent latch-up and malfunction due to noise and also to minimize a conversion error, insert a capacitor
between the AVSS pin and each of the following pins: the AVCC pin, VREF pin, or analog input pin ANi_j (i = none, 0, 2, 15; j = 0 to 7). Insert a capacitor between the VCC pin and the VSS pin as well. Figure 28.5 shows an example of individual pin handling.
MCU VCC1 C4 VCC1 AVCC VREF C1 VCC2 C5 VCC2 ANi VSS AVSS C3 C2 VCC1
VSS
NOTES: 1. C1 0.47 F, C2 0.47 F, C3 10000 pF, C4 0.1 F, C5 0.1 F (reference values) 2. Use thick and shortest possible wiring to connect capacitors.
Figure 28.5
Individual Pin Handling
* Set the port direction bit in the PDk register (k = 0 to 15), which corresponds to a pin used as an analog input
pin, to 0 (input mode). Also, set the port direction bit in the PDk register corresponding to the ADTRG pin, to 0 (input mode.)
* When the key input interrupt is used, do not select pins P10_4 to P10_7 (AN_4 to AN_7) as analog input pins. * AD frequency must be 16 MHz or lower when VCC1 = 4.2 V to 5.5 V, or 10 MHz or lower when
VCC1 = 3.0 V to 5.5 V. When the sample and hold is not activated, AD frequency must be 250 kHz or higher. When the sample and hold is activated, AD frequency must be 1 MHz or higher.
* When A/D operating mode is changed, set bits CH2 to CH0 in the AD0CON0 register or bits SCAN1 and
SCAN0 in the AD0CON1 register again to select analog input pins.
* The voltage applied to AN_0 to AN_7, AN15_0 to AN15_7, ANEX0, and ANEX1 must be VCC1 or below.
The voltage applied to AN0_0 to AN0_7, and AN2_0 to AN2_7 must be VCC2 or below.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
* If an A/D conversion in progress is forcibly aborted by setting the ADST bit in the AD0CON0 register to 0
(A/D conversion stops), the A/D conversion result will be incorrect. The AD0i register which is not performing A/D conversion may also be incorrect. If the ADST bit is set to 0 during A/D conversion, do not use values obtained from any of AD0i registers.
* External triggers cannot be used in DMAC operating mode. Do not read the AD00 register using instructions. * To abort an A/D conversion in progress by setting the ADST bit in the AD0CON0 register to 0 in single sweep
mode, disable interrupts before setting the ADST bit to 0. (Technical update: TN-16C-132A/EA)
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.13 Intelligent I/O 28.13.1 Register Setting
* Each value written to the following registers is reflected in synchronization with the count source (fBTi)
(i = 1, 2) set using bits BCK1 and BCK0 in the GiBR0 register. Set bits BCK1 and BCK0 before setting these registers. Group 1: G1BT, G1BCR1, G1TMCR0 to G1TMCR7, G1TPR6, G1TPR7, G1TM0 to G1TM7, G1POCR0 to G1POCR7, G1PO0 to G1PO7, G1FS, G1FE Group 2: G2BT, G2BCR1, G2POCR0 to G2POCR7, G2PO0 to G2PO7, G2FS, G2RTP, BTSR
* When interrupts are used in time measurement function and waveform generation function, use the following
procedure. (Refer to a flowchart of register settings for each function.) (1) Configure for time measurement function or waveform generation function (2) Set the IFEj bit (j = 0 to 7) in the GiFE register to 1 (3) Wait 2 fBTi clock cycles or more (4) Set for the intelligent I/O interrupt
* Each value written to the following registers is reflected in synchronization with the serial clock. Wait for one
clock cycle of the serial clock or more after selecting the serial clock, and then set these registers. Group 0 and 1: GmMR (m = 0, 1), GmCR, GmEMR, GmETC, GmERC, GmIRF, GmTB (GmDR), GmCMP0 to GmCMP3, GmMSK0 to GmMSK1, GmTCRC, GmRCRC, GmRB, GmRI, GmTO Group 2: G2TB, G2RB, G2MR, G2CR, IECR, IEAR, IETIF, IERIF
* If the IVL or INV bit in the GiPOCRj register is written while outputting waveform, the value written takes
effect immediately on the output waveform.
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.14 CAN
Use the following procedures to abort a remote frame transmit operation or to cancel a remote frame receive operation. (Technical update: TN-16C-126A/EA)
Start of transmit operation abort procedure
CiMCTLj register = 00h (note 2)
Read the CiMCTLj register (note 1) NO
CiMCTLj register: REMACTIVE bit = 0 ? YES End of transmit operation abort procedure
i = 0, 1, j = 0 to 15 NOTES: 1. The CiMCTLj register can be accessed when the BANKSEL bit the CiCTLR1 register is set to 0 (registers CiMCTLj, CiSSCTLR, and CiSSSTR are selected). 2. There is an infinite loop set in the flowchart to simplify the description. Set the time limit to break out of the infinite loop for practical use.
Figure 28.6
Procedure to Abort a Remote Frame Transmit Operation
Start of receive operation cancel procedure
CiMCTLj register = 00h (note 2)
Read the CiMCTLj register (note 1) NO
CiMCTLj register: REMACTIVE bit is 0 ? YES End of receive operation cancel procedure
i = 0, 1, j = 0 to 15 NOTES: 1. The CiMCTLj register can be accessed when the BANKSEL bit the CiCTLR1 register is set to 0 (registers CiMCTLj, CiSSCTLR, and CiSSSTR are selected). 2. There is an infinite loop set in the flowchart to simplify the description. Set the time limit to break out of each infinite loop for practical use.
Figure 28.7
Procedure to Cancel a Remote Frame Receive Operation
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
28. Usage Notes
28.15 Programmable I/O Ports
* Pins P7_2 to P7_5, P8_0, and P8_1 have the forced cutoff function of the three-phase PWM output. When
these ports are set in output mode (port output, timer output, three-phase PWM output, serial interface output, intelligent I/O output, RTP output), they are affected by the three-phase motor control timer function and the NMI pin setting. Table 28.5 shows the INVC0 register setting, NMI pin input level, and output pin states. Table 28.5 INVC0 Register Setting, NMI Pin Level, and Output Pin Status
INV03 Bit - 0 (three-phase motor control timer output disabled) 1 (three-phase motor control timer output enabled)(1) NMI Pin Input Level - Pin States of P7_2 to P7_5, P8_0, P8_1 (when set in output mode) Output functions selected using registers PS1, PSL1, PSC, PS2, and PSL2 High-impedance states
Setting Value of the INVC0 Register INV02 Bit 0 (three-phase motor control timer function not used)
- H
1 (three-phase motor control timer function used)
Output functions selected using registers PS1, PSL1, PSC, PS2, and PSL2
L High-impedance states (forcibly terminated)
-: Not affected by the bit setting nor the pin state NOTE: 1. The INV03 bit becomes 0 after a low-level ("L") signal is applied to the NMI pin.
* The availability of the pull-up resistors is undefined until the internal power voltage stabilizes even if the
RESET pin is held "L".
* The input threshold level varies between the input to the port and input to the peripheral functions. If the port
function and peripheral function share the same pin, the level verified by the peripheral function and the level obtained by reading the Port Pi register (i = 0 to 15) may vary during the process when the voltage applied to the pin changes from "H" to "L" or from "L" to "H". (Technical update: TN-M16C-102-0309)
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28. Usage Notes
28.16 Flash Memory 28.16.1 Operating Speed
Prior to entering CPU rewrite mode (EW0, EW1 mode), set the CPU clock frequency to 10 MHz or lower using bits MCD4 to MCD0 in the MCD register, and also set the PM12 bit in the PM1 register to 1 (1 wait state).
28.16.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the flash memory is accessed by executing these instructions: UND, INTO, JMPS, JSRS, and BRK instructions.
28.16.3 Interrupts (EW0 Mode)
* To use peripheral function interrupts, place interrupt routine programs and the relocatable vector table in the
RAM area.
* When an interrupt request is generated by the NMI, watchdog timer, Vdet4 detection function, or oscillation
stop detection function, registers FMR0 and FMR1 are forcibly initialized and the erase or program operation in progress is aborted. Now that the flash memory can be accessed, the interrupt routine will be executed. * The address match interrupt is not available because the flash memory is accessed to process this interrupt.
28.16.4 Interrupts (EW1 Mode)
* When an interrupt request is generated by the peripheral function or watchdog timer (when the PM22 bit in the
PM2 register is set to 0) during the erase or program operation, the interrupt is acknowledged after the erase or program operation is completed. * When an interrupt request is generated by the NMI, watchdog timer (when the PM22 bit is set to 1), Vdet4 detection function, or oscillation stop detection function, registers FMR0 and FMR1 are forcibly initialized and the erase or program operation in progress is aborted. Now that the flash memory can be accessed, the interrupt routine will be executed.
28.16.5 How to Access
To set the FMR01 or FMR02 bit in the FMR0 register, or the FMR11 bit in the FMR1 register to 1, write a 1 immediately after writing a 0 to the bit. Write to the FMR0 or FMR1 register in 8-bit units. Do not generate an interrupt or a DMA or DMACII transfer between these two settings. Also, set these bits while a high-level ("H") signal is applied to the NMI pin. To change the FMR01 bit from 1 to 0, enter read array mode first, and then write into address 0057h in 16-bit units. Set the eight high-order bits to 00h.
28.16.6 Rewriting User ROM Area (EW0 Mode)
If the supply voltage drops while rewriting the block where a rewrite control program is stored, it may not be possible to rewrite the flash memory again, because the rewrite control program is not rewritten successfully. If this happens, use standard serial I/O mode to rewrite the block.
28.16.7 Rewriting User ROM Area (EW1 Mode)
Do not rewrite a block where the rewrite control program is stored.
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28. Usage Notes
28.16.8 Boot Mode
When starting up in boot mode, input pins may not be placed in high-impedance states until the internal supply voltage stabilizes. Use the following procedure to power up in boot mode. (1) Input an "L" signal to the RESET pin and CNVSS pin (2) Wait for td(P-R) (internal power supply stabilization time) or more after the voltage applied to the VCC1 pin rises above 3.0 V (3) Input an "L" (pull-down) to the P6_5 or an "H" (pull-up) to the P6_7 (4) Input an "L" (pull-down) to the EPM (P5_5) and an "H" (pull-up) to the CE (P5_0) (5) Input an "H" to the CNVSS pin (6) Input an "H" to the RESET pin (out of reset)
28.16.9 Writing Command and Data
Write command codes and data to even addresses in the user ROM area.
28.16.10 Block Erase
If an erase operation in progress is aborted due to such as the NMI interrupt, hardware reset, or supply voltage drop, the lock bit of the block which has been erased may become 0 (locked). To erase the same block again, set the FMR02 bit in the FMR0 register to 1 (lock bit disabled) and then execute the block erase command.
28.16.11 Wait Mode
To enter wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then execute the WAIT instruction.
28.16.12 Stop Mode
To enter stop mode, use the following procedure: * Set the FMR01 bit to 0 (CPU rewrite mode disabled) before setting the CM10 bit to 1 (stop mode). * Execute the JMP.B instruction right after the instruction to set the CM10 bit to 1 (stop mode). e.g., BSET 0, CM1 ; Stop mode JMP.B L1 L1: Program after exiting stop mode
28.16.13 Low-Power Consumption Mode and On-Chip Oscillator Low-Power Consumption Mode
When the CM05 bit in the CM0 register is set to 1 (main clock stopped), do not execute the following commands: * Program command * Block erase command * Lock bit program command * Read lock bit status command
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28. Usage Notes
28.17 Difference Between Flash Memory Version and Mask ROM Version
Due to differences in internal ROM type and the layout pattern, flash memory version and mask ROM version may vary in characteristic values, performance margin, noise endurance, noise radiation, and so on, within a range provided in the chapter, Electrical Characteristics. When switching to mask ROM version, perform system evaluation tests equal to those held on the flash memory version.
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Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g
HD *1 108 D 73 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. bp b1
109
72
c1 HE E
c
Reference Symbol
*2
Dimension in Millimeters
Terminal cross section
1 ZD
A2
A
36 Index mark F
ZE
144
37
L L1
D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1
*3 e y
bp
x
Detail F
Min Nom Max 19.9 20.0 20.1 19.9 20.0 20.1 1.4 21.8 22.0 22.2 21.8 22.0 22.2 1.7 0.05 0.1 0.15 0.17 0.22 0.27 0.20 0.09 0.145 0.20 0.125 8 0 0.5 0.08 0.10 1.25 1.25 0.35 0.5 0.65 1.0
JEITA Package Code P-LQFP100-14x14-0.50
RENESAS Code PLQP0100KB-A
Previous Code 100P6Q-A / FP-100U / FP-100UV
MASS[Typ.] 0.6g
HD *1 D
75
51 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
76
50
A1
bp b1
HE
E
c
Reference Dimension in Millimeters Symbol
*2
c1
c
Terminal cross section
1 Index mark ZD
25 F
ZE
100
26
A2
A
D E A2 HD HE A A1 bp b1 c c1
c
A1
y e
*3
bp
L L1 Detail F
x
e x y ZD ZE L L1
Min Nom Max 13.9 14.0 14.1 13.9 14.0 14.1 1.4 15.8 16.0 16.2 15.8 16.0 16.2 1.7 0.05 0.1 0.15 0.15 0.20 0.25 0.18 0.09 0.145 0.20 0.125 0 8 0.5 0.08 0.08 1.0 1.0 0.35 0.5 0.65 1.0
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 582 of 587
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Appendix 1. Package Dimensions
JEITA Package Code P-QFP100-14x20-0.65
RENESAS Code PRQP0100JB-A
Previous Code 100P6S-A
MASS[Typ.] 1.6g
HD *1 80
D 51
81
50 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
*2
HE
E
ZE
Reference Dimension in Millimeters Symbol
100
31
1
ZD
Index mark
30 F
c
A2
L e y *3 bp Detail F
D E A2 HD HE A A1 bp c e y ZD ZE L
Min Nom Max 19.8 20.0 20.2 13.8 14.0 14.2 2.8 22.5 22.8 23.1 16.5 16.8 17.1 3.05 0.1 0.2 0 0.25 0.3 0.4 0.13 0.15 0.2 0 10 0.5 0.65 0.8 0.10 0.575 0.825 0.4 0.6 0.8
A
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 583 of 587
A1
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Index
Index
AD00 to AD07 ........................................ 299 AD0CON0 .............................................. 295 AD0CON1 .............................................. 296 AD0CON2 .............................................. 297 AD0CON3 .............................................. 298 AD0CON4 .............................................. 299 AIER ....................................................... 127
[A]
BTSR ..................................................... 335
[B]
C0AFS ................................................... 447 C0BRP ................................................... 416 C0CONR ................................................ 414 C0CTLR0 ............................................... 405 C0CTLR1 ............................................... 408 C0EFR ................................................... 424 C0EIMKR ............................................... 422 C0EISTR ................................................ 423 C0GMR0 ................................................ 432 C0GMR1 ................................................ 433 C0GMR2 ................................................ 434 C0GMR3 ................................................ 435 C0GMR4 ................................................ 436 C0IDR .................................................... 413 C0LMAR0 .............................................. 432 C0LMAR1 .............................................. 433 C0LMAR2 .............................................. 434 C0LMAR3 .............................................. 435 C0LMAR4 .............................................. 436 C0LMBR0 .............................................. 432 C0LMBR1 .............................................. 433 C0LMBR2 .............................................. 434 C0LMBR3 .............................................. 435 C0LMBR4 .............................................. 436 C0MCTL0 to C0MCTL15 ....................... 438 C0MDR .................................................. 426 C0REC ................................................... 418 C0SBS ................................................... 442 C0SIMKR ............................................... 421 C0SISTR ................................................ 419 C0SLOT0_0 ........................................... 443 C0SLOT0_1 ........................................... 443 C0SLOT0_14 ......................................... 446 C0SLOT0_15 ......................................... 446 C0SLOT0_2 ........................................... 444 C0SLOT0_3 ........................................... 444 C0SLOT0_4 ........................................... 445 REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 584 of 587
[C]
C0SLOT0_5 ........................................... 445 C0SLOT0_6 to C0SLOT0_13 ................ 446 C0SLOT1_0 ........................................... 443 C0SLOT1_1 ........................................... 443 C0SLOT1_14 ......................................... 446 C0SLOT1_15 ......................................... 446 C0SLOT1_2 ........................................... 444 C0SLOT1_3 ........................................... 444 C0SLOT1_4 ........................................... 445 C0SLOT1_5 ........................................... 445 C0SLOT1_6 to C0SLOT1_13 ................ 446 C0SLPR ................................................. 409 C0SSCTLR ............................................ 428 C0SSSTR ............................................... 430 C0STR ................................................... 410 C0TEC ................................................... 418 C0TSR ................................................... 417 C1AFS .................................................... 447 C1BRP ................................................... 416 C1CONR ................................................ 414 C1CTLR0 ............................................... 405 C1CTLR1 ............................................... 408 C1EFR ................................................... 424 C1EIMKR ............................................... 422 C1EISTR ................................................ 423 C1GMR0 ................................................ 432 C1GMR1 ................................................ 433 C1GMR2 ................................................ 434 C1GMR3 ................................................ 435 C1GMR4 ................................................ 436 C1IDR .................................................... 413 C1LMAR0 ............................................... 432 C1LMAR1 ............................................... 433 C1LMAR2 ............................................... 434 C1LMAR3 ............................................... 435 C1LMAR4 ............................................... 436 C1LMBR0 ............................................... 432 C1LMBR1 ............................................... 433 C1LMBR2 ............................................... 434 C1LMBR3 ............................................... 435 C1LMBR4 ............................................... 436 C1MCTL0 to C1MCTL15 ....................... 438 C1MDR .................................................. 426 C1REC ................................................... 418 C1SBS ................................................... 442 C1SIMKR ............................................... 421 C1SISTR ................................................ 419 C1SLOT0_0 ........................................... 443 C1SLOT0_1 ........................................... 443 C1SLOT0_14 ......................................... 446 C1SLOT0_15 ......................................... 446 C1SLOT0_2 ........................................... 444
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Index
C1SLOT0_3 ........................................... 444 C1SLOT0_4 ........................................... 445 C1SLOT0_5 ........................................... 445 C1SLOT0_6 to C1SLOT1_13 ................ 446 C1SLOT1_0 ........................................... 443 C1SLOT1_1 ........................................... 443 C1SLOT1_14 ......................................... 446 C1SLOT1_15 ......................................... 446 C1SLOT1_2 ........................................... 444 C1SLOT1_3 ........................................... 444 C1SLOT1_4 ........................................... 445 C1SLOT1_5 ........................................... 445 C1SLOT1_6 to C1SLOT1_13 ................ 446 C1SLPR ................................................. 409 C1SSCTLR ............................................ 428 C1SSSTR .............................................. 430 C1STR ................................................... 410 C1TEC ................................................... 418 C1TSR ................................................... 417 CCS ....................................................... 370 CM0 ................................................. 82, 136 CM1 ......................................................... 83 CM2 ......................................................... 85 CPSRF ..................................................... 88 CRCD ..................................................... 316 CRCIN .................................................... 316
FMR1 ..................................................... 500
D4INT ....................................................... 53 DA0 ........................................................ 314 DA1 ........................................................ 314 DACON .................................................. 314 DACON1 ................................................ 314 DCT0 to DCT3 ....................................... 143 DM0SL to DM3SL .................................. 140 DMA0 to DMA3 ...................................... 142 DMD0 ..................................................... 144 DMD1 ..................................................... 145 DRA0 to DRA3 ....................................... 143 DRC0 to DRC3 ...................................... 143 DS ............................................................ 63 DSA0 to DSA3 ....................................... 142 DTT ........................................................ 204
[D]
EWCR0 to EWCR3 .................................. 69
[E]
FMR0 ..................................................... 498 REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 585 of 587
[F]
G0CMP0 to G0CMP3 ............................. 376 G0CR ..................................................... 372 G0DR ..................................................... 377 G0EMR .................................................. 373 G0ERC ................................................... 374 G0ETC ................................................... 373 G0IRF ..................................................... 375 G0MR ..................................................... 371 G0MSK0 ................................................. 376 G0MSK1 ................................................. 376 G0RB ..................................................... 378 G0RCRC ................................................ 376 G0RI ....................................................... 378 G0TB ...................................................... 377 G0TCRC ................................................ 376 G0TO ..................................................... 378 G1BCR0 ................................................. 324 G1BCR1 ................................................. 325 G1BT ...................................................... 324 G1CMP0 to G1CMP3 ............................. 376 G1CR ..................................................... 372 G1DR ..................................................... 377 G1EMR .................................................. 373 G1ERC ................................................... 374 G1ETC ................................................... 373 G1FE ...................................................... 329 G1FS ...................................................... 329 G1IRF ..................................................... 375 G1MR ..................................................... 371 G1MSK0 ................................................. 376 G1MSK1 ................................................. 376 G1PO0 to G1PO7 .................................. 328 G1POCR0 to G1POCR7 ........................ 327 G1RB ..................................................... 378 G1RCRC ................................................ 376 G1RI ....................................................... 378 G1TB ...................................................... 377 G1TCRC ................................................. 376 G1TM0 to G1TM7 ................................... 327 G1TMCR0 to G1TMCR7 ........................ 326 G1TO ...................................................... 378 G1TPR6 ................................................. 326 G1TPR7 ................................................. 326 G2BCR0 ................................................. 330 G2BCR1 ................................................. 331 G2BT ...................................................... 330 G2CR ..................................................... 395 G2FE ...................................................... 334
[G]
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Index
G2MR ..................................................... 394 G2PO0 to G2PO7 .................................. 333 G2POCR0 to G2POCR7 ........................ 332 G2RB ..................................................... 393 G2RTP ................................................... 334 G2TB ...................................................... 393
ICTB2 ..................................................... 203 IDB0 ....................................................... 205 IDB1 ....................................................... 205 IEAR ....................................................... 396 IECR ...................................................... 396 IERIF ...................................................... 397 IETIF ...................................................... 397 IFSR ............................................... 124, 223 IFSRA .................................................... 125 IIO0IE to IIO11IE .................................... 130 IIO0IR to IIO11IR ................................... 129 Interrupt Control Register (1) ................. 114 Interrupt Control Register (2) ................. 115 INVC0 .................................................... 198 INVC1 .................................................... 199 IPS ......................................................... 485 IPSA ....................................................... 486 IPSB ....................................................... 486 IRCON ................................................... 270
[I]
PS4 ........................................................ 470 PS5 ........................................................ 470 PS6 ........................................................ 471 PS7 ........................................................ 471 PS8 ........................................................ 472 PS9 ........................................................ 472 PSC ........................................................ 477 PSC2 ...................................................... 477 PSC3 ...................................................... 478 PSC6 ...................................................... 478 PSD1 ...................................................... 479 PSD2 ...................................................... 479 PSE1 ...................................................... 480 PSE2 ...................................................... 480 PSL0 ...................................................... 473 PSL1 ...................................................... 473 PSL2 ...................................................... 474 PSL3 ...................................................... 474 PSL5 ...................................................... 475 PSL6 ...................................................... 475 PSL7 ...................................................... 476 PSL9 ...................................................... 476 PUR0 ...................................................... 481 PUR1 ...................................................... 481 PUR2 ...................................................... 482 PUR3 ...................................................... 483 PUR4 ...................................................... 484
MCD ......................................................... 84
[M]
ONSF ..................................................... 171
[O]
RLVL .............................................. 116, 152 RMAD0 to RMAD7 ................................. 127 ROMCP .................................................. 496 RTP0R to RTP3R ................................... 459
[R]
P0 to P15 ............................................... 467 PCR ....................................................... 485 PD0 to PD15 .......................................... 466 PLC0 ........................................................ 86 PLC1 ........................................................ 86 PM0 .......................................................... 60 PM1 .......................................................... 61 PM2 .......................................................... 87 PRCR ..................................................... 105 PS0 ........................................................ 468 PS1 ........................................................ 468 PS2 ........................................................ 469 PS3 ........................................................ 469 REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 586 of 587
[P]
TA0MR to TA4MR .......... 163, 164, 165, 166 TA0 to TA4 .............................................. 167 TA1, TA2, TA4, TA11, TA21, TA41 ......... 205 TA1MR, TA2MR, TA4MR ....................... 201 TABSR ................................... 170, 189, 206 TB0MR to TB5MR .................. 185, 186, 187 TB0 to TB5 ............................................. 188 TB2 ......................................................... 204 TB2MR ................................................... 200 TB2SC .................................................... 203 TBSR ...................................................... 189 TCSPR ............................................. 88, 162 TRGSR ........................................... 169, 202
[T]
M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Index
U0BRG to U4BRG ................................. 222 U0C0 to U4C0 ........................................ 221 U0C1 to U4C1 ........................................ 222 U0MR to U4MR ...................................... 216 U0RB to U4RB ....................................... 224 U0SMR2 to U4SMR2 ............................. 218 U0SMR3 to U4SMR3 ............................. 219 U0SMR4 to U4SMR4 ............................. 220 U0SMR to U4SMR ................................. 217 U0TB to U4TB ........................................ 224 U56CON ................................................ 276 U56IS ..................................................... 273 U5BRG ................................................... 275 U5C0 ...................................................... 275 U5C1 ...................................................... 276 U5MR ..................................................... 274 U5RB ..................................................... 277 U5TB ...................................................... 277 U6BRG ................................................... 275 U6C0 ...................................................... 275 U6C1 ...................................................... 276 U6MR ..................................................... 274 U6RB ..................................................... 277 U6TB ...................................................... 277 UDF ........................................................ 168
[U]
VCR1 ....................................................... 52 VCR2 ....................................................... 52
[V]
WDC ................................................ 54, 137 WDTS .................................................... 137
[W]
X0R to X15R .......................................... 318 XYC ........................................................ 318
[X]
Y0R to Y15R .......................................... 318
[Y]
REJ09B0180-0151 Rev.1.51 Jul 31, 2008 Page 587 of 587
REVISION HISTORY
Rev. 0.20 1.00 Date Dec 16, 2004 Aug 10, 2005
M32C/87 Group Hardware Manual
Description
Page
- - - - -
Summary First Edition issued
M32C/87A and M32C/87B added Package code changed: 144P6Q-A to PLQP0144KA-A, 100P6Q-A to PLQP0100KB-A, 100P6S-A to PRQP0100JB-A Function description for the reserved bits on register diagram modified "Low Voltage Detection Reset" changed to "Brown-out Detection Reset" Overview * Tables 1.1 and 1.2 M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Performance Performance for CAN and Electrical Characteristics modified * Figure 1.1 M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Block Diagram Diagram modified, note 5 added * Table 1.3 M32C/87 Group Product information updated * Figure 1.2 Product Numbering System ROM capacity modified * Figure 1.3 Pin Assignment for 144-Pin Package Note 15 added * Table 1.4 Pin Characteristics Note 1 added * Figure 1.4 Pin Assignment for 100-Pin Package Note 19 added * Figure 1.5 Pin Assignment for 100-Pin Package Note 15 added * Table 1.5 Pin Characteristics Note 1 added * Table 1.6 Pin Description Note 2 added Memory * Figure 3.1 Memory Map Diagram modified, notes 2 and 3 modified, notes 4 and 5 added Special Function Register (SFR) * The PM0 register Note 1 added * The PLC0 register Value after reset modified * The RLVL and IIO0IR to IIO11IR registers Value after reset modified * The G1BCR1 and G1RB registers Value after reset modified * Note "The CAN-associated registers in M32C/87B cannot be used. Only CAN0-associated registers in M32C/87A can be used" added * The IDB1 and IDB0 registers Value after reset modified * Note 1 added * The DM0SL to DM3SL and AD00 registers Value after reset modified * The PSC and PS2 registers Value after reset modified * The PCR register Value after reset modified * The PSD1 register Value after reset modified * The PCR register Value after reset modified Reset * Section "Voltage Detection Circuit" deleted to create the new chapter Voltage Detection Circuit * Section structure and description modified to create the new chapter * Figure 6.1 Voltage detection Circuit Block Diagram modified * Figure 6.2 WDC Register Note 3 added * Figure 6.3 VCR1 Register Note 1 deleted * Figure 6.3 VCR2 Register Note 2 deleted, note 5 added * Table 6.1 Conditions to Generate Low Voltage Detection Interrupt Request The D42 bit setting modified * Table 6.2 Sampling Periods Sampling period modified * 6.2 Cold Start-up/Warm Start-up Determine Function added
2, 3 4 5 6 7 8 11 12 13 17 22
23 26 29 32-37 38 40 41 42 43 44 45 46 51 52 53 55 57
C-1
REVISION HISTORY
Rev. Date
M32C/87 Group Hardware Manual
Description
Page 59 61 65 84 86 88 89 90 91 94 95 97 99 102 103 111 114 116 120 125 126 127 128 132 136 137 147 153 154 155 160 178 187
Summary
Processor Mode * Section structure and description modified * Figure 6.3 Memory Map in Each Processor Mode Note 3 modified Bus * Table 8.3 Processor Mode and Port Function Note 3 modified Clock Generation Circuit * Figure 9.4 MCD Register Note 4 added * Figure 9.6 TCSPR Register Note 2 added * Figure 9.8 PM2 Register The PM24 and PM25 bit functions modified * Figure 9.9 Main Clock Circuit Connection Diagram modified * Figure 9.10 Sub Clock Circuit Connection Diagram modified * Table 9.2 Bit Settings for On-Chip Oscillator Start Condition added * Table 9.4 CPU Clock Source and Bit Settings Table modified, note 1 added * 9.3.4 fCAN added * 9.5.2 Wait Mode Structure and description modified * 9.5.3 Stop Mode Structure and description modified * Figure 9.13 Status Transition in Wait Mode and Stop Mode Diagram modified, note 2 deleted * Figure 9.14 Status Transition Note 5 added Interrupt * Table 11.2 Relocatable Vector Table "Fault error" as interrupt source deleted, note 4 deleted, note 5 added * Figure 11.3 Interrupt Control register (1) Note 3 modified * Figure 11.5 RLVL Register Value after reset modified, note 3 modified, note 4 added * 11.6.6 Saving a Register Description modified * Figure 11.12 Key Input Interrupt Diagram modified * Figure 11.13 AIER Register Value after reset revised * Figure 11.14 Intelligent I/O Interrupt and CAN Interrupt Notes 1 and 2 revised * Description revised, note 1 added Watchdog Timer * Figure 12.2 WDC Register Note 3 added DMAC * Table 13.1 DMAC Specifications DMA Transfer Cycle specification modified, note 2 added * Figure 13.2 DM0SL to DM3SL Registers Value after reset modified DMAC II * Figure 14.1 RLVL Register Value after reset modified, note 3 modified, note 4 added * Figure 14.5 Transfer Cycle Values in the diagram modified Timer * Figure 15.1 Timer A Configuration Diagram modified * Figure 15.2 Timer B Configuration Diagram modified * Figure 15.7 TCSPR Register Note 2 added * Figure 15.21 TB0MR to TB5MR Registers The TCK1 bit function modified Three-Phase Motor Control Timer Functions * Figure 16.4 IDB0 and IDB1 Registers Value after reset modified
C-2
REVISION HISTORY
Rev. Date
M32C/87 Group Hardware Manual
Description
Page 194 195 200 201 202 204 212 213
Summary
Serial I/O * Figure 17.1 UART0 to UART4 Block Diagram Diagram modified * Figure 17.2 UART5 to UART6 Block Diagram Diagram modified * Figure 17.7 U0C0 to U6C0 Registers Note 3 added * Figure 17.8 U0C1 to U4C1 Registers Note 1 added * Figure 17.9 U5C1 to U6C1 Registers Value after reset modified * Figure 17.11 U0SMR2 to U4SMR2 Registers Value after reset modified * Table 17.4 Pin Settings in Clock Synchronous Serial I/O Mode The PSL0 register settings modified * Table 17.7 Pin Settings in Clock Synchronous Serial I/O Mode The PSL3 register settings modified * Table 17.8 Pin Settings The PS6 register settings modified * Table 17.9 Pin Settings The PS6 register settings modified * Table 17.13 Pin Settings in UART Mode The PSL0 register settings modified * Table 17.17 Pin Settings The PS6 register settings modified * Table 17.18 Pin Settings The PS6 register settings modified * Figure 17.20 Transmit Operation Diagram modified * Figure 17.21 Receive Operation Notes 1 and 2 revised * 17.2.1 Bit Rate added * Table 17.23 Pin Settings in I2C Mode The PSL0 register settings modified * Table 17.25 Pin Settings The PSL3 register settings modified * Table 17.29 Pin Settings in Special Mode 2 The PSL0 register settings modified * Table 17.31 Pin Settings The PSL3 register settings modified * 17.4.1 SSi Input Pin Function Description modified * Table 17.32 GCI Mode Specifications Transmit/Receive Start Condition modified * Table 17.34 Pin Settings in GCI Mode The PSL0 register settings deleted * Table 17.36 Pin Settings The PSL3 register settings modified * Table 17.39 Pin Settings in IE Mode The PSL0 register settings deleted * Table 17.41 Pin Settings The PSL3 register settings modified * Description in section 17.6 modified * Table 17.44 Pin Settings in SIM Mode The PSL0 register settings deleted * Figure 17.35 SIM Interface Operation Diagram modified * Figure 17.40 IRCON Register Address revised, the IRTPOL and IRRPOL function revised A/D Converter * Table 18.1 A/D Converter Specifications Notes 2 and 3 modified * Figure 18.2 AD0CON0 Register Notes 3, 5, and 7 modified, note 8 added * Figure 18.3 AD0CON1 Register Note 10 modified, note 11 and 12 added * 18.2.8 Analog Input Pin and External Sensor Equivalent Circuit deleted * 18.2.8 Output Impedance of Sensor Equivalent Circuit under A/D Conversion added D/A Converter * Figure 19.4 D/A Converter Equivalent Circuit Notes 3 and 4 modified
220 221 222 223 231 238 239 242 244 247 248 252 253 257
261 263 264 277
281
C-3
REVISION HISTORY
Rev. Date
M32C/87 Group Hardware Manual
Description
Page 292 293 295 296 301 303 304 314 330 331 332
Summary
Intelligent I/O * Figure 22.5 G1BCR1 Register The RST2 bit function modified, note 2 modified * Figure 22.6 G2BCR1 Register Note 3 deleted * Figure 22.8 G1TPR6 and G1TPR7 Registers Note 1 modified * Figure 22.9 G1POCR0 to G1POCR7 Registers Note 6 and 7 modified * Table 22.2 Base Timer Specifications Base Timer Reset Condition modified, Interrupt Request modified * Figure 22.14 Base Timer Block Diagram Diagram modified * Table 22.3 Base Timer Associated Register Settings Table layout modified * Table 22.8 Waveform Generating Function Associated Register Settings Table layout modified * Figure 22.31 G0RB and G1RB Registers Bit 14 modified as the PER bit * Figure 22.32 G1MR Register Bit 5 and 4 modified as the PRY and PRYE bits * Figure 22.33 G0EMR Register The RXSL and TXSL bit names and functions modified * Figure 22.33 G1EMR Register The RXSL and TXSL bit functions modified * Figure 22.34 G0ETC Register Note 1 modified * Figure 22.34 G1ETC Register Bits 2 to 0 functions modified, note 1 modified * Figure 22.35 G0ERC and G1ERC Registers Note 1 modified * Figure 22.37 G1IRF Register Note 1 modified * Table 22.16 Clock Synchronous Serial I/O Mode Specifications Error Detection specification modified * Table 22.18 Clock Settings in Clock Synchronous Serial I/O Mode Setting value of the G1PO0 register revised * Table 22.20 Pin Settings in Clock Synchronous Serial I/O Mode Register settings modified * Table 22.23 Pin Settings Register settings deleted * Table 22.24 UART Mode Specifications Data Transfer Format, Error Detection and Selectable Function specifications modified, note 2 modified * Table 22.25 Clock Settings in UART Mode "Input form ISCLK1" setting deleted, note 3 modified * Table 22.26 Register Settings in UART Mode The PRY and PRYE bit functions added * Figure 22.41 Transmit Operation Conditions modified * Figure 22.42 Receive Operation Conditions modified * 22.4.3 HDLC Data Processing Mode Description modified * Table 22.29 HDLC Data Processing Mode Specifications Items modified, Interrupt Request specifications modified * Table 22.31 Clock Settings in HDLC Processing Mode Setting value of the G1PO1 register modified * Table 22.32 Register Settings in HDLC Processing Mode The G1PO1 register function modified * Table 22.35 Pin Settings in Variable Clock Synchronous Serial I/O Mode The PD7 register settings modified
333 334 336 339 340 341 343 344
345 346 347 348 355
C-4
REVISION HISTORY
Rev. Date
M32C/87 Group Hardware Manual
Description
Page 360 415
CAN Module * NOTE added
Summary
Real-Time Port * Table 24.2 RTP-Associated Register Settings The RTP32 bit function revised * Table 24.4 Pin Settings The PS1 register settings modified, note 1 revised * Table 24.6 Pin Settings P104 to P107 functions revised Programmable I/O Port * Figure 25.15 PSC Register Note 1 added * Figure 25.15 PSC2 Register Note 1 added * Figure 25.16 PSC3 Register Note 1 added * Figure 25.19 PUR0 and PUR1 Registers Note 1 modified * Figure 25.22 IPSA Register Note 1 added * Table 25.3 Port P6 Peripheral Function Output Control Bit 2 and bit 6 settings in the PS0 register modified * Table 25.4 Port P7 Peripheral Function Output Control Bit 0 setting in the PS1 register revised Flash Memory Version * 26.2.1 ROM Code Protect Function Description modified * Figure 26.2 ROMCP Address Bits 5 and 4 functions modified, notes 2 to 4 modified, note 5 added * Figure 26.5 FMR1 Register Bits 0, 2 and 3 functions modified * 26.3.4.5 How to Access Descriptions modified * Table 26.7 Pin Description P76 and P77 functions modified Electrical Characteristics * Table 27.2 Recommended Operating Conditions f(BCLK) standard added * Table 27.3 Electrical Characteristics RPULLUP standard modified, Icc standard modified * Table 27.10 Memory Expansion Mode and Microprocessor Mode Formula on note 1 modified * Table 27.22 Memory Expansion Mode and Microprocessor Mode Formula on note 1 modified * Table 27.23 Memory Expansion Mode and Microprocessor Mode Formula on note 1 and 4 modified * Figure 27.3 Vcc1=Vcc2=5V Timing Diagram Values in the diagram modified, note 2 modified * Figure 27.4 Vcc1=Vcc2=5V Timing Diagram Values in the diagram modified, note 1 modified * Table 27.24 Electrical Characteristics RPULLUP standard modified, Icc standard modified * Table 27.25 A/D Conversion Characteristics tCONV standard modified * Table 27.28 Memory Expansion Mode and Microprocessor Mode Formula on note 1 modified * Table 27.40 Memory Expansion Mode and Microprocessor Mode Formula on note 1 modified * Table 27.41 Memory Expansion Mode and Microprocessor Mode Formula on note 1 and 4 modified
432 433 436 439 441
448 449 452 457 469 478 479 484 487 488 490 490 494 495 496 499 500
C-5
REVISION HISTORY
Rev. Date
M32C/87 Group Hardware Manual
Description
Page 501 502
Summary
Electrical Characteristics * Figure 27.7 Vcc1=Vcc2=3.3V Timing Diagram Values in the diagram modified, note 2 modified * Figure 27.8 Vcc1=Vcc2=3.3V Timing Diagram Values in the diagram modified, note 1 modified Precautions * Processor Mode Section deleted * 28.1 Reset section added * 28.4 Clock Generation Circuit Section structure and description modified * 28.6.3 INT Interrupt Description modified * 28.8 Timer Section structure and description modified * 28.9.2 UART Mode Description modified * Special Mode 2 Subsection deleted * 28.9.3 Special Mode 1 (I2C Mode) added * Figure 28.4 Use of Capacitors to Reduce Noise Diagram modified All in this manual * Descriptions and formats unified * Notation of numbers changed (e.g. 002 00b, FF16 FFh) * Notation of pin name changed (e.g. RTP00 RTP_0, A15(/D15) [A15/D15]) * Columns in pin settings tables are rearranged by the order of the setting procedure * [Term changed] Serial I/O Serial interface Clock synchronous serial I/O mode Clock synchronous mode Clock asynchronous serial I/O mode Clock asynchronous mode Clock synchronous variable length Variable data length clock synchronous Voltage detection circuit Power supply voltage detection function Low voltage detection interrupt Vdet4 detection interrupt Brown-out detection reset Vdet3 detection function * [NOTE changed] -"Nothing is assigned. If necessary, set to 0. When read, the content is undefined." "Unimplemented. Write 0. Read as undefined value." -"Set the PD9 and PS3 registers immediately after the PRC2 bit in the PRCR register is set to "1" (write enable). Do not generate an interrupt or a DMA transfer between the instruction to set to the PRC2 bit to "1" and the instruction to set the PD9 and PS3 registers." "Set the PD9 or PS3 register immediately after the PRC2 bit in the PRCR register is set to 1 (write enable). Do not generate an interrupt or a DMA or DMACII transfer between these two instructions." RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER RENESAS MCU Keep safety first in your circuit designs! deleted Notes regarding these materials partially modified General Precautions in the Handling of MPU/MCU Products added How to Use This Manual (revised overall) Sections Purpose and Target Readers, Notation of Numbers and Symbols, and List of Abbreviations and Acronyms added
- 505 508 513 516 520 -
521 1.50 Oct 20, 2007 All
Cover
- - -
C-6
REVISION HISTORY
Rev. Date
M32C/87 Group Hardware Manual
Description
Page 1
Summary
Overview * Header SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER RENESAS MCU * 1.1 Features title added, 1.1 Applications changed to 1.1.1 Applications 2 * 1.2 Performance Overview changed to 1.1.2 Specifications * Tables 1.1 to 1.4 Structure, descriptions in Specification field, NOTE, and 2-5 value partially revised or deleted * Real-Time Port Item deleted, ROM Correction Function Item added * 1.3 Block Diagram moved following the 1.2 Product List 8 * 1.2 Product List Tables revised, NOTE 1 added 6-7 9, 14, 15 * Figures 1.3 to 1.5 Arrows for VSS and VCC deleted, NOTES partially modified 11,17 * Tables 1.9 and 1.13 CLKOUT pin moved from Bus Control Pin column to Control Pin column 19-22 * Tables 1.15 to 1.19 Descriptions revised, NOTE 1 added
26 34-39 45 27 34
Memory * Text partially modified SFR * Tables 4.8 to 4.13 NOTE "Set the PM13 bit in the PM1 register to 1 (2 wait states for SFR area) before accessing the CAN-associated registers." added * Table 4.19 The PSL5 register added to the Address field of 03BBh item, the PSL7 register added to the Address field of 03BFh item * [Register names changed] 002Fh Low Voltage Detection Interrupt Register Vdet4 Detection Interrupt Register 01C1h UART5 Bit Rate Register UART5 Baud Rate Register 01C9h UART6 Bit Rate Register UART6 Baud Rate Register 01D0h UART5, UART6 Transmit/Receive Control Register 2 UART5, UART6 Transmit/Receive Control Register 01DBh to 01D8h Pulse Output Data Register RTP Output Buffer Register 0303h to 0302h Timer A1-1 Register Timer A11 Register 0305h to 0304h Timer A2-1 Register Timer A21 Register 0307h to 0306h Timer A4-1 Register Timer A41 Register 0340h Count Start Flag Count Start Register 0341h Clock Prescaler Reset Flag Clock Prescaler Reset Register 0342h One-Shot Start Flag One-Shot Start Register 0344h Up-Down Flag Up/Down Select Register * [Value After Reset changed] 000Fh WDC 000X XXX2 00XX XXXXb 002Fh D4INT 0016 XX00 0000b 007Bh IIO6IC XX00 X0002 XXXX X000b 00EFh G0CR XX00 X0112 0000 X011b 00FEh G0IRF 0016 0000 XXXXb 013Eh G1IRF 0016 0000 XXXXb 01C7h to 01C6h U5RB XXXX XXXX XXXX 0XXX2 XXXXh 01CFh to 01CEh U6RB XXXX XXXX XXXX 0XXX2 XXXXh 038Fh to 0382h AD07 to AD01 XXXX16 00XXh
41 42
27 27 29 31 31 32 34 34 44
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Description
Page 47-50 49 -
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Reset * Text, diagrams partially modified * Table 5.1 Title and structure modified, NOTE 4 added * Figure Brown-Out Detection Reset (Hardware Reset 2) Figure title changed and moved into the chapter 6. Power Supply Voltage Detection Function Power Supply Voltage Detection Function (revised overall) * [Term changed] Reset level Vdet3 Low voltage Vdet4 * Order of register figures rearranged, bit name, description in Function field, and NOTE partially modified * Figure 6.1 Block diagram modified (Block diagrams of voltage detection circuit, low voltage detection interrupt generation circuit, and cold start-up/ warm start-up determine function are integrated) * 6.1 Vdet3 Detection Function and Figure 6.5 added * 6.2 Vdet4 Detection Function added and Table 6.2 32MHz changed to 24MHz in CPU Clock field, NOTE 1 added * Figure 6.6 modified * 6.2.1 Usage Notes on Vdet4 Detection Interrupt Title and text partially modified * 6.3 Cold Start/Warm Start Determine Function Text partially modified and Figure 6.7 partially modified Processor Mode * Boot mode added, 7.2 Setting of Processor Mode Text partially modified, Table 7.2 Structure modified and NOTES deleted * Figures 7.1 and 7.2 NOTE modified * Figure 7.3 Text and NOTE modified BUS * [Term changed] signal either input or output * Text partially modified * Table 8.2 added * Table 8.3 Structure and NOTE partially modified * Figure 8.2 partially modified * Tables 8.4 and 8.5 structure and text partially modified * Figure 8.3 Bit symbol modified and NOTE partially modified * Table 8.6 Text partially modified and NOTE 1 added * Figures 8.4 to 8.11 partially modified * Table 8.7 NOTE 1 deleted, text partially modified * Table 8.8 CPU state and NOTE 1 added
52-54 51 55 56 57 58
59 60-61 62
63-79 64 65 67 68 69 70 71-78 77 78
Clock Generation Circuits * [Term changed] Normal Operating Mode CPU Operating Mode 82-88 * Figures 9.2 to 9.8 Order of figures rearranged * Table 9.1 Text partially modified 80 * Figure 9.1 Revised overall 81 82-88 * Figures 9.2 to 9.8 Bit Name, description in Function field, and NOTES partially modified 89-104 * Text partially modified
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Page 92 93
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Clock Generation Circuits * Figure 9.11 Flow chart partially modified * Table 9.3 Structure partially modified, Figure 9.12 Flow chart partially modified 95 * Table 9.4 Structure partially modified, Table 9.5 Bit setting value partially modified, NOTE 3 deleted 96 * Figure 9.13 added (entering wait mode from Low-power consumption mode disabled) 97 * "High-speed mode" and "Medium-speed mode" are changed to "Main clock mode". 97 * 9.5.1.7 Main Clock Direct Mode added 98 * Table CPU Clock Source and Bit Settings Structure modified became Table 9.6 Operation Mode, NOTES added 99 * 9.5.2.2 Entering Wait Mode Procedure became the flow chart 101 * Table 9.8 CAN interrupts usage conditions revised 101-102 * 9.5.3.1 Entering Stop Mode The program example added, procedures became the flow chart - * Figure Status Transition in Wait Mode and Stop Mode deleted 104 * 9.6 System Clock Protect Function Procedure became the flow chart
105 106-127 109 111 112 116 118 119 120 123-124 126 128
Protection * "desired address" changed to "SFR area"
Interrupt * Text partially modified * Figure 11.2 added * Table 11.2 Vector table address of the reserved space revised * Table 11.3 UART5,6, INT, CAN1 wake-up, and reserved space added * Figure 11.6 NOTE partially changed * Table 11.5 Table changed overall * Table 11.6 DMACII end-of-transfer interrupt added, Reset deleted * Figure 11.9 modified overall * Figures 11.11 and 11.12 added * Figure 11.15 partially modified * 11.11 Intelligent I/O Interrupts, CAN Interrupts, UART5 and UART6 Transmit/Receive Interrupts, and INT6 to INT8 Interrupts Overall structure and text modified, Figure 11.17 partially modified 129-130 * Figure 11.18 IIO0IR to IIO11IR Registers Bit Name added, Figure 11.19 IO0IE to IIO11IE Registers Bit Name changed, NOTE 2 added 131-133 * Table 11.7, Figures 11.20 and 11.21 added Watchdog Timer (revised overall) 134-137 * Overall structure and text revised, and order of register figures rearranged 134 * Table 12.1 and Table 12.2 added * Table 12.2 Values in WDC7 bit in WDC register changed * Figure 12.1 partially modified 135 * Figure 12.2 NOTE partially modified 136 * Section Count Source Protection Mode deleted DMAC * [Term changed] memory (forward direction) incremented address 138-150 * Text partially revised 139 * Table 13.1 Text partially modified, NOTE 1 deleted * Table 13.2 Description added to NOTE 3 141
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DMAC 142-145 * Figures 13.3 to 13.6 Order of register figures rearranged, NOTE partially modified 146-147 * Figures 13.7 and 13.8 Two flow charts added * Figure Transfer Cycle Examples with the Source-Read Bus Cycle deleted 149 * Table 13.3 Title and structure partially modified 150 * Figure 13.9 Title and figure modified DMACII * [Term changed] relocatable address incremented address 151-158 * Text partially modified 151 * Table 14.1 Structure and text partially modified * Figure 14.1 NOTE partially modified 152 157-158 * Figures 14.4 and 14.5 partially modified Timers * [Modification throughout all modes] Specification tables: Structure, text, and NOTES partially modified Operation timing diagrams: added or partially modified Register figures: Register figures of TA0MR to TA4MR in each mode are moved to earlier in the 15.1 Timer A section. * Text partially modified, order of register figures rearranged * Figures 15.4 to 15.13 Register name, bit name, description in Function field, and NOTE partially modified * Tables 15.1 and 15.2 Structure partially modified, NOTE 1 added, NOTE 2 moved from NOTE 1 * 15.1.2 Event Counter Mode Structure and text modified * Figure Counter Reset Timing deleted * Figures 15.19 and 15.20 Titles and figures partially modified * Figure 15.26 Register name and bit name partially modified * Figures 15.29 and 15.30 Titles and figures partially modified
159-195 162-171 172 174-178 182-183 189 194-195
Three-Phase Motor Control Timer Function (fully revised) * [Term changed] Positive and negative phases concurrent active Upper and lower arm simultaneous turn-on 196-213 * Structure, text, tables, and figures modified or added 198-206 * Order of register figures rearranged, Figures 16.2 to 16.10 Register name, bit name, description in Function field, and NOTE partially modified 198 * Bits INV01 and INV00 in Figure 16.2 INVC0 Register Bit name, Function changed * Figure 16.7 Two cases of "when n > 1" and "when n = 1" added under "When bits INV01 and INV00 are set to 11b...". Serial Interfaces (revised overall) * Chapter is divided into two sections 17.1 UART 0 to 4 and 17.2 UART 5,6 * Continuous receive mode is deleted in special mode 2 * IEBus mode is deleted, "special mode 4 (IE mode)" is now "special mode 4 (SIM mode)", "special mode 5 (SIM mode)" is now "special mode 5 (IrDA mode)", and "special mode 6 (IrDA mode)" is now "special mode 6 (IE mode)".
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REVISION HISTORY
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Serial Interfaces * [Term changed] Transmit buffer UiTB register Transmit register transmit shift register Transfer data length data length Bit rate baud rate Transfer clock serial clock, internal transmit clock, internal receive clock Transfer format bit order Actual bit rate, bit rate actual baud rate, target baud rate * [Modification throughout all modes] Specification tables: Structure and text partially modified Block diagrams: Partially modified Pin setting tables: Partially modified and NOTE added Register setting tables: Changed to flow chart Operation timing diagrams: Partially modified * Text modified * Order of register figures rearranged Figures 17.2 to 17.10 Register name, bit name, description in Function field, and NOTE partially modified * CTS/RTS Function, Procedure When the Communication Error is Occurred added * Formulas for baud rate added * Tables 17.10 and 17.11 Structure and text partially modified * Figure 17.38 Bit name and description in Function fields partially modified * Section 17.2 UART5, UART6 added as a section. * Figures 17.41 to 17.45 Register name, bit name, description in Function field, and NOTE partially modified * Figure 17.43 Bit 5 is changed to a reserved bit.
214-292 216-224 233,241 239,291 246-247 270 272-292 273-277 275 293-313 294 295 296-300
A/D Converter * Text partially modified * Table 18.1 Structure, text, and NOTE partially modified * Figure 18.1 Figure partially modified * Figures 18.2 to 18.6 Bit name, description in Function field, and NOTE partially modified * Tables 18.2 and 18.3 added 301 302-309 * Tables 18.4 to 18.10 Structure and text partially modified * Figure 18.7 added 307 * Section 18.3 Read from the AD0i Register (i = 0 to 7) added 312 312-313 * Section 18.4 and Figure 18.9 Values revised
314 316 317
D/A Converter * Text partially modified * Figure 19.1 moved before Table 19.2, NOTE 1 added * Table 19.2 Pin Settings Note 1 added * Figure 19.3 Diagram and NOTE partially modified CRC Calculation * Text partially modified
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REVISION HISTORY
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M32C/87 Group Hardware Manual
Description
Page
Summary
Intelligent I/O * [Term changed] Modulated span Number of modulated pulses Transmit buffer GiTB register Transmit register Transmit shift register Transfer format Bit order Transfer data format, character bit, transfer bit length Data length Bit rate Baud rate Transfer clock Serial clock, baud rate, internal transmit clock, internal receive clock During transmit data processing When HDLC frame data is generated During received data processing When source data is generated * [Modification throughout functions and modes] Specification tables: Structure, text, NOTE, and formula: Partially modified Block diagrams: Partially modified, figures for communication function is moved to communication function section. Pin setting tables: Partially modified, column sequence rearranged Register setting tables: Became flow chart Operation timing diagrams: Partially modified * Text partially modified, order of register figures rearranged * Figures 22.3 to 22.14 Bit name, description in Function field, and NOTE partially modified * 22.2.1 Prescaler function and 22.2.2 Gate function Flow charts for register settings added * Table 22.6 Registers PSL5 and PSL7, and NOTE added * Table 22.11 Structure and title partially modified * Tables 22.12 and 22.13 Inversed output functions deleted from Selectable function fields * 22.3.7 GiPOj Register reload timing select function added * Figures 22.38 to 22.46 Bit name, description in Function field, and NOTE partially modified * Figure 22.41 Bits SMODE and BSINT deleted from the GiEMR register, bits SOF, ASTE, and TBSF0 deleted from the GiETC register * Figure 22.42 RBSF0 bit deleted * Figure 22.43 BSERR bit deleted * Table 22.16 NOTE partially modified, Table 22.17 PSL5 register and NOTE added * Table 22.19 PSL5 register and NOTE added, Table Clock Settings in UART Mode (Group 1) deleted * Figures 22.56 to 22.60 Bit name, description in Function field, and NOTE partially modified * Table 22.27 PSL7 register and NOTE 3 added * Section IEBus Mode deleted CAN Module * Table 23.1 Structure and text partially modified * Table 23.2 NOTE 1 added * Figure 23.3 NOTE partially modified * Figure 23.6 Function description for bits TRMSUCC, RECSUCC and STATE_RESET partially modified * Figure 23.8 NOTE 1 added * Figure 23.9 NOTE 1 added
322-401 325-336 347-349 352 362 363, 365 368 371-379 374 375 376 381 387 394-398 401 - 402 405 406 411 415 417
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Page 418 431 438 439 440 440 443 449
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CAN Module * Figure 23.10 added * Figure 23.22 Descriptions in function fields partially modified * Figures 23.28 and 23.29 partially modified * Figure 23.30 Descriptions in Function fields and NOTE partially modified * Table 23.4 Structure partially modified * 23.1.20.2 TRMACTIVE/INVALDATA Bit Text partially modified * Subsections 23.1.21.1 and 23.1.21.2 Text partially modified * 23.2 CAN Clock and CPU Clock Title and structure partially modified, a table and a figure deleted * 23.3 Setting and Timing in CAN-Associated Registers Title partially 450 modified 451-453 * Figures 23.38 to 23.40 partially modified 454-458 * 23.4 CAN Interrupts Structure partially modified, Figure 23.42 partially modified, Figures 23.41, 23.43, tables 23.5, and 23.6 added Real-Time Port (RTP) 459 * Text partially modified, Specification table deleted 459,460 * Figure 24.1 and 24.3 partially modified * Figure 24.2 Register name and bit name partially revised 460 * Table 24.1 NOTE 1 added, 461 RTP-Associated Register Settings Table deleted Programmable I/O Ports 462-463 * Text partially modified 464-466 * Figures 25.1 to 25.3 partially modified 467,468 * Figure 25.5 and 25.6 Descriptions in Function field and NOTE partially modified 469-481 * Figures 25.7 to 25.19 Bit name and descriptions in Function fields partially modified 476 * Figure 25.14 PSL5 register added * Figure 25.15 PSL7 register added 477 * Figure 25.24 Descriptions in Function fields partially modified 486 * Tables 25.1 and 25.2 AVCC and AVSS deleted, 488 Figure 25.26 Partially modified 489-493 * Tables 25.3 to 25.13 partially modified Flash Memory * Text partially modified * Tables 26.1 and 26.2 Structure, text, and NOTE partially modified * Figure 26.1 Title and NOTE partially modified * Figure 26.2 Bit name, descriptions in Function fields, and NOTE partially modified * Figure 26.3 partially modified 497 * Table 26.3 Structure, title, text, and NOTE partially modified 498 * Figure 26.5 Value after reset revised 501 502-504 * Figures 26.6 to 26.8 Flow chart and NOTE partially modified - * Subsection Precautions in CPU Rewrite Mode moved to 28. Usage Notes 511 * Table 26.5 D0 to D7 are changed to b7 to b0 respectively, Table 26.6 Text partially modified 514 * Table 26.7 Structure and text partially modified - * Subsection ID Code Verify Function deleted
494-519 494 495 497
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Description
Page 518 -
Summary
Flash Memory * Figures 26.17 and 26.18 partially modified * Subsection ROM Code Protect Function deleted Electrical Characteristics * [Term changed] Low Voltage Reset Hardware Reset 2 Low Voltage Detection Vdet3 and Vdet4 detection circuit * Table 27.1 Description in Condition field of Pd (Power consumption) partially modified * Tables 27.4 to 27.9 f(BCLK) is changed to f(CPU) * Table 27.4 Description added in Parameter field of f(CPU), f(VCO) added * Tables 27.5 to 27.7 and Tables 27.31 to 27.33 Description in XCOUT and Hysteresis in Parameter fields partially modified * Table 27.7 and 27.33 Structure and standard values revised, items in Measurement Condition and NOTE added * Table 27.10 Description in Parameter field and NOTE partially modified * Tables 27.11 and 27.12 Description in Parameter field and standard value partially modified * Tables 27.19 and 27.42 added * Table 27.24 Values revised, Table 27.25 and 27.26 added * Table 27.27 Titles modified, NOTE added * Table 27.28 moved to the last table in Timing Requirements * Table 27.29 NOTE 3 added, Table 26.30 NOTE 5 added * Figures 27.3 to 27.6 Order rearranged, measurement condition modified * Table 27.31 to 27.35 f(BCLK) revised to f(CPU) * Table 27.47 Values revised, Table27.48 and 27.49 added * Table 27.50 Titles modified, NOTE added * Table 27.51 Table moved to the last table in Timing Requirements * Table 27.52 NOTE 3 added, Table 27.53 NOTE 5 added * Figures 27.7 to 27.10 Order rearranged Usage Note (chapter title changed) * [New section] 28.1.2 Power Supply Ripple 28.3 Processor Mode 28.10 Three-Phase Motor Control Timer Function 28.14 CAN * Text partially modified * Section Reset changed to 28.1 Power Supply, 28.1.1 Power-on added, Figure 28.1 partially modified * 28.1.3 Noise partially modified and moved earlier in the chapter * Table 28.4 added * Subsection External Bus deleted * 28.5 Clock Generation Circuits Structure modified * Figures 28.3 and 28.4 added * 28.11 Serial Interfaces Structure modified * 28.13 Intelligent I/O Structure modified * 28.16 Flash Memory Structure modified
520 522-527 522 524-526, 542-544 526,544 528 529 531,547 532 533 534 535-536 538-541 542-545 548 549 550 551-552 553-556
558 560 573 578 557-582 557 558 559 562-564 567-568 574 577 580-581
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REVISION HISTORY
Rev. 1.51 Date Jul 31, 2008
M32C/87 Group Hardware Manual
Description
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All in this manual [pin and bit symbol notation modified] * P5_5(EPM) EPM(P5_5) * P5_0(CE) CE(P5_0) * PM04, PM05 PM05 and PM04 [description modified] * Title of group tables "(current table number / total tables)" added Overview * 1.5 Pin Descriptions Chapter and table title changed to Pin Functions * Table 1.17 Supply voltage for AN0_0 to AN0_7, AN2_0 to AN2_7 modified Special Function Registers (SFRs) * Table 4.20 A value of After Reset column in 03FFh modified Power Supply Voltage Detection Circuit * Figure 6.6 NOTE 1 "internal VDC" changed to "the main voltage regulator"
19 21 46 57 81 91 93 97 97 98
Clock Generation Function * Figure 9.1 "Charge pump" changed to "Loop filter" * Table 9.2 "(The clock keeps running in stop mode)" deleted * 9.1.4 PLL Clock Text partly revised * 9.5.1.3 Low-Speed Mode Text partly revised * 9.5.1.4 Low-Power Consumption Mode Text partly revised * Table 9.6 Values of "-" in bits CM21 and CM17 in the Sub Clock row and in CM17 bit in the On-chip oscillator mode row changed to "0" 99, 102 * Figure 9.14 and 9.15 Note 1 partly modified * Table 9.8 Word "the clock input to the CLKi pin (i = 0 to 6)" changed to "the 101 external clock" * 9.6 System Clock Protect Function and Figure 9.16 Text partly revised 104
110 110 121
Interrupts * 11.5.1 Fixed Vector Table Text partly revised * Table 11.1 Reference in the Watchdog timer row, "Reset" changed to "Voltage detection" * Figure 11.10 "Interrupt request priority level detection result" changed to "Interrupt request level determination" Watchdog Timer * Table 12.2 Values in WDC7 bit in WDC register revised DMAC * Table 13.1 "DMA stop condition" modified Timer * Figure 15.24 NOTE 3 "a 0" deleted * Figure 15.30 NOTE 3 "a 0" deleted Three-Phase Motor Control Timer Function * Figure 16.5 Value in operating mode select bits column "01b" changed to "10b" * Figure 16.7 Function column of ICTB2 register In the sentence "When bits INV01 and INV00 are set to 11b", two cases of when n > 1 and when n = 1 are added subsequently Serial Interfaces * Table 17.7 NOTE 3 Sentence of "The IR bit in the SiRIC register..." deleted * Figure 17.23 "IICM2 = 1" changed to "IICM = 0 or IICM2 = 1" * Figure 17.33 The sentence "m:setting value of the UiBRG register" added
134 139 187 195 201 203
242 243 266
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A/D Converter * Figure 18.1 Figure partly modified
Intelligent I/O * Figure 22.25 Procedure "G1BCR1 register: BTS bit = 1" moved 352 * Figure 22.26 Procedure "G1BCR1 register: BTS bit = 1" moved 353 385-386 * Table 22.18 and Figure 22.51 Baud rate "0001h to FFFDh" changed to "0006h to FFFDh" * Table 22.18 In Receive start condition column, "("L" level)" added 385 * Figure 22.52 In the final step, "("L" level)" added 387 Programmable I/O Ports * 25.2 Port Pi Register (Pi Register, i = 0 to 15) Text partly modified 461 463-465 * Figures 25.1 to 25.3 Figures partly modified Flash Memory * Figure 26.4 NOTE 1 "the FMR01 bit" changed to "bits FMR01 and FMR02", The sentence of "Set it by the ..." deleted 500 * Figure 26.5 NOTE 1 "while the FMR01 bit is set to 1" added * Figure 26.7 In EW1 mode enabled procedure, text partly modified 502 505-508 * 26.3.2.4 Program Command - 26.3.2.7 Read Lock Bit Status Command Text revised partially * Figure 26.12 "to the highest-order even address of block" in the second 508 box deleted 511 * Figure 26.13 "[During...operation]" changed to "[When...is executed]" * Figure 26.15 A wiring line connecting between pin no.7 and pin no.97 515 added 516 * Figure 26.16 "VCC" modified to "VCC2"
498
558 559 561 569 578 579
Usage Notes * Table 28.4 "EXTZ" deleted from Arithmetic row * 28.3 Processor Mode Text partly modified * 28.5.1 Main Clock Text partly modified * 28.9 Timers Text partly modified * 28.15 Programmable I/O Ports Text partly modified * 28.16 Flash Memory Text partly modified
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Hardware Manual Publication Date : Rev.0.20 Rev.1.51 Dec.16, 2004 Jul 31, 2008
Published by : Sales Strategic Planning Div. Renesas Technology Corp.
(c) 2008. Renesas Technology Corp., All rights reserved. Printed in Japan
M32C/87 Group (M32C/87, M32C/87A, M32C/87B) Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan

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